Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013276
Tetsuya Sagawa, Ichiro Komaki, Yuki Okawa, Yasunari Kohashi, H. Kanaya
This paper presents a design of one-sided directional slot antenna for 2.4 GHz band application. The antenna element is composed of a top metal, a dielectric substrate, and a bottom floating metal layer. The antenna element is connected to the coplanar waveguide (CPW) feed line. The simulation and measurement results of the reflection coefficient (S 11) and antenna gain are presented in this paper. The peak gain of the proposed antenna is approximately −4 dB at around 2.4 GHz.
{"title":"Design of 2.4 GHz one-sided directional slot antenna with the main board","authors":"Tetsuya Sagawa, Ichiro Komaki, Yuki Okawa, Yasunari Kohashi, H. Kanaya","doi":"10.1109/EPTC56328.2022.10013276","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013276","url":null,"abstract":"This paper presents a design of one-sided directional slot antenna for 2.4 GHz band application. The antenna element is composed of a top metal, a dielectric substrate, and a bottom floating metal layer. The antenna element is connected to the coplanar waveguide (CPW) feed line. The simulation and measurement results of the reflection coefficient (S 11) and antenna gain are presented in this paper. The peak gain of the proposed antenna is approximately −4 dB at around 2.4 GHz.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126469787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013187
Takshashila Pathade, Yash Agrawal, R. Parekh, Mekala Girish Kumar
Rigorous technology scaling results in embedding billions of transistors and interconnects on to a VLSI chip. This leads to high speed operation and more functionality in integrated circuits (ICs). However there is trade-off between speed and power in VLSI designs. At submicron technology nodes high power consumption becomes a challenging deal. It has been observed from literature that majority of the power dissipation happens in processing elements. One such basic operational component of any processor is arithmetic logic unit (ALU). This unit is designed with the help of combinational digital circuits to perform different arithmetic and logic operations. Data registers are used to hold the operands and result of ALU operation. Hence, for low power application ICs power dissipation at ALU, data registers and interconnections between them need to be taken care. For this purpose this research work has focused on implementing a low power ALU system using graphene based device and interconnects. Carbon nanotube field effect transistors (CNTFETs) are used to design basic logic gates that reduce power consumption of the system while multiwall carbon nanotube bundle (MWCNTB) interconnects are incorporated in connection between data registers that helps to increase speed of the system. 8-bit ALU, and data registers are designed using bottom–up approach, in which each system block is implemented using basic digital circuit. For validation purpose simulated results are compared with CMOS based ALU system. Experimentation is carried out at 22nm technology node. It is speculated from this work that CNTFET are good alternative for CMOS based transistors for low power application as well as higher speed.
{"title":"Effective Low Power ALU Design with Incorporation of MWCNTB On-chip Interconnects","authors":"Takshashila Pathade, Yash Agrawal, R. Parekh, Mekala Girish Kumar","doi":"10.1109/EPTC56328.2022.10013187","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013187","url":null,"abstract":"Rigorous technology scaling results in embedding billions of transistors and interconnects on to a VLSI chip. This leads to high speed operation and more functionality in integrated circuits (ICs). However there is trade-off between speed and power in VLSI designs. At submicron technology nodes high power consumption becomes a challenging deal. It has been observed from literature that majority of the power dissipation happens in processing elements. One such basic operational component of any processor is arithmetic logic unit (ALU). This unit is designed with the help of combinational digital circuits to perform different arithmetic and logic operations. Data registers are used to hold the operands and result of ALU operation. Hence, for low power application ICs power dissipation at ALU, data registers and interconnections between them need to be taken care. For this purpose this research work has focused on implementing a low power ALU system using graphene based device and interconnects. Carbon nanotube field effect transistors (CNTFETs) are used to design basic logic gates that reduce power consumption of the system while multiwall carbon nanotube bundle (MWCNTB) interconnects are incorporated in connection between data registers that helps to increase speed of the system. 8-bit ALU, and data registers are designed using bottom–up approach, in which each system block is implemented using basic digital circuit. For validation purpose simulated results are compared with CMOS based ALU system. Experimentation is carried out at 22nm technology node. It is speculated from this work that CNTFET are good alternative for CMOS based transistors for low power application as well as higher speed.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"550 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117051397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013202
D. Giusti, F. Quaglia, D. Rahul, V. S. Rao, A. Savoia, M. Shaw, D. Wee
In medical ultrasound scanning applications PMUT (Piezo Micromachined Ultrasound transducers) need to be assembled along with the ASIC devices that drive the PMUT devices in transmission and receive the reflected ultrasound signal. To produce a sufficiently high resolution image, a large number of interconnections are required between the PMUT device and the companion ASICs (Application Specific Integrated Circuit) which is done using Cu pillar technology. This integration of Ultrasound Transducers using wafer level bonding between the traducer and the ASIC wafer has already been demonstrated [1]. This process suffers from the problem of yield if a non functioning transducer is bonded to a functioning ASIC or vice versa, and it also requires the ASIC die to be the same dimensions of the traducer die. In this article we will present a solution where known good ASIC die are assembled in a FOWLP (Fan Out wafer level Package) with known good PMUT device assembled using Cu pillar technology allowing for the optimisation of the ASIC for size/yield while still maintain the performance of the transducer required. Verification of the assembly flow has been done using a dummy die to ensure that the fully assembled FOWLP is practicable.
{"title":"Co-packaging of PMUT array with FOWLP ASIC's","authors":"D. Giusti, F. Quaglia, D. Rahul, V. S. Rao, A. Savoia, M. Shaw, D. Wee","doi":"10.1109/EPTC56328.2022.10013202","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013202","url":null,"abstract":"In medical ultrasound scanning applications PMUT (Piezo Micromachined Ultrasound transducers) need to be assembled along with the ASIC devices that drive the PMUT devices in transmission and receive the reflected ultrasound signal. To produce a sufficiently high resolution image, a large number of interconnections are required between the PMUT device and the companion ASICs (Application Specific Integrated Circuit) which is done using Cu pillar technology. This integration of Ultrasound Transducers using wafer level bonding between the traducer and the ASIC wafer has already been demonstrated [1]. This process suffers from the problem of yield if a non functioning transducer is bonded to a functioning ASIC or vice versa, and it also requires the ASIC die to be the same dimensions of the traducer die. In this article we will present a solution where known good ASIC die are assembled in a FOWLP (Fan Out wafer level Package) with known good PMUT device assembled using Cu pillar technology allowing for the optimisation of the ASIC for size/yield while still maintain the performance of the transducer required. Verification of the assembly flow has been done using a dummy die to ensure that the fully assembled FOWLP is practicable.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124306812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013270
Sheng-Chi Hsieh, Hong-Sheng Huang, Wen‐Chun Hsiao, Si-Min Wang, Cheng-Yu Ho
In this paper, we present a dual-band (28/39GHz) 2 by 2 antenna array design on a 10(4+2+4) multi-layer organic substrate bringing broad bandwidth and higher isolation onto a compact AiP module. The antenna structure is a stacking patch antenna with multi-parasitic elements to improve bandwidth. This proposed H-type slot antenna structure can improve interference and isolation between 28 and 39GHz bands. The dimension of dual band AiP is about 13 by 13 mm2. Our AiP design has better than 10 dB return loss in 24.6-29.65 GHz range, with ~5 GHz bandwidth and provides a high-gain (above ~11.5 dBi) radiation pattern for 28GHz applications. For 39GHz band, the antenna has 6 GHz bandwidth and provides a 10 dBi gain between 38–44 GHz. The isolation is greater than 15 dB between low and high band. Finally, the 3D beam steering of 2 by 2 antenna array is simulated with multi-states at 27GHz, with a maximum realized gain of 11.1dBi achieved in the beam direction (θ=28°, Φ=312°) of quadrant IV. It shows that beamforming can be generated at a specific beam direction by controlling the phase of the signal in each antenna element. The compact size antenna structure provides a broadband benefit to approach 28GHz mmWave bands of 3GPP standard for n257, n258, and n261.
{"title":"Design of Dual-Band (28/39GHz) Antenna-in-Package with broad bandwidth for 5G Millimeter-Wave Application","authors":"Sheng-Chi Hsieh, Hong-Sheng Huang, Wen‐Chun Hsiao, Si-Min Wang, Cheng-Yu Ho","doi":"10.1109/EPTC56328.2022.10013270","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013270","url":null,"abstract":"In this paper, we present a dual-band (28/39GHz) 2 by 2 antenna array design on a 10(4+2+4) multi-layer organic substrate bringing broad bandwidth and higher isolation onto a compact AiP module. The antenna structure is a stacking patch antenna with multi-parasitic elements to improve bandwidth. This proposed H-type slot antenna structure can improve interference and isolation between 28 and 39GHz bands. The dimension of dual band AiP is about 13 by 13 mm2. Our AiP design has better than 10 dB return loss in 24.6-29.65 GHz range, with ~5 GHz bandwidth and provides a high-gain (above ~11.5 dBi) radiation pattern for 28GHz applications. For 39GHz band, the antenna has 6 GHz bandwidth and provides a 10 dBi gain between 38–44 GHz. The isolation is greater than 15 dB between low and high band. Finally, the 3D beam steering of 2 by 2 antenna array is simulated with multi-states at 27GHz, with a maximum realized gain of 11.1dBi achieved in the beam direction (θ=28°, Φ=312°) of quadrant IV. It shows that beamforming can be generated at a specific beam direction by controlling the phase of the signal in each antenna element. The compact size antenna structure provides a broadband benefit to approach 28GHz mmWave bands of 3GPP standard for n257, n258, and n261.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"192 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120947573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013248
Hongyun Li, M. Yao, Li Ma, Xuelian Han, Fen Chen, D. Payne, A. Hutzler, Yan Liu
Pressure copper (Cu) sintering paste with high shear strength, high thermal/electrical conductivity, and positive reliability was developed for high-power device die-attach applications. The paste is suitable for different metallizations, e.g., Au, Ag, and Cu. When sintering with 15-20MPa pressure, > 60MPa shear strength was achieved for 3mm x 3mm joints and> 30MPa for 5mm x 5mm joints. After more than 1000 hours (250°C) aging and 3500 cycles TCT (−40°C-17 SOC), the joints exhibited excellent performance without delamination. Shear strength increased with increased TCT cycles. This Cu sintering paste can be used for both dispensing and printing applications. For strong bonding between die and substrate, the sintering process requires N2, H2, formic acid, and a vacuum atmosphere.
{"title":"Pressure Copper Sintering Paste for High-Power Device Die-Attach Applications","authors":"Hongyun Li, M. Yao, Li Ma, Xuelian Han, Fen Chen, D. Payne, A. Hutzler, Yan Liu","doi":"10.1109/EPTC56328.2022.10013248","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013248","url":null,"abstract":"Pressure copper (Cu) sintering paste with high shear strength, high thermal/electrical conductivity, and positive reliability was developed for high-power device die-attach applications. The paste is suitable for different metallizations, e.g., Au, Ag, and Cu. When sintering with 15-20MPa pressure, > 60MPa shear strength was achieved for 3mm x 3mm joints and> 30MPa for 5mm x 5mm joints. After more than 1000 hours (250°C) aging and 3500 cycles TCT (−40°C-17 SOC), the joints exhibited excellent performance without delamination. Shear strength increased with increased TCT cycles. This Cu sintering paste can be used for both dispensing and printing applications. For strong bonding between die and substrate, the sintering process requires N2, H2, formic acid, and a vacuum atmosphere.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121064147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013192
Sung-min Jeon, Sang-Yeob Kim, Sung-Young Lee, Hyun-Jun Park, Minaeva Ra, Monghyun Cho, J. Moon
The bonding wire that connects electrical signals for semiconductor PKG mainly used Au material, but it is being replaced with relatively cheaper material such as Cu and Ag due to a steady rise in Au prices. However, materials such as Cu or Ag to replace Au have a common problem in that the free air ball is oxidized by reaction with oxygen in the atmosphere when forming the free air ball, and thus a spherical free air ball cannot be formed. And since Cu wire has high hardness, there is a limitation in that it cannot completely replace Au wire due to a problem that may cause damage to the Al pad during bonding. In this study, we developed ACA (Au Coated Ag) bonding wire in which Au is plated on the surface of the Ag core which has similar hardness to that of Au to replace the Au wire. When the ACA is melted in the air atmosphere, Au on the wire surface melts and wraps around the molten Ag core to prevent oxidation and also prevents oxygen adsorption to the molten Ag core. Due to this, high surface tension is maintained and a spherical free air ball is formed even in air atmosphere. In addition, in the high-temperature reliability evaluation conducted by bonding the free air ball of ACA formed in the atmospheric atmosphere to the Al pad, the advantage of not forming Kirkendall voids was confirmed because the IMC growth rate of ACA-Al bond was slower than that of the Au-Al bond. Therefore, it was found that the high temperature reliability of the ACA-Al bond was superior to that of the Au-Al bond.
{"title":"High reliability performance of Ag-cored Au coated wire capable of bonding in gas free condition","authors":"Sung-min Jeon, Sang-Yeob Kim, Sung-Young Lee, Hyun-Jun Park, Minaeva Ra, Monghyun Cho, J. Moon","doi":"10.1109/EPTC56328.2022.10013192","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013192","url":null,"abstract":"The bonding wire that connects electrical signals for semiconductor PKG mainly used Au material, but it is being replaced with relatively cheaper material such as Cu and Ag due to a steady rise in Au prices. However, materials such as Cu or Ag to replace Au have a common problem in that the free air ball is oxidized by reaction with oxygen in the atmosphere when forming the free air ball, and thus a spherical free air ball cannot be formed. And since Cu wire has high hardness, there is a limitation in that it cannot completely replace Au wire due to a problem that may cause damage to the Al pad during bonding. In this study, we developed ACA (Au Coated Ag) bonding wire in which Au is plated on the surface of the Ag core which has similar hardness to that of Au to replace the Au wire. When the ACA is melted in the air atmosphere, Au on the wire surface melts and wraps around the molten Ag core to prevent oxidation and also prevents oxygen adsorption to the molten Ag core. Due to this, high surface tension is maintained and a spherical free air ball is formed even in air atmosphere. In addition, in the high-temperature reliability evaluation conducted by bonding the free air ball of ACA formed in the atmospheric atmosphere to the Al pad, the advantage of not forming Kirkendall voids was confirmed because the IMC growth rate of ACA-Al bond was slower than that of the Au-Al bond. Therefore, it was found that the high temperature reliability of the ACA-Al bond was superior to that of the Au-Al bond.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131508907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013191
S. Buenviaje
Tapeless technology of QFN-mr has been a breakthrough in back-end manufacturing. However, back-etching process has some tradeoffs. Surface discoloration at this station has been a chronic defect. In this study, process simulations and material characterizations were performed to determine the root cause. Presence of copper and sulfur was correlated with the high concentration of sulfuric acid through a phenomenon called as copper redeposition.
{"title":"Failure Analysis of QFN Surface Discoloration by Copper Redeposition","authors":"S. Buenviaje","doi":"10.1109/EPTC56328.2022.10013191","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013191","url":null,"abstract":"Tapeless technology of QFN-mr has been a breakthrough in back-end manufacturing. However, back-etching process has some tradeoffs. Surface discoloration at this station has been a chronic defect. In this study, process simulations and material characterizations were performed to determine the root cause. Presence of copper and sulfur was correlated with the high concentration of sulfuric acid through a phenomenon called as copper redeposition.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131885258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013303
F. Tan, Li Wern Chew, L. L. Ong, Sze Lin Mak, Chee Hoong Mah
This paper investigates Signal Integrity - Power Integrity relationship using a dual reference package design and understanding high-speed interconnect circuit's behavior through Jitter Transfer Function. A dual referencing design and modeling approach is introduced to enable maximum noise coupling to differential signal traces. Simulation platform that allows a quick jitter assessment with power noise injection is then built to evaluate the risk of having dual referencing design. Using Peripheral Component Interconnect Express Gen5 interconnects as a case study, the findings shown that mid-frequency power noise matters most to differential interconnects, which turned out to be correlated to its Jitter Transfer Function.
{"title":"Determining System Level Margin through SIPI Co-simulation and Jitter Transfer Function","authors":"F. Tan, Li Wern Chew, L. L. Ong, Sze Lin Mak, Chee Hoong Mah","doi":"10.1109/EPTC56328.2022.10013303","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013303","url":null,"abstract":"This paper investigates Signal Integrity - Power Integrity relationship using a dual reference package design and understanding high-speed interconnect circuit's behavior through Jitter Transfer Function. A dual referencing design and modeling approach is introduced to enable maximum noise coupling to differential signal traces. Simulation platform that allows a quick jitter assessment with power noise injection is then built to evaluate the risk of having dual referencing design. Using Peripheral Component Interconnect Express Gen5 interconnects as a case study, the findings shown that mid-frequency power noise matters most to differential interconnects, which turned out to be correlated to its Jitter Transfer Function.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132021634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013162
D. K. Mishra, V. N. Sekhar, C. Choong, V. S. Rao
With the advancement in the fine-pitch packaging < 10µm and the requirement of heterogeneous integration, chip-to-wafer (C2W) hybrid bonding is widely explored for future needs. Hybrid bonding is widely explored for stacking of multiple dies vertically. For C2W bonding, there is a need to select a proper dielectric material to have a good bond interface. There are broadly two types of dielectric materials explored by the research community, i.e., inorganic such as oxide/SiCN and organics such as polyimides/polymer. This article explored different polymer materials for the hybrid bonding of bottom substrate and top chip with polymer dielectrics. Such a combination of dielectric materials is required for stacking of dies vertically. Initially, four different polymer materials were considered, i.e., #A, #B, #C, and #D, from different suppliers with different curing temperatures and curing times. However, due to the low shear strength of polymer #A and the toxic nature of polymer #C, only polymer #B and #D were further investigated. After the blanket coating and curing, the CMP process was optimized to obtain uniform polymer thickness and required surface roughness < 5 nm with reduced scratches. After the bonding process, the shear strength of the polymers was measured using the die shear test.
{"title":"Evaluation of Polymer Materials for Hybrid Bonding Application","authors":"D. K. Mishra, V. N. Sekhar, C. Choong, V. S. Rao","doi":"10.1109/EPTC56328.2022.10013162","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013162","url":null,"abstract":"With the advancement in the fine-pitch packaging < 10µm and the requirement of heterogeneous integration, chip-to-wafer (C2W) hybrid bonding is widely explored for future needs. Hybrid bonding is widely explored for stacking of multiple dies vertically. For C2W bonding, there is a need to select a proper dielectric material to have a good bond interface. There are broadly two types of dielectric materials explored by the research community, i.e., inorganic such as oxide/SiCN and organics such as polyimides/polymer. This article explored different polymer materials for the hybrid bonding of bottom substrate and top chip with polymer dielectrics. Such a combination of dielectric materials is required for stacking of dies vertically. Initially, four different polymer materials were considered, i.e., #A, #B, #C, and #D, from different suppliers with different curing temperatures and curing times. However, due to the low shear strength of polymer #A and the toxic nature of polymer #C, only polymer #B and #D were further investigated. After the blanket coating and curing, the CMP process was optimized to obtain uniform polymer thickness and required surface roughness < 5 nm with reduced scratches. After the bonding process, the shear strength of the polymers was measured using the die shear test.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133085442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013215
Daniel Ssu-Han Chen, E. Wai, Yi Xuan Yeo, J. Sharma, A. Lal, K. Chai
This work reports a novel approach to form chip-level Au to AuSn bonding below eutectic temperature, and the techniques to investigate the bonding interface quality for gigahertz bulk acoustic wave (BAW) transmission. The primary study involved bonding a $6times 6$ mm MEMS chip with BAW transducer arrays to an $8times 8$ mm silicon substrate by an intermediate Au-AuSn layer deposited by e-beam evaporation. The bonding was achieved by using a custom-made chip bonder where the compression was done at room temperature and later heat treated in an N2 ambient oven at 200°C to form the bond. The bonding quality was evaluated by pulsating the MEMS transducers with 80 ns pulsed-RF signal at 1.465 GHz to generate a packet of bulk acoustic waves and then assess the reflected echo signals. With good interface bonding, it is hypothesized that acoustic energy can propagate through the bonded layer and back to the transducers. By analyzing the received echo signals on the transducer array, we predicted whether acoustic transmission through the bonding interface occurred. Electro-acoustic measurements were done pre/post bonding to compare the pulse-echo signature differences. There are a total of 32 transducer arrays, which cover half of the MEMS chip area and were used to correlate with the CSAM inspection to determine the uniformity of the bond.
本文报道了一种在共晶温度下形成芯片级Au与AuSn键合的新方法，以及研究千兆赫体声波(BAW)传输的键合界面质量的技术。主要研究是通过电子束蒸发沉积的中间Au-AuSn层，将具有BAW换能器阵列的6 × 6$ mm MEMS芯片连接到8 × 8$ mm硅衬底上。通过使用定制的芯片粘结器实现粘合，在室温下进行压缩，然后在200°C的N2环境烤箱中进行热处理以形成粘合。通过在1.465 GHz频率下对MEMS换能器施加80 ns脉冲射频信号，产生一包体声波，然后对反射回波信号进行评估，从而评估键合质量。在良好的界面结合下，假设声能可以通过结合层传播并返回到换能器。通过分析换能器阵列接收到的回波信号，预测了通过结合界面的声传输是否发生。在连接前后进行电声测量，以比较脉冲回波特征的差异。总共有32个传感器阵列，覆盖了一半的MEMS芯片面积，并用于与CSAM检查相关联，以确定键合的均匀性。
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