Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013164
Wang Jie, Richard Chang, Xu Xun, Cai Lile, Chuan-Sheng Foo, R. Pahwa
The 2D-3D metrology is a critical step for in-line inspection and off-line failure analysis. Due to lack of relevant data and complexity of embedded components, identifying and segmenting defects such as voids, pad misalignments in 2D and 3D voxel data has been a challenge in the semiconductor industry. Addressing this problem has the potential to further improve fault detection in this field significantly. This work follows our previously published works in EPTC 2020, ECTC 2021, introducing a cost-effective and non-destructive approach using deep learning and 3D x-ray microscopy. In particular, we apply our 3D object detection and Semi-Supervised Learning (SSL) image segmentation on High Bandwidth memory and logic bumps (HBMs). This paper introduces new detection and segmentation methods that overcomes issues in the current data such as data imbalance or defective bumps. We applied better 2D-3D detection strategy and loss and activation functions for 3D semicon data. We describe the data features, our new approach on 2D-3D scanned data, methods developed to perform better object detection and segmentation to classify each pixel into individual categories such as solders, voids, Cu-Pillars, and Cu-Pad. We analyze in-depth observations from our new models and discuss the benefits and improvements of our revised approach.
{"title":"Improved Bump Detection and Defect Identification for HBMs using Refined Machine Learning Approach","authors":"Wang Jie, Richard Chang, Xu Xun, Cai Lile, Chuan-Sheng Foo, R. Pahwa","doi":"10.1109/EPTC56328.2022.10013164","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013164","url":null,"abstract":"The 2D-3D metrology is a critical step for in-line inspection and off-line failure analysis. Due to lack of relevant data and complexity of embedded components, identifying and segmenting defects such as voids, pad misalignments in 2D and 3D voxel data has been a challenge in the semiconductor industry. Addressing this problem has the potential to further improve fault detection in this field significantly. This work follows our previously published works in EPTC 2020, ECTC 2021, introducing a cost-effective and non-destructive approach using deep learning and 3D x-ray microscopy. In particular, we apply our 3D object detection and Semi-Supervised Learning (SSL) image segmentation on High Bandwidth memory and logic bumps (HBMs). This paper introduces new detection and segmentation methods that overcomes issues in the current data such as data imbalance or defective bumps. We applied better 2D-3D detection strategy and loss and activation functions for 3D semicon data. We describe the data features, our new approach on 2D-3D scanned data, methods developed to perform better object detection and segmentation to classify each pixel into individual categories such as solders, voids, Cu-Pillars, and Cu-Pad. We analyze in-depth observations from our new models and discuss the benefits and improvements of our revised approach.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125215292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In the semiconductor industry, defect detection is very important as it affects performance. In Hybrid Bonding, identifying defect types prior to bonding is critical in determining bonding performance. To overcome this challenge, we propose a solution involving Computer Vision and Deep Learning to accomplish classification of these defects with limited availability of data. With this approach, the defect identification time is reduced, thereby driving faster research and product development.
{"title":"Defect Classification using Deep Learning for Hybrid Bonding Application","authors":"Rahul Reddy Komatireddi, Sachin Dangayach, Prayudi Lianto, Rohith Cherikkallil, Sneha Rupa","doi":"10.1109/EPTC56328.2022.10013145","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013145","url":null,"abstract":"In the semiconductor industry, defect detection is very important as it affects performance. In Hybrid Bonding, identifying defect types prior to bonding is critical in determining bonding performance. To overcome this challenge, we propose a solution involving Computer Vision and Deep Learning to accomplish classification of these defects with limited availability of data. With this approach, the defect identification time is reduced, thereby driving faster research and product development.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132368354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013186
Zhiwen Li, April Joy H. Garete, Zhou Zhou, H. Fan, Elmer Holgado, Ibarra Licup
In this paper, the influence of epoxy molding compound thermomechanical material properties on die top silicon nitride passivation stress during temperature cycling on a high-power surface mount device was studied. The combination of EMC properties (Tg, CTE, and modulus) using different advanced EMCs to achieve lower tensile stress on SiN passivation layer for a high-power SMD was successfully investigated through material characterization, assembly and delamination performance, thermo-mechanical stress simulation, reliability testing, and passivation layer integrity check after TCT. Furthermore, stress relief mechanism related to the mold compound property was proposed based on the results of the study.
{"title":"Thermo-mechanical Characterization and Stress Simulation of Epoxy Molding Compound for a High-Power Package with Silicon Nitride Passivation Layer","authors":"Zhiwen Li, April Joy H. Garete, Zhou Zhou, H. Fan, Elmer Holgado, Ibarra Licup","doi":"10.1109/EPTC56328.2022.10013186","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013186","url":null,"abstract":"In this paper, the influence of epoxy molding compound thermomechanical material properties on die top silicon nitride passivation stress during temperature cycling on a high-power surface mount device was studied. The combination of EMC properties (Tg, CTE, and modulus) using different advanced EMCs to achieve lower tensile stress on SiN passivation layer for a high-power SMD was successfully investigated through material characterization, assembly and delamination performance, thermo-mechanical stress simulation, reliability testing, and passivation layer integrity check after TCT. Furthermore, stress relief mechanism related to the mold compound property was proposed based on the results of the study.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"300 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122776649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013290
F. Che, Yeow Chon Ong, L. Pan, Wei Yu, Hong Wan Ng
Board level reliability, such as solder joint reliability under temperature cycling, is essential requirement for electronic packages. At the design stage, many optimization methods are adopted like geometry, structure, and materials. Finite element analysis (FEA) is a powerful and efficient tool to assess reliability performance. However, FEA simulation is still time-consuming for numerous DOE runs. In this study, combining statistical software and FEA analyses, regression equation is generated for quick assessment on solder joint reliability (SJR) by choosing an example of effect of solder joint shape on SJR performance. Interaction of different parameters can be considered in the equation. This provides an efficient and accurate methodology for design optimization and improvement with saving cycle time for new product introduction (NPI). Such methodology can be extended to other areas to make design-for-reliability more robust and efficient.
{"title":"Study on Solder Joint Shape Impact on Board Level Reliability for Managed NAND Mobile Package","authors":"F. Che, Yeow Chon Ong, L. Pan, Wei Yu, Hong Wan Ng","doi":"10.1109/EPTC56328.2022.10013290","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013290","url":null,"abstract":"Board level reliability, such as solder joint reliability under temperature cycling, is essential requirement for electronic packages. At the design stage, many optimization methods are adopted like geometry, structure, and materials. Finite element analysis (FEA) is a powerful and efficient tool to assess reliability performance. However, FEA simulation is still time-consuming for numerous DOE runs. In this study, combining statistical software and FEA analyses, regression equation is generated for quick assessment on solder joint reliability (SJR) by choosing an example of effect of solder joint shape on SJR performance. Interaction of different parameters can be considered in the equation. This provides an efficient and accurate methodology for design optimization and improvement with saving cycle time for new product introduction (NPI). Such methodology can be extended to other areas to make design-for-reliability more robust and efficient.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122891695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013111
Aditi, Rishabh Agarwal, Rishi Sharma, L. Maiolo, A. Minotti, F. Maita, R. Mukhiya
The paper presents a wafer-level fabrication of a capacitive micromachined ultrasonic transducer (cMUT) using a wafer bonding process and interconnection technique without through silicon vias (TSV)/through glass vias (TGV) process. Anodic bonding technique is utilized for the fabrication and bottom electrode connections are taken by etching the structural layer of Silicon and silicon dioxide. The developed approach is reliable, repeatable and suitable for integration. An element having an array of 125 circular cMUT cell is reported having center frequency of 4.4 MHz.
{"title":"Wafer Level Fabrication of cMUT using Bonding and Interconnection Technique without TSV/TGV","authors":"Aditi, Rishabh Agarwal, Rishi Sharma, L. Maiolo, A. Minotti, F. Maita, R. Mukhiya","doi":"10.1109/EPTC56328.2022.10013111","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013111","url":null,"abstract":"The paper presents a wafer-level fabrication of a capacitive micromachined ultrasonic transducer (cMUT) using a wafer bonding process and interconnection technique without through silicon vias (TSV)/through glass vias (TGV) process. Anodic bonding technique is utilized for the fabrication and bottom electrode connections are taken by etching the structural layer of Silicon and silicon dioxide. The developed approach is reliable, repeatable and suitable for integration. An element having an array of 125 circular cMUT cell is reported having center frequency of 4.4 MHz.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126985168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013157
Jan Joseph Miranda, Marjorie Tinao, Olga Rivera
This study aims to assess and define the appropriate reflow profiling set-up on molded air cavity packages in reference to molded packages during its qualification. The reflow evaluation was done using two reflow profile set-ups: 1) thermocouple on top of the molded package (adapted from JEDEC 020-E industry standard); 2) modified reflow profile set-up where the thermocouple was located on leads (target area during qualification) and in two reflow temperature settings at 245°C and 260°C. Additional reliability tests like moisture resistance test and temperature cycle were also done on the units to check response to package reliability. Results showed that if the reflow profile set-up adapted is putting the thermocouple on top of the designed molded air cavity package with a package thickness of 4.97 mm and top height of 3.15 mm (height with respect to the leads), a delta temperature of around +10°C will be experienced on the lead area. This had led to bubble leak test failure due to mold-lead delamination during reflow process. Taking into consideration the JEP140 guideline for the beaded thermocouple temperature measurement of semiconductor packages, package type and dimension, the package interface or area of interest on a molded air cavity package must have a thermocouple attached to it (i.e., lead interface) and be the basis for the reflow profiling to have an accurate assessment and qualification of the package.
{"title":"Defining the Appropriate Reflow Profiling Set-up for Molded Air Cavity Package","authors":"Jan Joseph Miranda, Marjorie Tinao, Olga Rivera","doi":"10.1109/EPTC56328.2022.10013157","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013157","url":null,"abstract":"This study aims to assess and define the appropriate reflow profiling set-up on molded air cavity packages in reference to molded packages during its qualification. The reflow evaluation was done using two reflow profile set-ups: 1) thermocouple on top of the molded package (adapted from JEDEC 020-E industry standard); 2) modified reflow profile set-up where the thermocouple was located on leads (target area during qualification) and in two reflow temperature settings at 245°C and 260°C. Additional reliability tests like moisture resistance test and temperature cycle were also done on the units to check response to package reliability. Results showed that if the reflow profile set-up adapted is putting the thermocouple on top of the designed molded air cavity package with a package thickness of 4.97 mm and top height of 3.15 mm (height with respect to the leads), a delta temperature of around +10°C will be experienced on the lead area. This had led to bubble leak test failure due to mold-lead delamination during reflow process. Taking into consideration the JEP140 guideline for the beaded thermocouple temperature measurement of semiconductor packages, package type and dimension, the package interface or area of interest on a molded air cavity package must have a thermocouple attached to it (i.e., lead interface) and be the basis for the reflow profiling to have an accurate assessment and qualification of the package.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133519563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013160
Rachel Lee Siew Tan, B. Salam, L. L. Wai
Being in a tropical country, most of us are not used to freezing cold temperature. Working in a cold room environment at harsh temperatures will lower productivity as well as the amount of time we stay in the work environment before we need to take a rest. Furthermore, the change in ambient temperature from the coldroom to outside environment will be a drastic change. Using flexible washable heaters in coldroom apparels can help alleviate this pain point and allow workers in coldroom to feel more comfortable during their working shifts. Furthermore, this will also allow coldroom apparel designers to use alternative materials to improve the comfort level while wearing these garments. In this work, we showcase the collaboration of garment and technology expertise to create heated coldroom apparels.
{"title":"Fabrication of Coldroom Apparels with Flexible Washable Heater","authors":"Rachel Lee Siew Tan, B. Salam, L. L. Wai","doi":"10.1109/EPTC56328.2022.10013160","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013160","url":null,"abstract":"Being in a tropical country, most of us are not used to freezing cold temperature. Working in a cold room environment at harsh temperatures will lower productivity as well as the amount of time we stay in the work environment before we need to take a rest. Furthermore, the change in ambient temperature from the coldroom to outside environment will be a drastic change. Using flexible washable heaters in coldroom apparels can help alleviate this pain point and allow workers in coldroom to feel more comfortable during their working shifts. Furthermore, this will also allow coldroom apparel designers to use alternative materials to improve the comfort level while wearing these garments. In this work, we showcase the collaboration of garment and technology expertise to create heated coldroom apparels.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134072684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013156
G. Tang
Silicon Carbide (SiC) based power modules are widely used in the 5G communications, electric vehicle, aerospace, marine, energy and other industrial fields. Different from the consumer electronics application, automotive grade SiC power devices are operation with higher junction temperature, higher power density, higher switching frequency, and harsher environment, the reliability of the power module is particularly important. Power cycling testing is one of the critical tests used for the reliability assessment of the power semiconductor devices and power module development. Power cycling test periodically applies a current to the devices integrated in the power module. This leads to power loss in the entire module and results in a rise in the temperature of the power devices, as well the ununiformed temperature distribution in the power module. In this paper, thermal analysis is conducted for a 6-in-1 double side cooling SiC power module. The temperature distribution of the power module is simulated and the junction temperature of the SiC power devices in the power module is analyzed. The junction temperature difference under different power cycling test conditions is evaluated, and final test condition of the power cycling test for the developed 6-in-1 power module is proposed.
{"title":"Thermal Analysis and Test Condition Definition of Power cycling Tests for a 6-in-1 Double Side Cooling SiC Power Module","authors":"G. Tang","doi":"10.1109/EPTC56328.2022.10013156","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013156","url":null,"abstract":"Silicon Carbide (SiC) based power modules are widely used in the 5G communications, electric vehicle, aerospace, marine, energy and other industrial fields. Different from the consumer electronics application, automotive grade SiC power devices are operation with higher junction temperature, higher power density, higher switching frequency, and harsher environment, the reliability of the power module is particularly important. Power cycling testing is one of the critical tests used for the reliability assessment of the power semiconductor devices and power module development. Power cycling test periodically applies a current to the devices integrated in the power module. This leads to power loss in the entire module and results in a rise in the temperature of the power devices, as well the ununiformed temperature distribution in the power module. In this paper, thermal analysis is conducted for a 6-in-1 double side cooling SiC power module. The temperature distribution of the power module is simulated and the junction temperature of the SiC power devices in the power module is analyzed. The junction temperature difference under different power cycling test conditions is evaluated, and final test condition of the power cycling test for the developed 6-in-1 power module is proposed.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114424775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013272
Z. Karim, Kay Song, Cliff Sandstrom, Benedict A. San Jose, Kenta Yamazaki, N. Sato, Yuki Nara
Using proprietary cure equipment with unique technology, YES and Deca Technologies partnered with material supplier FujiFilm to demonstrate a rapid cure process that delivers physical, mechanical, thermal, and electrical properties comparable to those resulting from conventional atmospheric cure. This paper describes the ultra-fast curing of FujiFilm's low-temperature polyimide LTC 9300 series. Not only was the cure time reduced to a mere 5 minutes, thereby reducing thermal budget, but also an imidization ratio of >98% as well as better elongation and glass transition temperature were achieved.
{"title":"Reducing the Thermal Budget in Low-Temperature Polyimide Dielectric Cure for Laser Direct Image Patterning in Advanced Backend Applications","authors":"Z. Karim, Kay Song, Cliff Sandstrom, Benedict A. San Jose, Kenta Yamazaki, N. Sato, Yuki Nara","doi":"10.1109/EPTC56328.2022.10013272","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013272","url":null,"abstract":"Using proprietary cure equipment with unique technology, YES and Deca Technologies partnered with material supplier FujiFilm to demonstrate a rapid cure process that delivers physical, mechanical, thermal, and electrical properties comparable to those resulting from conventional atmospheric cure. This paper describes the ultra-fast curing of FujiFilm's low-temperature polyimide LTC 9300 series. Not only was the cure time reduced to a mere 5 minutes, thereby reducing thermal budget, but also an imidization ratio of >98% as well as better elongation and glass transition temperature were achieved.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121727847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013294
Hsiao Hsiang-Yao, David Ho Soon Wee, S. Ps
In this paper, the fabrication process flow and results of a High-Density Fan Out Wafer Level Packaging for Chiplets packaging were presented. Fan-out Chiplets package has a 34.2×26.7 mm2 package size, which includes five layers of 2 µm line and space (L/S) redistribution layers (RDLs). The passivation layer includes 2 µm thickness and the diameter of 3um vias. High density and fine pitch RDLs were used to lay out the Advanced Interface Bus (AlB) connection to numerous channels between chiplets and chiplets. Fan-out chiplets packaging using RDL-1st process flow and a laser de-bonding technique. The fan-out chiplets packaging fabrication process and the Chip to wafer (C2W) assembly process were demonstrated.
{"title":"Process Development of Fan-Out with Multi-layer RDL for Chiplets Packaging","authors":"Hsiao Hsiang-Yao, David Ho Soon Wee, S. Ps","doi":"10.1109/EPTC56328.2022.10013294","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013294","url":null,"abstract":"In this paper, the fabrication process flow and results of a High-Density Fan Out Wafer Level Packaging for Chiplets packaging were presented. Fan-out Chiplets package has a 34.2×26.7 mm2 package size, which includes five layers of 2 µm line and space (L/S) redistribution layers (RDLs). The passivation layer includes 2 µm thickness and the diameter of 3um vias. High density and fine pitch RDLs were used to lay out the Advanced Interface Bus (AlB) connection to numerous channels between chiplets and chiplets. Fan-out chiplets packaging using RDL-1st process flow and a laser de-bonding technique. The fan-out chiplets packaging fabrication process and the Chip to wafer (C2W) assembly process were demonstrated.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114947901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：