Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013307
Jiale Peng, Wei-Hao Lan, Fulong Wei, Chao Deng, Xiaobing Luo
The logging tools detecting the hydrocarbon resources are obliged to operate for several hours under high temperature downhole environment. However, the internal electronics, especially the high-power electronics, cannot function for such long time limited by their temperature resistance. In previous thermal management, the heat conduction thermal resistance between the heat source and the PCM was high, resulting in a large temperature difference between them and the operating time of the electronics limited. To solve this problem, a thermal management for high-power downhole electronics combining liquid cooling with PCM under high temperature environment was proposed. Numerical simulation of the proposed thermal management method was calculated by finite element method. The results show that compared to conventional thermal management, the final temperature of the heat source is reduced by 29°C, the average equivalent thermal resistance is reduced by more than 0.5°C/W, and the PCM utilization is improved by 1.9%. Moreover, the heat flow from the heat source to PCM is enhanced compared to the convention thermal management.
{"title":"Thermal management for high-power downhole electronics using liquid cooling and PCM under high temperature environment","authors":"Jiale Peng, Wei-Hao Lan, Fulong Wei, Chao Deng, Xiaobing Luo","doi":"10.1109/EPTC56328.2022.10013307","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013307","url":null,"abstract":"The logging tools detecting the hydrocarbon resources are obliged to operate for several hours under high temperature downhole environment. However, the internal electronics, especially the high-power electronics, cannot function for such long time limited by their temperature resistance. In previous thermal management, the heat conduction thermal resistance between the heat source and the PCM was high, resulting in a large temperature difference between them and the operating time of the electronics limited. To solve this problem, a thermal management for high-power downhole electronics combining liquid cooling with PCM under high temperature environment was proposed. Numerical simulation of the proposed thermal management method was calculated by finite element method. The results show that compared to conventional thermal management, the final temperature of the heat source is reduced by 29°C, the average equivalent thermal resistance is reduced by more than 0.5°C/W, and the PCM utilization is improved by 1.9%. Moreover, the heat flow from the heat source to PCM is enhanced compared to the convention thermal management.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131988644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013182
Hemanth Kumar Cheemalamarri, Darshini Senthilkumar, B. C. Rao
The TSV technology has become the key driver for advanced electronic packages such as 3D memory and BSI (backside illuminated image) sensor applications. Among the various methods of integrating the TSVs (via first, via middle, and via last, via after bonding), via last, or via after bonding has gained much interest. This method helps process integration by reducing the impact on the BEOL processing and does not demand a TSV reveal for wafer thinning. However, an efficient TSV's bottom oxide etch back is necessary for making contact with the underneath interconnect layer. One potential challenge in TSV etch is in protecting the top corner of TSV liner oxide during etch back for better electrical reliability. It is due to the lower etch rate at the bottom of the via compared to the TSV top corner. This work focuses on process methodology to increase the bottom oxide etch rate with reduced TSV top corner oxide etch rate. The oxide etch back process has been optimized with a fluorine-deficient regime to minimize the etch rate difference. The optimized process suggests that - adding a slight amount of O2 with Ar-diluted C4F8 plasma helps protect the top corner oxide by depositing a passivation layer.
{"title":"Through Silicon Via Oxide Etch Back for Via-last Integration Scheme","authors":"Hemanth Kumar Cheemalamarri, Darshini Senthilkumar, B. C. Rao","doi":"10.1109/EPTC56328.2022.10013182","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013182","url":null,"abstract":"The TSV technology has become the key driver for advanced electronic packages such as 3D memory and BSI (backside illuminated image) sensor applications. Among the various methods of integrating the TSVs (via first, via middle, and via last, via after bonding), via last, or via after bonding has gained much interest. This method helps process integration by reducing the impact on the BEOL processing and does not demand a TSV reveal for wafer thinning. However, an efficient TSV's bottom oxide etch back is necessary for making contact with the underneath interconnect layer. One potential challenge in TSV etch is in protecting the top corner of TSV liner oxide during etch back for better electrical reliability. It is due to the lower etch rate at the bottom of the via compared to the TSV top corner. This work focuses on process methodology to increase the bottom oxide etch rate with reduced TSV top corner oxide etch rate. The oxide etch back process has been optimized with a fluorine-deficient regime to minimize the etch rate difference. The optimized process suggests that - adding a slight amount of O2 with Ar-diluted C4F8 plasma helps protect the top corner oxide by depositing a passivation layer.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133658922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013224
Marty Lorgino D. Pulutan, Matthew M. Fernandez, Janice Estolano
High power applications have driven the package assembly to design devices into more robust packaging at lower manufacturing cost that could survive stringent reliability tests with no consequent failures such as delamination. For molded packages, the industry slowly shift to non-plated bare Cu leadframes for higher mold adhesion as the organic compound has higher affinity to Cu surfaces. However, the risk of oxide formation on top surface is deemed detrimental especially when exposed to series of heat processes along with material staging time in an uncontrolled environment. Plasma treatment prior mold has been introduced as dry method for isotropic and homogenous cleaning of surface impurities on metal surfaces. Different plasma chemistries are being utilized for different applications on device packaging with varying surface alteration effect. Plasma cleaning has two different mechanisms-through physical sputtering and through chemical reaction. Pure Ar plasma are widely used for surface activation and has prominent sputtering effect which causes micro to submicron surface roughening. However, material redeposition of etched particles from the topmost layer are commonly encountered which causes performance failure such as leakage current. The pure Ar plasma composition could not also completely remove the unwanted oxide layers since inert Ar ion species are highly unreactive and thus has a less effective surface cleaning. On the other hand, the mixed gas plasma chemistry with a certain percent amount of Hydrogen introduces minimal to no surface alteration as the primary reactive Hydrogen radicals react with organic layers producing volatile hydrides byproduct during chemical reaction with oxides thus cleaning the surface and exposing the base metal [1]. The study focused on surface characterization of non-roughened and oxidation-roughened bare Cu leadframes in response of 95:5 $text{Ar}+mathrm{H}2$ strip plasma to assess the effectiveness and define optimized parameters for efficient oxide surface cleaning of mixed gas plasma chemistry in response to 0-hour and post reliability mold-to-Cu surface interface delamination and test performance.
{"title":"The Effect of Mixed Gas Ar+H2 Strip Plasma onto the Non-Roughened and Oxidation-Roughened Bare Cu Leadframe Surfaces","authors":"Marty Lorgino D. Pulutan, Matthew M. Fernandez, Janice Estolano","doi":"10.1109/EPTC56328.2022.10013224","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013224","url":null,"abstract":"High power applications have driven the package assembly to design devices into more robust packaging at lower manufacturing cost that could survive stringent reliability tests with no consequent failures such as delamination. For molded packages, the industry slowly shift to non-plated bare Cu leadframes for higher mold adhesion as the organic compound has higher affinity to Cu surfaces. However, the risk of oxide formation on top surface is deemed detrimental especially when exposed to series of heat processes along with material staging time in an uncontrolled environment. Plasma treatment prior mold has been introduced as dry method for isotropic and homogenous cleaning of surface impurities on metal surfaces. Different plasma chemistries are being utilized for different applications on device packaging with varying surface alteration effect. Plasma cleaning has two different mechanisms-through physical sputtering and through chemical reaction. Pure Ar plasma are widely used for surface activation and has prominent sputtering effect which causes micro to submicron surface roughening. However, material redeposition of etched particles from the topmost layer are commonly encountered which causes performance failure such as leakage current. The pure Ar plasma composition could not also completely remove the unwanted oxide layers since inert Ar ion species are highly unreactive and thus has a less effective surface cleaning. On the other hand, the mixed gas plasma chemistry with a certain percent amount of Hydrogen introduces minimal to no surface alteration as the primary reactive Hydrogen radicals react with organic layers producing volatile hydrides byproduct during chemical reaction with oxides thus cleaning the surface and exposing the base metal [1]. The study focused on surface characterization of non-roughened and oxidation-roughened bare Cu leadframes in response of 95:5 $text{Ar}+mathrm{H}2$ strip plasma to assess the effectiveness and define optimized parameters for efficient oxide surface cleaning of mixed gas plasma chemistry in response to 0-hour and post reliability mold-to-Cu surface interface delamination and test performance.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114932248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013294
Hsiao Hsiang-Yao, David Ho Soon Wee, S. Ps
In this paper, the fabrication process flow and results of a High-Density Fan Out Wafer Level Packaging for Chiplets packaging were presented. Fan-out Chiplets package has a 34.2×26.7 mm2 package size, which includes five layers of 2 µm line and space (L/S) redistribution layers (RDLs). The passivation layer includes 2 µm thickness and the diameter of 3um vias. High density and fine pitch RDLs were used to lay out the Advanced Interface Bus (AlB) connection to numerous channels between chiplets and chiplets. Fan-out chiplets packaging using RDL-1st process flow and a laser de-bonding technique. The fan-out chiplets packaging fabrication process and the Chip to wafer (C2W) assembly process were demonstrated.
{"title":"Process Development of Fan-Out with Multi-layer RDL for Chiplets Packaging","authors":"Hsiao Hsiang-Yao, David Ho Soon Wee, S. Ps","doi":"10.1109/EPTC56328.2022.10013294","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013294","url":null,"abstract":"In this paper, the fabrication process flow and results of a High-Density Fan Out Wafer Level Packaging for Chiplets packaging were presented. Fan-out Chiplets package has a 34.2×26.7 mm2 package size, which includes five layers of 2 µm line and space (L/S) redistribution layers (RDLs). The passivation layer includes 2 µm thickness and the diameter of 3um vias. High density and fine pitch RDLs were used to lay out the Advanced Interface Bus (AlB) connection to numerous channels between chiplets and chiplets. Fan-out chiplets packaging using RDL-1st process flow and a laser de-bonding technique. The fan-out chiplets packaging fabrication process and the Chip to wafer (C2W) assembly process were demonstrated.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114947901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013272
Z. Karim, Kay Song, Cliff Sandstrom, Benedict A. San Jose, Kenta Yamazaki, N. Sato, Yuki Nara
Using proprietary cure equipment with unique technology, YES and Deca Technologies partnered with material supplier FujiFilm to demonstrate a rapid cure process that delivers physical, mechanical, thermal, and electrical properties comparable to those resulting from conventional atmospheric cure. This paper describes the ultra-fast curing of FujiFilm's low-temperature polyimide LTC 9300 series. Not only was the cure time reduced to a mere 5 minutes, thereby reducing thermal budget, but also an imidization ratio of >98% as well as better elongation and glass transition temperature were achieved.
{"title":"Reducing the Thermal Budget in Low-Temperature Polyimide Dielectric Cure for Laser Direct Image Patterning in Advanced Backend Applications","authors":"Z. Karim, Kay Song, Cliff Sandstrom, Benedict A. San Jose, Kenta Yamazaki, N. Sato, Yuki Nara","doi":"10.1109/EPTC56328.2022.10013272","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013272","url":null,"abstract":"Using proprietary cure equipment with unique technology, YES and Deca Technologies partnered with material supplier FujiFilm to demonstrate a rapid cure process that delivers physical, mechanical, thermal, and electrical properties comparable to those resulting from conventional atmospheric cure. This paper describes the ultra-fast curing of FujiFilm's low-temperature polyimide LTC 9300 series. Not only was the cure time reduced to a mere 5 minutes, thereby reducing thermal budget, but also an imidization ratio of >98% as well as better elongation and glass transition temperature were achieved.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121727847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013237
N. Jaafar, C. Choong
The most popular first - level interconnection technologies used for the connection of chip to chip and chip to substrate are Wire Bonding and Flip Chip. As the semiconductor packaging requirement leading toward the finer pitch, higher pin count, multi -stack devices, there is an increase in the challenges for wire bonding process. With increase number of bond pads, wire bonding on multi -stack devices platform which lead to complex design of the layout that causes wire to cross, bundle and touch each other after molding process due to wire sweep effect, insulated bonding wire, X-Wire™ was introduced. X-Wire™ Technology is a patented nano-scale thin film dielectric coating that is applied onto the bare wire via proprietary application process. This coating provides a level of electrical insulation that permits bonding wires to cross and contact within electronic devices without risk of short-circuiting. In this studies, selection of capillary and parameters optimization of the FAB size, ball size range of 39µm+/-5 µm will be achieved with bond pad size 50µm by 50µm using the 0.7mils X-Wire™. The wire bonder used for this evaluation and study is ASM Extreme Eagle. Dage Bond Tester Series 4000 will be used to collect the ball shear and wire pull measurement. Failure mode will be analyse using high power scope and SEM and results will be shared in the full paper.
{"title":"Establishment of Highly Dense Wire Bonding with Insulated Au Wire","authors":"N. Jaafar, C. Choong","doi":"10.1109/EPTC56328.2022.10013237","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013237","url":null,"abstract":"The most popular first - level interconnection technologies used for the connection of chip to chip and chip to substrate are Wire Bonding and Flip Chip. As the semiconductor packaging requirement leading toward the finer pitch, higher pin count, multi -stack devices, there is an increase in the challenges for wire bonding process. With increase number of bond pads, wire bonding on multi -stack devices platform which lead to complex design of the layout that causes wire to cross, bundle and touch each other after molding process due to wire sweep effect, insulated bonding wire, X-Wire™ was introduced. X-Wire™ Technology is a patented nano-scale thin film dielectric coating that is applied onto the bare wire via proprietary application process. This coating provides a level of electrical insulation that permits bonding wires to cross and contact within electronic devices without risk of short-circuiting. In this studies, selection of capillary and parameters optimization of the FAB size, ball size range of 39µm+/-5 µm will be achieved with bond pad size 50µm by 50µm using the 0.7mils X-Wire™. The wire bonder used for this evaluation and study is ASM Extreme Eagle. Dage Bond Tester Series 4000 will be used to collect the ball shear and wire pull measurement. Failure mode will be analyse using high power scope and SEM and results will be shared in the full paper.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128174324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013127
K. B. Zheng, Sun Mei, Sharon Lim Pei Siang, Jong Ming Chinq, Lau Boon Long, Zhou Lin, Lim Teck Guan
Fan-Out Wafer-Level-Packaging (FOWLP) to PCB transition enables the scaling of an antenna element into an array at a PCB level. This paper presents key design steps ensuring the FOWLP package-to-board transition structure's performance. The back-to-back package-to-board transition structure has a maximum simulated insertion loss of 0.88 dB and a minimum return loss of 11.73 dB over 20 to 35 GHz. A prototype was also fabricated for further characterization.
{"title":"RF Performance of FOWLP to PCB Board Transition","authors":"K. B. Zheng, Sun Mei, Sharon Lim Pei Siang, Jong Ming Chinq, Lau Boon Long, Zhou Lin, Lim Teck Guan","doi":"10.1109/EPTC56328.2022.10013127","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013127","url":null,"abstract":"Fan-Out Wafer-Level-Packaging (FOWLP) to PCB transition enables the scaling of an antenna element into an array at a PCB level. This paper presents key design steps ensuring the FOWLP package-to-board transition structure's performance. The back-to-back package-to-board transition structure has a maximum simulated insertion loss of 0.88 dB and a minimum return loss of 11.73 dB over 20 to 35 GHz. A prototype was also fabricated for further characterization.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128389207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013204
L. Pan, F. Che, Yeow Chon Ong, H. Ng, K. Sinha, Wren Chen
As 5G mobile products become ubiquitous, mobile memory and storage performance must also scale to keep up with fast data download speeds. Along with mobile technology towards multifunction, design-for-reliability for mobile becomes challenging and essential. Among of reliability issues, the solder joint reliability of electronic package plays a more important role than before. This study focuses on temperature cycling (TC) solder joint reliability (SJR) performance of Universal Flash Storage (UFS) 3.1 fine pitch BGA (FBGA) package which enables faster read and write performance. Numerical studies were conducted by using the finite element analysis (FEA) technique to investigate the impact of partial underfill on SJR performance. Firstly, three patterns with no-underfill, partial underfill and full underfill are investigated in this study. Secondly, involved the thermal reliability performance of three different types of reworkable and non-reworkable underfill to compare CTE and Tg effect. This paper uncovered the reworkable underfill with high CTE may contribute negatively to thermal cycling SJR reliability. Reworkable underfill with high CTE aims to achieve excellent drop test performance with low manufacture cost. This trade-off may increase potential SJR failure risk under temperature cycling condition.
随着5G移动产品的普及，移动内存和存储性能也必须扩展，以跟上快速的数据下载速度。随着移动技术向多功能发展，移动设备的可靠性设计变得具有挑战性和必要性。在可靠性问题中，电子封装的焊点可靠性扮演着越来越重要的角色。本文研究了Universal Flash Storage (UFS) 3.1 fine pitch BGA (FBGA)封装的温度循环(TC)焊点可靠性(SJR)性能，该封装可实现更快的读写性能。采用有限元分析技术，研究了局部下填对SJR性能的影响。首先，研究了无底填、部分底填和完全底填三种模式。其次，对三种不同类型的可修和不可修底填土的热可靠性性能进行比较，比较CTE和Tg效应。本文揭示了高CTE可重填底土对SJR热循环可靠性的不利影响。具有高CTE的可重构底填料旨在以较低的制造成本获得优异的跌落测试性能。这种权衡可能会增加SJR在温度循环条件下的潜在失效风险。
{"title":"Partial Underfill Impact Study on Solder Joint Reliability in Smartphone Application","authors":"L. Pan, F. Che, Yeow Chon Ong, H. Ng, K. Sinha, Wren Chen","doi":"10.1109/EPTC56328.2022.10013204","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013204","url":null,"abstract":"As 5G mobile products become ubiquitous, mobile memory and storage performance must also scale to keep up with fast data download speeds. Along with mobile technology towards multifunction, design-for-reliability for mobile becomes challenging and essential. Among of reliability issues, the solder joint reliability of electronic package plays a more important role than before. This study focuses on temperature cycling (TC) solder joint reliability (SJR) performance of Universal Flash Storage (UFS) 3.1 fine pitch BGA (FBGA) package which enables faster read and write performance. Numerical studies were conducted by using the finite element analysis (FEA) technique to investigate the impact of partial underfill on SJR performance. Firstly, three patterns with no-underfill, partial underfill and full underfill are investigated in this study. Secondly, involved the thermal reliability performance of three different types of reworkable and non-reworkable underfill to compare CTE and Tg effect. This paper uncovered the reworkable underfill with high CTE may contribute negatively to thermal cycling SJR reliability. Reworkable underfill with high CTE aims to achieve excellent drop test performance with low manufacture cost. This trade-off may increase potential SJR failure risk under temperature cycling condition.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129629788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013225
Haoran Chen, T. Lim, G. Tang
This paper studies the thermal characteristics of a compact 2.5D heterogeneous integrated platform by numerical simulation. The platform contains a silicon interposer carrying high-density power amplifiers made of gallium nitride on silicon carbide (GaN-on-SiC) and temperature sensitive passive filter dies. Comparing with traditional wire bonding method, the flip chip method suspended by metal stub enjoys greater benefits on RF performance. However, thermal issue becomes more challenging in this configuration due to the improper thermal transferring path. This work numerically studies the metal casing as a cooling solution and explores the potential capabilities in 2.5D heterogeneous integrated platform based on a full-scale 3D finite element model. Temperature distributions across the package in different conditions are presented to reveal the effect of the casing. And the parametric study results guide the thermal design of such casing in practice. The information in this paper could be helpful in the thermal design of 2.5D heterogeneous integrated platform for RF front end.
{"title":"Thermal modelling, characterization and optimization of 2.5D heterogeneous integrated platform for RF front end","authors":"Haoran Chen, T. Lim, G. Tang","doi":"10.1109/EPTC56328.2022.10013225","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013225","url":null,"abstract":"This paper studies the thermal characteristics of a compact 2.5D heterogeneous integrated platform by numerical simulation. The platform contains a silicon interposer carrying high-density power amplifiers made of gallium nitride on silicon carbide (GaN-on-SiC) and temperature sensitive passive filter dies. Comparing with traditional wire bonding method, the flip chip method suspended by metal stub enjoys greater benefits on RF performance. However, thermal issue becomes more challenging in this configuration due to the improper thermal transferring path. This work numerically studies the metal casing as a cooling solution and explores the potential capabilities in 2.5D heterogeneous integrated platform based on a full-scale 3D finite element model. Temperature distributions across the package in different conditions are presented to reveal the effect of the casing. And the parametric study results guide the thermal design of such casing in practice. The information in this paper could be helpful in the thermal design of 2.5D heterogeneous integrated platform for RF front end.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130781666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013180
B. Ayoub, S. Lhostis, S. Moreau, E. Souchier, E. Deloffre, S. Mermoz, Maria Gabriela Gusmão Cacho, Norah Szekely, Christelle Rey, Ece Aybeke, V. Gredy, P. Lamontagne, O. Thomas, H. Frémont
With hybrid bonding pitch reduction, many challenges are arising especially the ones related to Cu-Cu connections with submicron Cu pads. A methodology is presented here to achieve submicron hybrid bonding pitch starting from single Cu pad thermomechanical behavior study to quantifying Cu-Cu contact resistivity. Depending on the single crystal Cu orientation, several nanometers difference in total deformation is obtained. The Cu dishing limit should be restricted with respect to the lowest deformation. Contact resistivity studies allow to further refine the Cu dishing to get a contribution of contact resistivity below $10^{-11} Omega.text{cm}^{2}$. By respecting these criteria, a 100 % yield was achieved down to 0.81 µm Cu/SiO2 hybrid bonding pitch. A successful method for the capacitance increase compensation with pitch reduction is also presented based on the adaptation of the geometric parameters of the hybrid bonding interconnects.
随着杂化键距的减小，出现了许多挑战，特别是与亚微米铜衬垫的Cu-Cu连接相关的挑战。本文提出了一种从单铜焊盘热力学行为研究到Cu-Cu接触电阻率量化的亚微米级杂化键距实现方法。根据单晶Cu取向的不同，总变形有几纳米的差异。应以最小变形为限制铜盘的极限。接触电阻率研究允许进一步改进Cu碟形，以获得低于$10^{-11} Omega.text{cm}^{2}$的接触电阻率贡献。通过遵守这些标准，在0.81 μ m Cu/SiO2杂化键合间距下实现了100%的产率。提出了一种基于杂化键合互连几何参数自适应的减节电容补偿方法。
{"title":"Sub $1 mu mathrm{m}$ Pitch Achievement for Cu/SiO2 Hybrid Bonding","authors":"B. Ayoub, S. Lhostis, S. Moreau, E. Souchier, E. Deloffre, S. Mermoz, Maria Gabriela Gusmão Cacho, Norah Szekely, Christelle Rey, Ece Aybeke, V. Gredy, P. Lamontagne, O. Thomas, H. Frémont","doi":"10.1109/EPTC56328.2022.10013180","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013180","url":null,"abstract":"With hybrid bonding pitch reduction, many challenges are arising especially the ones related to Cu-Cu connections with submicron Cu pads. A methodology is presented here to achieve submicron hybrid bonding pitch starting from single Cu pad thermomechanical behavior study to quantifying Cu-Cu contact resistivity. Depending on the single crystal Cu orientation, several nanometers difference in total deformation is obtained. The Cu dishing limit should be restricted with respect to the lowest deformation. Contact resistivity studies allow to further refine the Cu dishing to get a contribution of contact resistivity below $10^{-11} Omega.text{cm}^{2}$. By respecting these criteria, a 100 % yield was achieved down to 0.81 µm Cu/SiO2 hybrid bonding pitch. A successful method for the capacitance increase compensation with pitch reduction is also presented based on the adaptation of the geometric parameters of the hybrid bonding interconnects.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129687054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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