Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508309
A. Townley, Paul Swirhun, D. Titz, A. Bisognin, F. Gianesello, R. Pilard, C. Luxey, A. Niknejad
A prototype phased-array IC with four transmitters, four receivers, and integrated LO generation was designed and fabricated in a 130nm SiGe BiCMOS technology. Including LO phase shifter power consumption, the transmit array consumes 71mW per element with a per-element output power of +6.4dBm at 94GHz. The receiver array consumes 56mW per element, and achieves an RX element noise figure of 12.5dB at 94GHz. Integrated LO generation includes a 47GHz VCO, 2× frequency multiplier, 94GHz LO buffers, and a 32× CML divider chain. The transceiver has been integrated into a flip chip antenna module with four transmit and four receive antennas, and achieves TX and RX beam steering over a scan angle range of ±20°. Including LO and bias overhead power, the array has improved per-element power consumption compared with state-of-the-art 94GHz arrays, consuming only 106mW per TX channel and 91mW per RX channel, while achieving comparable performance and levels of integration.
{"title":"A 94GHz 4TX-4RX phased-array for FMCW radar with integrated LO and flip-chip antenna package","authors":"A. Townley, Paul Swirhun, D. Titz, A. Bisognin, F. Gianesello, R. Pilard, C. Luxey, A. Niknejad","doi":"10.1109/RFIC.2016.7508309","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508309","url":null,"abstract":"A prototype phased-array IC with four transmitters, four receivers, and integrated LO generation was designed and fabricated in a 130nm SiGe BiCMOS technology. Including LO phase shifter power consumption, the transmit array consumes 71mW per element with a per-element output power of +6.4dBm at 94GHz. The receiver array consumes 56mW per element, and achieves an RX element noise figure of 12.5dB at 94GHz. Integrated LO generation includes a 47GHz VCO, 2× frequency multiplier, 94GHz LO buffers, and a 32× CML divider chain. The transceiver has been integrated into a flip chip antenna module with four transmit and four receive antennas, and achieves TX and RX beam steering over a scan angle range of ±20°. Including LO and bias overhead power, the array has improved per-element power consumption compared with state-of-the-art 94GHz arrays, consuming only 106mW per TX channel and 91mW per RX channel, while achieving comparable performance and levels of integration.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133808116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508289
Chenxi Huang, Yongdong Chen, Tong Zhang, V. Sathe, J. Rudell
This paper describes a single-ended switch-capacitor harmonic-rejection power amplifier to operate in the 915 MHz ISM band for ZigBee applications. A multipath feed-forward harmonic-rejection technique is employed to suppress the 2nd/3rd/4th harmonics of the switch-capacitor power amplifier (PA) by 48/17/24 dB, respectively. The measured PA peak drain efficiency is 43% at a peak output power of 8.9dBm with the harmonic-rejection enabled. This PA was implemented in a 40nm TSMC CMOS process with an active area of 180μm×700μm.
{"title":"A 40nm CMOS single-ended switch-capacitor harmonic-rejection power amplifier for ZigBee applications","authors":"Chenxi Huang, Yongdong Chen, Tong Zhang, V. Sathe, J. Rudell","doi":"10.1109/RFIC.2016.7508289","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508289","url":null,"abstract":"This paper describes a single-ended switch-capacitor harmonic-rejection power amplifier to operate in the 915 MHz ISM band for ZigBee applications. A multipath feed-forward harmonic-rejection technique is employed to suppress the 2nd/3rd/4th harmonics of the switch-capacitor power amplifier (PA) by 48/17/24 dB, respectively. The measured PA peak drain efficiency is 43% at a peak output power of 8.9dBm with the harmonic-rejection enabled. This PA was implemented in a 40nm TSMC CMOS process with an active area of 180μm×700μm.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132379794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508283
A. H. M. Shirazi, Amir Nikpaik, S. Mirabbasi, S. Shekhar
Achieving high output power in (sub-)THz voltage-controlled oscillators (VCOs) has been a severe design challenge in CMOS technology. In this work, an architecture for coupled terahertz (THz) VCOs is presented. The architecture utilizes four coupled triple-push VCOs and combines the generated third harmonic currents using slow-wave coplanar waveguide (S-CPW) at 300 GHz. Coupling four cores increases output power, and use of S-CPW reduces the loss and increases the quality factor of the VCO tank. It is shown that using S-CPW results in ~2.6 dB of lower loss as compared to the conventional CPW or grounded-CPW (GCPW) structures. The VCO is tuned using parasitic tuning technique and achieves 1.7% frequency tuning range (FTR). The proposed structure is designed and fabricated in a 65-nm bulk CMOS process. The measured peak output power of the 295-to-301 GHz VCO is 0.9 dBm (≈1.25 mW) at 300 GHz while consuming 235 mW (with a DC to RF efficiency of 0.52%).
{"title":"A quad-core-coupled triple-push 295-to-301 GHz source with 1.25 mW peak output power in 65nm CMOS using slow-wave effect","authors":"A. H. M. Shirazi, Amir Nikpaik, S. Mirabbasi, S. Shekhar","doi":"10.1109/RFIC.2016.7508283","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508283","url":null,"abstract":"Achieving high output power in (sub-)THz voltage-controlled oscillators (VCOs) has been a severe design challenge in CMOS technology. In this work, an architecture for coupled terahertz (THz) VCOs is presented. The architecture utilizes four coupled triple-push VCOs and combines the generated third harmonic currents using slow-wave coplanar waveguide (S-CPW) at 300 GHz. Coupling four cores increases output power, and use of S-CPW reduces the loss and increases the quality factor of the VCO tank. It is shown that using S-CPW results in ~2.6 dB of lower loss as compared to the conventional CPW or grounded-CPW (GCPW) structures. The VCO is tuned using parasitic tuning technique and achieves 1.7% frequency tuning range (FTR). The proposed structure is designed and fabricated in a 65-nm bulk CMOS process. The measured peak output power of the 295-to-301 GHz VCO is 0.9 dBm (≈1.25 mW) at 300 GHz while consuming 235 mW (with a DC to RF efficiency of 0.52%).","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133388055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508310
Q. Zhong, W. Choi, N. Sharma, Z. Ahmad, J. P. McMillan, C. Neese, F. D. De Lucia, K. O
A fully integrated CMOS receiver for mm-wave rotational spectroscopy is demonstrated. The receiver consists of a sub-harmonic mixer based receiving front-end which down-converts 225-280 GHz RF input to 20 GHz intermediate frequency, a 20-GHz AM demodulator followed by a baseband buffer amplifier, and an 122-139 GHz local oscillator chain which is comprised of a frequency quadrupler and a driver amplifier. The receiver exhibits responsivity of 400-1200 kV/W and noise equivalent power of 0.4 to 1.2 pW/√Hz from 225 to 280 GHz. Detection of ethanol, propionitrile (EtCN), acetonitrile (CH3CN) and acetone in a mixture is demonstrated using the receiver in a rotational spectrometer setup. This is the first demonstration that a CMOS receiver can be used for rotational spectroscopy and that a CMOS circuit can support an existing application at frequencies above 200 GHz.
{"title":"225–280 GHz receiver for rotational spectroscopy","authors":"Q. Zhong, W. Choi, N. Sharma, Z. Ahmad, J. P. McMillan, C. Neese, F. D. De Lucia, K. O","doi":"10.1109/RFIC.2016.7508310","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508310","url":null,"abstract":"A fully integrated CMOS receiver for mm-wave rotational spectroscopy is demonstrated. The receiver consists of a sub-harmonic mixer based receiving front-end which down-converts 225-280 GHz RF input to 20 GHz intermediate frequency, a 20-GHz AM demodulator followed by a baseband buffer amplifier, and an 122-139 GHz local oscillator chain which is comprised of a frequency quadrupler and a driver amplifier. The receiver exhibits responsivity of 400-1200 kV/W and noise equivalent power of 0.4 to 1.2 pW/√Hz from 225 to 280 GHz. Detection of ethanol, propionitrile (EtCN), acetonitrile (CH3CN) and acetone in a mixture is demonstrated using the receiver in a rotational spectrometer setup. This is the first demonstration that a CMOS receiver can be used for rotational spectroscopy and that a CMOS circuit can support an existing application at frequencies above 200 GHz.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130204037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508238
Nguyen Ngoc Mai-Khanh, T. Iizuka, K. Asada
This paper presents a new microwave pulse generator based on a positive feedback scheme. The positive feedback is proposed to produce a quick regenerated trigger switch to spark an LC circuit and then generate a shock pulse. The proposed circuit does not need any edge-sharpener circuit or over-sized transistors and hence requires a small chip area. A testing prototype is fabricated in a 0.18-μm CMOS technology (fmax ≈ 40 GHz). A 120-mV peak-to-peak pulse output at a center frequency of 13.4GHz with a wide bandwidth of 7.46 GHz is measured. The pulse center frequency is achieved with 33.5% of the fmax. The proposed pulse generator is suitable for transmitter design in low-cost low-power wideband sensing network applications.
{"title":"A damping pulse generator based on regenerated trigger switch","authors":"Nguyen Ngoc Mai-Khanh, T. Iizuka, K. Asada","doi":"10.1109/RFIC.2016.7508238","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508238","url":null,"abstract":"This paper presents a new microwave pulse generator based on a positive feedback scheme. The positive feedback is proposed to produce a quick regenerated trigger switch to spark an LC circuit and then generate a shock pulse. The proposed circuit does not need any edge-sharpener circuit or over-sized transistors and hence requires a small chip area. A testing prototype is fabricated in a 0.18-μm CMOS technology (fmax ≈ 40 GHz). A 120-mV peak-to-peak pulse output at a center frequency of 13.4GHz with a wide bandwidth of 7.46 GHz is measured. The pulse center frequency is achieved with 33.5% of the fmax. The proposed pulse generator is suitable for transmitter design in low-cost low-power wideband sensing network applications.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132873920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508240
D. Teeter, Ming Ji, David Southcombe, Praveen Nadimpalli, D. Widay
As the number of RF components increases inside mobile devices, the industry has rapidly adopted and utilized MIPI's RFFE serial bus specification [1] to communicate with these devices and reduce the amount of control line routing between components. However, the use of a serial bus within the RF front end increases the risk that RF energy, particularly from the Power Amplifier (PA), can corrupt the RFFE bus communication. RF coupling to areas such as the RFFE serial clock (SCLK) signal seen within the PA's RFFE state machine can result in communication errors with the PA. This coupling can be to the SCLK signal itself, or to the PA's CMOS controller's ground reference. PA designers must pay special attention to the positioning and design of the CMOS controller and the internal routing of signals to the controller to avoid these problems. This paper provides a detailed analysis of how RF energy coupling to the internal CMOS controller can create “glitches” on the SCLK signal that cause communication errors. A simple example is provided to illustrate how choices in PA module layout can significantly impact these issues. A natural extension of these concepts applies to phone or radio board layouts, too.
{"title":"RF induced communication errors in RFFE MIPI controlled Power Amplifiers","authors":"D. Teeter, Ming Ji, David Southcombe, Praveen Nadimpalli, D. Widay","doi":"10.1109/RFIC.2016.7508240","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508240","url":null,"abstract":"As the number of RF components increases inside mobile devices, the industry has rapidly adopted and utilized MIPI's RFFE serial bus specification [1] to communicate with these devices and reduce the amount of control line routing between components. However, the use of a serial bus within the RF front end increases the risk that RF energy, particularly from the Power Amplifier (PA), can corrupt the RFFE bus communication. RF coupling to areas such as the RFFE serial clock (SCLK) signal seen within the PA's RFFE state machine can result in communication errors with the PA. This coupling can be to the SCLK signal itself, or to the PA's CMOS controller's ground reference. PA designers must pay special attention to the positioning and design of the CMOS controller and the internal routing of signals to the controller to avoid these problems. This paper provides a detailed analysis of how RF energy coupling to the internal CMOS controller can create “glitches” on the SCLK signal that cause communication errors. A simple example is provided to illustrate how choices in PA module layout can significantly impact these issues. A natural extension of these concepts applies to phone or radio board layouts, too.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133239119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508271
Benqing Guo, Jun Chen, Yao Wang, Haiyan Jin, G. Yang
A complementary noise cancelling CMOS Low-noise amplifier (LNA) for mobile DTV application with enhanced linearity is proposed. Intrinsic noise cancellation mechanism maintains acceptable NF with reduced power consumption due to current reuse principle. Complementary multi-gated transistor (MGTR) technique is further employed to null the third-order distortion and compensate second-order nonlinearity of noise cancelling stage. Implemented in a 0.18-μm CMOS process, measurement results show that the proposed LNA provides a NF of 3 dB, and a maximum gain of 17.5 dB from 0.1 to 2 GHz. An input 1-dB compression point (IP1dB) and an IIP3 of -3 dBm and 14.3 dBm, respectively, are obtained. The circuit core only draws 9.7 mA from a 2.2 V supply.
{"title":"A wideband complementary noise cancelling CMOS LNA","authors":"Benqing Guo, Jun Chen, Yao Wang, Haiyan Jin, G. Yang","doi":"10.1109/RFIC.2016.7508271","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508271","url":null,"abstract":"A complementary noise cancelling CMOS Low-noise amplifier (LNA) for mobile DTV application with enhanced linearity is proposed. Intrinsic noise cancellation mechanism maintains acceptable NF with reduced power consumption due to current reuse principle. Complementary multi-gated transistor (MGTR) technique is further employed to null the third-order distortion and compensate second-order nonlinearity of noise cancelling stage. Implemented in a 0.18-μm CMOS process, measurement results show that the proposed LNA provides a NF of 3 dB, and a maximum gain of 17.5 dB from 0.1 to 2 GHz. An input 1-dB compression point (IP1dB) and an IIP3 of -3 dBm and 14.3 dBm, respectively, are obtained. The circuit core only draws 9.7 mA from a 2.2 V supply.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132432136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508258
Min-Yu Huang, T. Chi, Hua Wang
This paper presents an all-passive negative feedback network to perform autonomous RF front-end beam-forming towards the direction of the incident RF beam. The beam-forming front-end block consists of a passive network for RF signal processing, voltage rectifiers, and voltage-controlled phase shifters, all of which are passive components and consume zero DC power. A proof-of-concept 4-element self-steering beam-forming block at 5GHz is implemented in a standard 130nm CMOS process and occupies an area of 4.1mm2. The measurements demonstrate that a high-quality 4-element array factor is successfully synthesized for the input progressive phase shift from -120° to +120°. At an input power Pin of -17dBm/element, the normalized array factor is -4.3dB/-3.2dB at +90°/-90° input progressive phase shift in the closed-loop operation, out-performing reported active self-steering beam-formers. To the best of our knowledge, this is the first demonstration of an all-passive network for front-end self-steering beam-forming with zero DC power.
{"title":"A 5GHz all-passive negative feedback network for RF front-end self-steering beam-forming with zero DC power consumption","authors":"Min-Yu Huang, T. Chi, Hua Wang","doi":"10.1109/RFIC.2016.7508258","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508258","url":null,"abstract":"This paper presents an all-passive negative feedback network to perform autonomous RF front-end beam-forming towards the direction of the incident RF beam. The beam-forming front-end block consists of a passive network for RF signal processing, voltage rectifiers, and voltage-controlled phase shifters, all of which are passive components and consume zero DC power. A proof-of-concept 4-element self-steering beam-forming block at 5GHz is implemented in a standard 130nm CMOS process and occupies an area of 4.1mm2. The measurements demonstrate that a high-quality 4-element array factor is successfully synthesized for the input progressive phase shift from -120° to +120°. At an input power Pin of -17dBm/element, the normalized array factor is -4.3dB/-3.2dB at +90°/-90° input progressive phase shift in the closed-loop operation, out-performing reported active self-steering beam-formers. To the best of our knowledge, this is the first demonstration of an all-passive network for front-end self-steering beam-forming with zero DC power.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125779593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508241
C. Coen, S. Zeinolabedinzadeh, M. Kaynak, B. Tillack, J. Cressler
This paper presents a 138-170 GHz active frequency doubler implemented in a 0.13 μm SiGe BiCMOS technology with a peak output power of 5.6 dBm and peak power-added efficiency of 7.6%. The doubler achieves a peak conversion gain of 4.9 dB and consumes only 36 mW of DC power at peak drive through the use of a push-push frequency doubling stage optimized for low drive power, along with a low-power output buffer. To the best of our knowledge, this doubler achieves the highest output power, efficiency, and fundamental frequency suppression of all D-band and G-band SiGe HBT frequency doublers to date.
{"title":"A highly-efficient 138–170 GHz SiGe HBT frequency doubler for power-constrained applications","authors":"C. Coen, S. Zeinolabedinzadeh, M. Kaynak, B. Tillack, J. Cressler","doi":"10.1109/RFIC.2016.7508241","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508241","url":null,"abstract":"This paper presents a 138-170 GHz active frequency doubler implemented in a 0.13 μm SiGe BiCMOS technology with a peak output power of 5.6 dBm and peak power-added efficiency of 7.6%. The doubler achieves a peak conversion gain of 4.9 dB and consumes only 36 mW of DC power at peak drive through the use of a push-push frequency doubling stage optimized for low drive power, along with a low-power output buffer. To the best of our knowledge, this doubler achieves the highest output power, efficiency, and fundamental frequency suppression of all D-band and G-band SiGe HBT frequency doublers to date.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125961979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508255
Youngmin Kim, Pilsung Jang, Junghwan Han, Heeseon Shin, Suseob Ahn, Daehyun Kwon, J. Choi, Sanghoon Kang, Seungchan Heo, T. Cho
An RF receiver for carrier aggregation employing a low noise amplifier with a current reusing technique and a frequency-band switchable transformer is demonstrated in a 28nm LP CMOS technology. The proposed single-ended low-noise amplifier can support multiple-channel RF signals for both inter- and intra-band carrier aggregation with high performance and low DC current consumption. Moreover, a frequency-band switchable transformer is developed to realize a size-efficient receiver for handling three carrier components carrier aggregation. The receiver operates at frequency bands, ranging from 0.7 to 2.7 GHz. The receiver has conversion gain more than 70 dB and noise figure of less than 3.5 dB for all carrier aggregation combinations.
{"title":"An RF receiver for multi-band inter- and intra-band carrier aggregation","authors":"Youngmin Kim, Pilsung Jang, Junghwan Han, Heeseon Shin, Suseob Ahn, Daehyun Kwon, J. Choi, Sanghoon Kang, Seungchan Heo, T. Cho","doi":"10.1109/RFIC.2016.7508255","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508255","url":null,"abstract":"An RF receiver for carrier aggregation employing a low noise amplifier with a current reusing technique and a frequency-band switchable transformer is demonstrated in a 28nm LP CMOS technology. The proposed single-ended low-noise amplifier can support multiple-channel RF signals for both inter- and intra-band carrier aggregation with high performance and low DC current consumption. Moreover, a frequency-band switchable transformer is developed to realize a size-efficient receiver for handling three carrier components carrier aggregation. The receiver operates at frequency bands, ranging from 0.7 to 2.7 GHz. The receiver has conversion gain more than 70 dB and noise figure of less than 3.5 dB for all carrier aggregation combinations.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130120973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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