Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508314
A. Samelis, E. Whittaker, Michael Ball, A. Bruce, J. Nisbet, L. Lam, C. Christmas, W. Vaillancourt
A fully integrated flip-chip SiGe BiCMOS power amplifier for wireless local area network (WLAN) applications in the 2 GHz band is presented. In a front-end module (FEM) configuration and under 802.11ac signal excitation, the PA delivers 29 dB small-signal gain and -30.4 dB dynamic error vector magnitude (EVM) at 20.6 dBm, at nominal operating conditions (3.3 V, 25 °C). The PA tightly controls detector voltage and corrects the dynamic EVM over supply voltage, temperature, orthogonal frequency division multiplexing (OFDM) burst length and duty cycle variations.
{"title":"A fully integrated flip-chip SiGe BiCMOS power amplifier for 802.11ac applications","authors":"A. Samelis, E. Whittaker, Michael Ball, A. Bruce, J. Nisbet, L. Lam, C. Christmas, W. Vaillancourt","doi":"10.1109/RFIC.2016.7508314","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508314","url":null,"abstract":"A fully integrated flip-chip SiGe BiCMOS power amplifier for wireless local area network (WLAN) applications in the 2 GHz band is presented. In a front-end module (FEM) configuration and under 802.11ac signal excitation, the PA delivers 29 dB small-signal gain and -30.4 dB dynamic error vector magnitude (EVM) at 20.6 dBm, at nominal operating conditions (3.3 V, 25 °C). The PA tightly controls detector voltage and corrects the dynamic EVM over supply voltage, temperature, orthogonal frequency division multiplexing (OFDM) burst length and duty cycle variations.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122423409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508326
Y. Tousi, A. Valdes-Garcia
We present a passive digital-to-phase converter with sub-degree phase precision for phased array frontends. The phase tuning approach is based on manipulating the electromagnetic properties of an artificially constructed transmission line. By simultaneously controlling dispersion, characteristic impedance, and loss across the structure, the phase shifter minimizes phase imprecisions while ensuring a flat amplitude response across different phase settings. The chip prototype is fabricated in a 130nm SiGe BiCMOS process, occupies an area of 0.18mm2, and consumes no power. The insertion loss is -9.3 dB ± 0.25 dB at 28 GHz. The phase control operates with 4.75 degree steps while maintaining an RMS phase error of 0.6 degrees across multiple chips and temperatures, demonstrating the best phase and amplitude accuracy when compared to state-of-the-art integrated microwave and mm-wave phase shifters.
{"title":"A Ka-band digitally-controlled phase shifter with sub-degree phase precision","authors":"Y. Tousi, A. Valdes-Garcia","doi":"10.1109/RFIC.2016.7508326","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508326","url":null,"abstract":"We present a passive digital-to-phase converter with sub-degree phase precision for phased array frontends. The phase tuning approach is based on manipulating the electromagnetic properties of an artificially constructed transmission line. By simultaneously controlling dispersion, characteristic impedance, and loss across the structure, the phase shifter minimizes phase imprecisions while ensuring a flat amplitude response across different phase settings. The chip prototype is fabricated in a 130nm SiGe BiCMOS process, occupies an area of 0.18mm2, and consumes no power. The insertion loss is -9.3 dB ± 0.25 dB at 28 GHz. The phase control operates with 4.75 degree steps while maintaining an RMS phase error of 0.6 degrees across multiple chips and temperatures, demonstrating the best phase and amplitude accuracy when compared to state-of-the-art integrated microwave and mm-wave phase shifters.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115831060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508268
Tapio Rapinoja, Yury Antonov, K. Stadius, J. Ryynanen
This paper presents a 0.4 to 2.1 GHz open-loop fractional-N multiplying delay-locked loop based frequency synthesizer in 65 nm CMOS. The proposed frequency synthesizer architecture is based on Digital Period Synthesis that features wide frequency range, fine frequency resolution, instantaneous frequency switching and is capable to provide several independent outputs. An inherent challenge of fractional-N synthesis is a notable deterministic jitter. In this paper we present a high-speed direct delay modulation circuit (DDM) that provides over ten-fold reduction in deterministic jitter over the entire frequency range. The measured deterministic period jitter, related to the fractional mode operation, is reduced from 51 ps to 4 ps by using the DDM. Furthermore, in this paper we demonstrate, for the first time, how the implemented synthesizer can produce two totally independent outputs at different frequencies.
{"title":"Fractional-N open-loop digital frequency synthesizer with a post-modulator for jitter reduction","authors":"Tapio Rapinoja, Yury Antonov, K. Stadius, J. Ryynanen","doi":"10.1109/RFIC.2016.7508268","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508268","url":null,"abstract":"This paper presents a 0.4 to 2.1 GHz open-loop fractional-N multiplying delay-locked loop based frequency synthesizer in 65 nm CMOS. The proposed frequency synthesizer architecture is based on Digital Period Synthesis that features wide frequency range, fine frequency resolution, instantaneous frequency switching and is capable to provide several independent outputs. An inherent challenge of fractional-N synthesis is a notable deterministic jitter. In this paper we present a high-speed direct delay modulation circuit (DDM) that provides over ten-fold reduction in deterministic jitter over the entire frequency range. The measured deterministic period jitter, related to the fractional mode operation, is reduced from 51 ps to 4 ps by using the DDM. Furthermore, in this paper we demonstrate, for the first time, how the implemented synthesizer can produce two totally independent outputs at different frequencies.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131037755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508313
Hyunjin Ahn, Seungjun Baek, Hyunsik Ryu, I. Nam, O. Lee
In this paper, a fully integrated high-efficiency linear CMOS power amplifier (PA) is developed for 802.11g WLAN applications with the proposed power combining transformer. In comparison with conventional power combining transformers, the proposed power combining transformer can offer high-efficiency performances with a smaller die size. The fabricated two-stage PA using a 65nm CMOS technology achieves a saturated output power of 26.7 dBm with a drain efficiency (DE) of 47.7% at 2.48 GHz. The PA is tested with 54Mbps WLAN 802.11g signal and it meets the stringent error vector magnitude (EVM) and spectral mask requirements at a 20.13-dBm output power with a DE of 21.4%.
{"title":"A highly efficient WLAN CMOS PA with two-winding and single-winding combined transformer","authors":"Hyunjin Ahn, Seungjun Baek, Hyunsik Ryu, I. Nam, O. Lee","doi":"10.1109/RFIC.2016.7508313","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508313","url":null,"abstract":"In this paper, a fully integrated high-efficiency linear CMOS power amplifier (PA) is developed for 802.11g WLAN applications with the proposed power combining transformer. In comparison with conventional power combining transformers, the proposed power combining transformer can offer high-efficiency performances with a smaller die size. The fabricated two-stage PA using a 65nm CMOS technology achieves a saturated output power of 26.7 dBm with a drain efficiency (DE) of 47.7% at 2.48 GHz. The PA is tested with 54Mbps WLAN 802.11g signal and it meets the stringent error vector magnitude (EVM) and spectral mask requirements at a 20.13-dBm output power with a DE of 21.4%.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130676627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508311
Sriram Muralidharan, Kefei Wu, M. Hella
This paper presents the design and measurements of a 165-230 GHz SiGe BiCMOS power amplifier - frequency doubler chain, which can deliver up to 5 dBm peak output power at 204 GHz with a 3-dB bandwidth of 65 GHz. A compact high efficiency power divider is used to split the power from the input mm-wave source and convert the single ended input to two differential signals. The 3-staged transformer-coupled cascode power amplifier is optimized to deliver 14 dBm saturated output power at 110 GHz, while the frequency doubler uses a second harmonic reflector at its input to reduce the conversion loss. The chip is designed in 0.13μm SiGe BiCMOS technology. To the authors' best knowledge, this is the highest output power above 200 GHz from silicon based amplifier-multiplier chains.
{"title":"A 165–230GHz SiGe amplifier-doubler chain with 5dBm peak output power","authors":"Sriram Muralidharan, Kefei Wu, M. Hella","doi":"10.1109/RFIC.2016.7508311","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508311","url":null,"abstract":"This paper presents the design and measurements of a 165-230 GHz SiGe BiCMOS power amplifier - frequency doubler chain, which can deliver up to 5 dBm peak output power at 204 GHz with a 3-dB bandwidth of 65 GHz. A compact high efficiency power divider is used to split the power from the input mm-wave source and convert the single ended input to two differential signals. The 3-staged transformer-coupled cascode power amplifier is optimized to deliver 14 dBm saturated output power at 110 GHz, while the frequency doubler uses a second harmonic reflector at its input to reduce the conversion loss. The chip is designed in 0.13μm SiGe BiCMOS technology. To the authors' best knowledge, this is the highest output power above 200 GHz from silicon based amplifier-multiplier chains.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"260 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122898342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508288
Wen Yuan, J. Walling
This paper presents a multiphase switched-capacitor power amplifier (MP-SCPA). Cartesian combining architectures suffer reduced output power and efficiency owing to combination of out-of-phase signals. The multiphase architecture reduces the phase difference between the basis vectors that are combined, increasing the output power and efficiency compared to the Cartesian combiners. 16 equally spaced phases are produced by a phase generator with each phase's relative amplitude weighted on the bottom plate of a capacitor array and combined on a common top plate, resulting in linear amplification. The MP-SCPA delivers a peak output power and PAE of 26 dBm and 24.9%, respectively. When amplifying an LTE signal the average output power and PAE are 20.9 dBm and 15.2%, respectively while achieving <;-30 dBc ACLR and 3.5 %-rms EVM.
{"title":"A multiphase switched capacitor power amplifier in 130nm CMOS","authors":"Wen Yuan, J. Walling","doi":"10.1109/RFIC.2016.7508288","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508288","url":null,"abstract":"This paper presents a multiphase switched-capacitor power amplifier (MP-SCPA). Cartesian combining architectures suffer reduced output power and efficiency owing to combination of out-of-phase signals. The multiphase architecture reduces the phase difference between the basis vectors that are combined, increasing the output power and efficiency compared to the Cartesian combiners. 16 equally spaced phases are produced by a phase generator with each phase's relative amplitude weighted on the bottom plate of a capacitor array and combined on a common top plate, resulting in linear amplification. The MP-SCPA delivers a peak output power and PAE of 26 dBm and 24.9%, respectively. When amplifying an LTE signal the average output power and PAE are 20.9 dBm and 15.2%, respectively while achieving <;-30 dBc ACLR and 3.5 %-rms EVM.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122122885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508301
J. Jayamon, J. Buckwalter, P. Asbeck
In deeply scaled CMOS processes with gate lengths below 40 nm the analog performance of NMOS and PMOS FETs are comparable. At the same time PMOS FETs can typically operate under higher operating voltages than NMOS devices. In this paper, we present the first millimeter-wave power amplifier exclusively employing PMOS. The single stage, 3-stack power amplifier operates at 65 - 92 GHz with more than 35% fractional bandwidth and 12 dB gain. At 78 GHz, the PA achieves a maximum output power of 19.6 dBm and PAE of 18% with class-A bias, and 18.7 dBm and 24% PAE with class-AB bias. The PA has been fabricated in 32 nm CMOS SOI process and occupies 440 μm × 280 μm area (only 0.05 mm2 excluding pads). To the authors' knowledge this PA achieves the highest efficiency for any silicon PA in the 60-90 GHz frequency band. The output power is also the best reported in silicon for this frequency range, for amplifiers that do not use elaborate power-combining approaches.
{"title":"A PMOS mm-wave power amplifier at 77 GHz with 90 mW output power and 24% efficiency","authors":"J. Jayamon, J. Buckwalter, P. Asbeck","doi":"10.1109/RFIC.2016.7508301","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508301","url":null,"abstract":"In deeply scaled CMOS processes with gate lengths below 40 nm the analog performance of NMOS and PMOS FETs are comparable. At the same time PMOS FETs can typically operate under higher operating voltages than NMOS devices. In this paper, we present the first millimeter-wave power amplifier exclusively employing PMOS. The single stage, 3-stack power amplifier operates at 65 - 92 GHz with more than 35% fractional bandwidth and 12 dB gain. At 78 GHz, the PA achieves a maximum output power of 19.6 dBm and PAE of 18% with class-A bias, and 18.7 dBm and 24% PAE with class-AB bias. The PA has been fabricated in 32 nm CMOS SOI process and occupies 440 μm × 280 μm area (only 0.05 mm2 excluding pads). To the authors' knowledge this PA achieves the highest efficiency for any silicon PA in the 60-90 GHz frequency band. The output power is also the best reported in silicon for this frequency range, for amplifiers that do not use elaborate power-combining approaches.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115246353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508265
W. El-Halwagy, A. Nag, P. Hisayasu, F. Aryanfar, P. Mousavi, M. Hossain
A 26-32GHz quadrature cascaded phase locked loop (PLL) is presented. The PLL is implemented in 65nm bulk CMOS, consuming 27mW and has less than 100fsec integrated jitter with -114.4 and -112.6dBc/Hz phase noise at 1MHz offset for integer and fractional modes, respectively.
{"title":"A 28GHz quadrature fractional-N synthesizer for 5G mobile communication with less than 100fs jitter in 65nm CMOS","authors":"W. El-Halwagy, A. Nag, P. Hisayasu, F. Aryanfar, P. Mousavi, M. Hossain","doi":"10.1109/RFIC.2016.7508265","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508265","url":null,"abstract":"A 26-32GHz quadrature cascaded phase locked loop (PLL) is presented. The PLL is implemented in 65nm bulk CMOS, consuming 27mW and has less than 100fsec integrated jitter with -114.4 and -112.6dBc/Hz phase noise at 1MHz offset for integer and fractional modes, respectively.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129999062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508281
Hossein Jalili, O. Momeni
A 1×4 scalable mm-wave power generation and radiation array is designed using a standing wave harmonic oscillator architecture. A varactor-less scheme has been used to improve the tuning range above 300 GHz. The circuit with on chip patch antennas is implemented in a 130nm SiGe process with 215 GHz of fmax and is measured to provide 5.9% tuning range, -10.5 dBm total radiated power and 1.2 dBm EIRP at 342 GHz while consuming 425 mW DC power from 1.8 V supply voltage.
{"title":"A 0.34-THz varactor-less scalable standing wave radiator array with 5.9% tuning range in 130nm BiCMOS","authors":"Hossein Jalili, O. Momeni","doi":"10.1109/RFIC.2016.7508281","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508281","url":null,"abstract":"A 1×4 scalable mm-wave power generation and radiation array is designed using a standing wave harmonic oscillator architecture. A varactor-less scheme has been used to improve the tuning range above 300 GHz. The circuit with on chip patch antennas is implemented in a 130nm SiGe process with 215 GHz of fmax and is measured to provide 5.9% tuning range, -10.5 dBm total radiated power and 1.2 dBm EIRP at 342 GHz while consuming 425 mW DC power from 1.8 V supply voltage.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124446382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508252
Xiang Yi, Kaituo Yang, Zhipeng Liang, Bei Liu, Khanna Devrishi, C. Boon, Chenyang Li, Guangyin Feng, D. Regev, S. Shilo, F. Meng, Hang-Ji Liu, Junyi Sun, Gengen Hu, Y. Miao
This work presents a parallel direct-conversion and double-conversion transceiver to solve the problems of crosstalk and LO pulling in the carrier aggregation scenario. An EVM of -34.9 dB is obtained when the output power of the PA driver is 0.4 dBm. Three aggregated carriers with 80 MHz 256-QAM modulation are demonstrated. To the authors' best knowledge, this work is the first CMOS integrated transceiver for IEEE 802.11 WLAN carrier aggregation application.
{"title":"A 65nm CMOS carrier-aggregation transceiver for IEEE 802.11 WLAN applications","authors":"Xiang Yi, Kaituo Yang, Zhipeng Liang, Bei Liu, Khanna Devrishi, C. Boon, Chenyang Li, Guangyin Feng, D. Regev, S. Shilo, F. Meng, Hang-Ji Liu, Junyi Sun, Gengen Hu, Y. Miao","doi":"10.1109/RFIC.2016.7508252","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508252","url":null,"abstract":"This work presents a parallel direct-conversion and double-conversion transceiver to solve the problems of crosstalk and LO pulling in the carrier aggregation scenario. An EVM of -34.9 dB is obtained when the output power of the PA driver is 0.4 dBm. Three aggregated carriers with 80 MHz 256-QAM modulation are demonstrated. To the authors' best knowledge, this work is the first CMOS integrated transceiver for IEEE 802.11 WLAN carrier aggregation application.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116290473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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