Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508262
Ming Li, Shaoqiang Zhang, P. Shyam, Raj Verma Purakh
Power Amplifier (PA) modules are becoming more and more complex in modern wireless systems. In order to meet the efficiency/linearity design schemes such as Envelope elimination and restoration (EER) and Envelope tracking (ET) are increasingly becoming popular in PA applications. This paper describes an optimized isolated 5V EDMOS in 55nm Low Power extended (LPx) platform which is ideal for use in the bias modulator and controller of the PA module. Industry leading Rsp of 0.96 mohm-mm2 for high voltage NMOS and 2.6 mohm-mm2 for the high voltage PMOS is reported. Drain to source breakdown voltages of 10.5V was achieved for these devices. Due to special considerations given to optimizing the CGD capacitance while maintaining the Rsp, high Johnson's figure of merit (fT*BVDS) of 536 GHz-V and 168 GHz-V were achieved for the NMOS and PMOS respectively.
{"title":"An optimized isolated 5V EDMOS in 55nm LPx platform for use in Power Amplifier applications","authors":"Ming Li, Shaoqiang Zhang, P. Shyam, Raj Verma Purakh","doi":"10.1109/RFIC.2016.7508262","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508262","url":null,"abstract":"Power Amplifier (PA) modules are becoming more and more complex in modern wireless systems. In order to meet the efficiency/linearity design schemes such as Envelope elimination and restoration (EER) and Envelope tracking (ET) are increasingly becoming popular in PA applications. This paper describes an optimized isolated 5V EDMOS in 55nm Low Power extended (LPx) platform which is ideal for use in the bias modulator and controller of the PA module. Industry leading Rsp of 0.96 mohm-mm2 for high voltage NMOS and 2.6 mohm-mm2 for the high voltage PMOS is reported. Drain to source breakdown voltages of 10.5V was achieved for these devices. Due to special considerations given to optimizing the CGD capacitance while maintaining the Rsp, high Johnson's figure of merit (fT*BVDS) of 536 GHz-V and 168 GHz-V were achieved for the NMOS and PMOS respectively.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132087958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508302
Voravit Vorapipat, Cooper S. Levy, P. Asbeck
This paper presents a new wideband Doherty Amplifier technique that can achieve high efficiency while maintaining excellent linearity. By modifying a “forgotten” topology originally proposed by Doherty, a new Doherty Amplifier architecture is realized with two voltage mode PAs and transformers, thus eliminating a narrowband impedance inverter. The voltage mode PA is implemented with a switched capacitor PA known for its excellent linearity. The PA is fabricated in 65 nm low-leakage CMOS and achieves 24 dBm saturated power (at standard supply voltage) with 45%/34% PAE at peak and 5.6dB back-off over 750 MHz to 1050 MHz 1dB bandwidth. With memory-less linearization, this PA can transmit 40 MHz 256-QAM 9dB PAPR 802.11ac modulation centered at 900 MHz meeting the spectral mask with measured EVM of -34.8dB and 22% PAE without backing-off or equalization.
{"title":"A wideband voltage mode Doherty power amplifier","authors":"Voravit Vorapipat, Cooper S. Levy, P. Asbeck","doi":"10.1109/RFIC.2016.7508302","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508302","url":null,"abstract":"This paper presents a new wideband Doherty Amplifier technique that can achieve high efficiency while maintaining excellent linearity. By modifying a “forgotten” topology originally proposed by Doherty, a new Doherty Amplifier architecture is realized with two voltage mode PAs and transformers, thus eliminating a narrowband impedance inverter. The voltage mode PA is implemented with a switched capacitor PA known for its excellent linearity. The PA is fabricated in 65 nm low-leakage CMOS and achieves 24 dBm saturated power (at standard supply voltage) with 45%/34% PAE at peak and 5.6dB back-off over 750 MHz to 1050 MHz 1dB bandwidth. With memory-less linearization, this PA can transmit 40 MHz 256-QAM 9dB PAPR 802.11ac modulation centered at 900 MHz meeting the spectral mask with measured EVM of -34.8dB and 22% PAE without backing-off or equalization.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128042625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508295
Mohammed Abdulaziz, W. Ahmad, Anders Nejdel, M. Tormanen, H. Sjoland
A receiver front-end supporting contiguous and non-contiguous intra-band carrier aggregation scenarios with a fully integrated spectrum sensor that can detect both in-gap and out-of-band blockers has been implemented in 65nm CMOS technology. An NF of 2.5dB is achieved using a noise canceling LNTA, and linearized OTAs are used to achieve an IIP3 improvement of up to 6.5dB in-band and 11dB at the filter band edge. The spectrum sensor can detect blocker levels in 22 steps of 9MHz between -100MHz and 100MHz IF. The system consumes between 36.6mA and 57.6mA from a 1.2V supply.
{"title":"A cellular receiver front-end with blocker sensing","authors":"Mohammed Abdulaziz, W. Ahmad, Anders Nejdel, M. Tormanen, H. Sjoland","doi":"10.1109/RFIC.2016.7508295","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508295","url":null,"abstract":"A receiver front-end supporting contiguous and non-contiguous intra-band carrier aggregation scenarios with a fully integrated spectrum sensor that can detect both in-gap and out-of-band blockers has been implemented in 65nm CMOS technology. An NF of 2.5dB is achieved using a noise canceling LNTA, and linearized OTAs are used to achieve an IIP3 improvement of up to 6.5dB in-band and 11dB at the filter band edge. The spectrum sensor can detect blocker levels in 22 steps of 9MHz between -100MHz and 100MHz IF. The system consumes between 36.6mA and 57.6mA from a 1.2V supply.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"171 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132906258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508324
Umut Kodak, Gabriel M. Rebeiz
This paper presents a low-power 26-28 GHz phased-array receive channel in 45nm CMOS SOI. The design alternates cascode amplifiers with switched-LC phase-shifter cells to result in 5-bit phase control with gain and rms phase error <; 0.6 dB and 4°, respectively, over 32 phase states. The measured gain, noise figure (NF) and IIP3 are 12.2 dB, 4 dB and 0 dBm, respectively, and are achieved at a DC power of 42 mW. A gain control of 6-dB is also available without affecting the system NF. To our knowledge, this represents state-of-the-art in mm-wave phased-arrays with the best published linearity at low NF. Application areas include 5G base-stations and hand-held units.
{"title":"A 42mW 26–28 GHz phased-array receive channel with 12 dB gain, 4 dB NF and 0 dBm IIP3 in 45nm CMOS SOI","authors":"Umut Kodak, Gabriel M. Rebeiz","doi":"10.1109/RFIC.2016.7508324","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508324","url":null,"abstract":"This paper presents a low-power 26-28 GHz phased-array receive channel in 45nm CMOS SOI. The design alternates cascode amplifiers with switched-LC phase-shifter cells to result in 5-bit phase control with gain and rms phase error <; 0.6 dB and 4°, respectively, over 32 phase states. The measured gain, noise figure (NF) and IIP3 are 12.2 dB, 4 dB and 0 dBm, respectively, and are achieved at a DC power of 42 mW. A gain control of 6-dB is also available without affecting the system NF. To our knowledge, this represents state-of-the-art in mm-wave phased-arrays with the best published linearity at low NF. Application areas include 5G base-stations and hand-held units.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133484080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508274
Hao Gao, Kuangyuan Ying, M. Matters-Kammerer, P. Harpe, Q. Ma, A. V. van Roermund, P. Baltus
This paper presents a low noise amplifier realized in 40-nm CMOS technology for the 60 GHz ISM band. To reduce the noise contribution from the input passive structure, a new metal slotting method is applied to the transmission line for increasing the effective conducting cross-section area. The design incorporates additional noise matching between the common-source stage and the common-gate stage to reduce the noise impact by the latter stage. The measured noise figure is below 4 dB from 51 GHz to 65 GHz, 3.6 dB at 55 GHz and 3.8 dB at 60 GHz. The achieved 3 dB power gain bandwidth is 13 GHz, from 48 GHz to 61 GHz. The peak transducer gain (Gt) is 15 dB at 55 GHz, and 12.5 dB at 60 GHz. The total power consumption is 20.4 mW.
{"title":"A 48–61 GHz LNA in 40-nm CMOS with 3.6 dB minimum NF employing a metal slotting method","authors":"Hao Gao, Kuangyuan Ying, M. Matters-Kammerer, P. Harpe, Q. Ma, A. V. van Roermund, P. Baltus","doi":"10.1109/RFIC.2016.7508274","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508274","url":null,"abstract":"This paper presents a low noise amplifier realized in 40-nm CMOS technology for the 60 GHz ISM band. To reduce the noise contribution from the input passive structure, a new metal slotting method is applied to the transmission line for increasing the effective conducting cross-section area. The design incorporates additional noise matching between the common-source stage and the common-gate stage to reduce the noise impact by the latter stage. The measured noise figure is below 4 dB from 51 GHz to 65 GHz, 3.6 dB at 55 GHz and 3.8 dB at 60 GHz. The achieved 3 dB power gain bandwidth is 13 GHz, from 48 GHz to 61 GHz. The peak transducer gain (Gt) is 15 dB at 55 GHz, and 12.5 dB at 60 GHz. The total power consumption is 20.4 mW.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122386518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508237
Johan C. J. G. Withagen, A. Annema, B. Nauta, F. V. van Vliet
An 8-10 GHz X-band upconversion quadrature mixer stage implemented in 250 nm SiGe BiCMOS is presented. Orthogonality of the spurious responses caused by clock feed through, I/Q mismatch and baseband harmonics after self-mixing was exploited to realize a baseband calibration scheme reducing all in-band spurs down to below -73dBc, for baseband signals up to a bandwidth of 2MHz and with an IF center frequency up to 100MHz. Utilizing a low-frequency output spectrum analysis of an integrated self-mixer at the upconversion mixer output for calibration, eliminates the need for expensive microwave frequency spectrum analyzers.
{"title":"An 8–10 GHz upconversion mixer, with a low-frequency calibration loop resulting in better than −73dBc in-band spurs","authors":"Johan C. J. G. Withagen, A. Annema, B. Nauta, F. V. van Vliet","doi":"10.1109/RFIC.2016.7508237","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508237","url":null,"abstract":"An 8-10 GHz X-band upconversion quadrature mixer stage implemented in 250 nm SiGe BiCMOS is presented. Orthogonality of the spurious responses caused by clock feed through, I/Q mismatch and baseband harmonics after self-mixing was exploited to realize a baseband calibration scheme reducing all in-band spurs down to below -73dBc, for baseband signals up to a bandwidth of 2MHz and with an IF center frequency up to 100MHz. Utilizing a low-frequency output spectrum analysis of an integrated self-mixer at the upconversion mixer output for calibration, eliminates the need for expensive microwave frequency spectrum analyzers.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130962358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508244
Liheng Lou, Bo Chen, Kai Tang, Supeng Liu, Yuanjin Zheng
The paper presents an ultra-wideband, low-power frequency synthesizer for Ku-band FMCW radars. This ADPLL-based frequency synthesizer generates chirps with configurable rate from 0.4 to 3.2GHz/ms, up to 2GHz bandwidth in triangle or sawtooth mode. Adaptive loop bandwidth is adopted to reduce variations of the loop tracking characteristic during ramping under different chirp rate, by which, a low frequency RMS error of ~179kHz is achieved for the chirp rate below 2GHz/ms. Fabricated in a 65nm CMOS, the synthesizer generates a wideband chirp from 13.8GHz to 15.8GHz, and consumes 36.3mW, featuring state of the art performance.
{"title":"An ultra-wideband low-power ADPLL chirp synthesizer with adaptive loop bandwidth in 65nm CMOS","authors":"Liheng Lou, Bo Chen, Kai Tang, Supeng Liu, Yuanjin Zheng","doi":"10.1109/RFIC.2016.7508244","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508244","url":null,"abstract":"The paper presents an ultra-wideband, low-power frequency synthesizer for Ku-band FMCW radars. This ADPLL-based frequency synthesizer generates chirps with configurable rate from 0.4 to 3.2GHz/ms, up to 2GHz bandwidth in triangle or sawtooth mode. Adaptive loop bandwidth is adopted to reduce variations of the loop tracking characteristic during ramping under different chirp rate, by which, a low frequency RMS error of ~179kHz is achieved for the chirp rate below 2GHz/ms. Fabricated in a 65nm CMOS, the synthesizer generates a wideband chirp from 13.8GHz to 15.8GHz, and consumes 36.3mW, featuring state of the art performance.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"184 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115552275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508276
Yang Xu, Praveen Kumar Venkatachala, Spencer Leuenberger, U. Moon
This paper proposes a highly reconfigurable charge-domain switched-gm-C biquad band-pass filter (BPF) topology that uses a semi-passive charge-sharing technique. It uses only switches, capacitors, digital circuitry for 3-phase non-overlapping clock generation and linearity-enhanced gm-stages. A 4th-order BPF prototype operating at 1.2GS/s sampling rate is implemented using a cascade of two independent biquads in a 65nm LPE CMOS. A tunable center frequency of 35-70MHz is measured with programmable bandwidth and a maximum stop-band rejection of 72dB. The in-band 1-dB compression point is -2.4dBm, and the in-band IIP3 is +9dBm. The filter prototype consumes 7.5mW from a 1.2V supply, and occupies an active area of 0.17mm2.
{"title":"A 7.5mW 35–70MHz 4th-order semi-passive charge-sharing band-pass filter with programmable bandwidth and 72dB stop-band rejection in 65nm CMOS","authors":"Yang Xu, Praveen Kumar Venkatachala, Spencer Leuenberger, U. Moon","doi":"10.1109/RFIC.2016.7508276","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508276","url":null,"abstract":"This paper proposes a highly reconfigurable charge-domain switched-gm-C biquad band-pass filter (BPF) topology that uses a semi-passive charge-sharing technique. It uses only switches, capacitors, digital circuitry for 3-phase non-overlapping clock generation and linearity-enhanced gm-stages. A 4th-order BPF prototype operating at 1.2GS/s sampling rate is implemented using a cascade of two independent biquads in a 65nm LPE CMOS. A tunable center frequency of 35-70MHz is measured with programmable bandwidth and a maximum stop-band rejection of 72dB. The in-band 1-dB compression point is -2.4dBm, and the in-band IIP3 is +9dBm. The filter prototype consumes 7.5mW from a 1.2V supply, and occupies an active area of 0.17mm2.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"227 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127004959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508298
Saeed Pourbagheri, K. Mayaram, T. Fiez
A blocker filtering technique is presented that extracts the clock from the blocker for SAW-less receivers. The extracted clock is utilized to suppress the blocker without requiring any prior information of the exact location of the blocker. This clock runs at the blocker frequency and drives a notch filter that steers the blocker current away from the signal path. Implemented in a 65 nm CMOS process, the filter is able to track the blocker within 1 to 1.6 GHz and provides about 20 dB of rejection relative to the signal at the notch frequency for blockers from -40 dBm to -10 dBm.
{"title":"A self-clocked blocker-filtering technique for SAW-less wireless applications","authors":"Saeed Pourbagheri, K. Mayaram, T. Fiez","doi":"10.1109/RFIC.2016.7508298","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508298","url":null,"abstract":"A blocker filtering technique is presented that extracts the clock from the blocker for SAW-less receivers. The extracted clock is utilized to suppress the blocker without requiring any prior information of the exact location of the blocker. This clock runs at the blocker frequency and drives a notch filter that steers the blocker current away from the signal path. Implemented in a 65 nm CMOS process, the filter is able to track the blocker within 1 to 1.6 GHz and provides about 20 dB of rejection relative to the signal at the notch frequency for blockers from -40 dBm to -10 dBm.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126510905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508260
Sanket Jain, Yunqi Wang, A. Natarajan
An architecture for low-noise spatial cancellation of co-channel interferer (CCI) at RF in a digital beamforming (DBF)/MIMO receiver (RX) array is presented. The proposed RF cancellation can attenuate CCI prior to the ADC in a DBF/MIMO RX array while preserving a field-of-view (FoV) in each array element, enabling subsequent DSP for multi-beamforming. A novel hybrid-coupler/polyphase-filter based input coupling scheme that simplifies spatial selection of CCI and enables low-noise cancellation is described. A 4-element 10GHz prototype is implemented in 65nm CMOS that achieves >20dB spatial cancellation of CCI while adding <;1.5dB output noise.
{"title":"A 10GHz CMOS RX frontend with spatial cancellation of co-channel interferers for MIMO/digital beamforming arrays","authors":"Sanket Jain, Yunqi Wang, A. Natarajan","doi":"10.1109/RFIC.2016.7508260","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508260","url":null,"abstract":"An architecture for low-noise spatial cancellation of co-channel interferer (CCI) at RF in a digital beamforming (DBF)/MIMO receiver (RX) array is presented. The proposed RF cancellation can attenuate CCI prior to the ADC in a DBF/MIMO RX array while preserving a field-of-view (FoV) in each array element, enabling subsequent DSP for multi-beamforming. A novel hybrid-coupler/polyphase-filter based input coupling scheme that simplifies spatial selection of CCI and enables low-noise cancellation is described. A 4-element 10GHz prototype is implemented in 65nm CMOS that achieves >20dB spatial cancellation of CCI while adding <;1.5dB output noise.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133365000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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