Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508277
R. Xu, Ja-yol Lee, D. Kim, Shinwoong Park, Z. Ahmad, K. O. Kenneth
An 840-GHz Schottky diode detector is integrated with an analog lock-in amplifier in 130-nm bulk CMOS. The integrated lock-in amplifier can support a modulation frequency of up to 10 MHz with a gain of 54 dB, a dynamic range of 42 dB, and an input referred noise of less than 10 nV/√(Hz) at modulation frequencies higher than 100 kHz. The integrated lock-in amplifier occupies an area of 0.17 mm2 and consumes 4.9 mA from a 1.2-V supply. The detector and on-chip lock-in amplifier combination was used to form terahertz images.
{"title":"0.84-THz imaging pixel with a lock-in amplifier in CMOS","authors":"R. Xu, Ja-yol Lee, D. Kim, Shinwoong Park, Z. Ahmad, K. O. Kenneth","doi":"10.1109/RFIC.2016.7508277","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508277","url":null,"abstract":"An 840-GHz Schottky diode detector is integrated with an analog lock-in amplifier in 130-nm bulk CMOS. The integrated lock-in amplifier can support a modulation frequency of up to 10 MHz with a gain of 54 dB, a dynamic range of 42 dB, and an input referred noise of less than 10 nV/√(Hz) at modulation frequencies higher than 100 kHz. The integrated lock-in amplifier occupies an area of 0.17 mm2 and consumes 4.9 mA from a 1.2-V supply. The detector and on-chip lock-in amplifier combination was used to form terahertz images.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123280030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508312
K. Datta, H. Hashemi
High-breakdown, high-fmax multi-port transistor topologies are presented in this work for realizing high power, highly efficient mm-wave switching power amplifiers at 75-105 GHz. Implemented in a 90nm SiGe BiCMOS process, the proposed active structures comprising of two and three stacked transistors with integrated layout parasitics achieve (fmax, breakdown voltage) of (295 GHz, 8V) and (260 GHz, 11 V) respectively and demonstrate peak (output power, PAE) of (22 dBm, 19%) at 85 GHz and (23.3 dBm, 17%) at 83 GHz respectively. The implemented designs are benchmarked against a 88 GHz 19.5 dBm, 16% PAE W-band Class-E power amplifier using native transistor footprints fabricated in the same 90nm SiGe BiCMOS process. The superior performance of the composite transistor designs highlight the benefit of the proposed approach.
{"title":"75 – 105 GHz switching power amplifiers using high-breakdown, high-fmax multi-port stacked transistor topologies","authors":"K. Datta, H. Hashemi","doi":"10.1109/RFIC.2016.7508312","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508312","url":null,"abstract":"High-breakdown, high-fmax multi-port transistor topologies are presented in this work for realizing high power, highly efficient mm-wave switching power amplifiers at 75-105 GHz. Implemented in a 90nm SiGe BiCMOS process, the proposed active structures comprising of two and three stacked transistors with integrated layout parasitics achieve (fmax, breakdown voltage) of (295 GHz, 8V) and (260 GHz, 11 V) respectively and demonstrate peak (output power, PAE) of (22 dBm, 19%) at 85 GHz and (23.3 dBm, 17%) at 83 GHz respectively. The implemented designs are benchmarked against a 88 GHz 19.5 dBm, 16% PAE W-band Class-E power amplifier using native transistor footprints fabricated in the same 90nm SiGe BiCMOS process. The superior performance of the composite transistor designs highlight the benefit of the proposed approach.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125374534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508275
H. Gheidi, T. Nakatani, V. Leung, P. Asbeck
This paper presents a new architecture for an RF phase modulator that significantly improves the phase resolution. The modulator utilizes 32 variable delay elements in a delay lock loop (DLL) configuration to provide wideband 1-3GHz operation with coarse 5-bit resolution. A 5-bit multiplexer selects different taps of the DLL according to the baseband digital phase data to generate desired phase modulated signal at the output. A high speed 5-bit digital delta-sigma modulator is additionally used to compensate for the phase truncation occurring in the 5-bit DLL. The phase modulator IC is implemented in 45nm CMOS SOI and achieves <;2% rms EVM while achieving 55dB rejection of close-to-carrier emissions for an 8Mb/s GMSK signal at 2.3GHz, with power consumption below 35mW.
{"title":"A wideband delta-sigma based closed-loop fully digital phase modulator in 45nm CMOS SOI","authors":"H. Gheidi, T. Nakatani, V. Leung, P. Asbeck","doi":"10.1109/RFIC.2016.7508275","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508275","url":null,"abstract":"This paper presents a new architecture for an RF phase modulator that significantly improves the phase resolution. The modulator utilizes 32 variable delay elements in a delay lock loop (DLL) configuration to provide wideband 1-3GHz operation with coarse 5-bit resolution. A 5-bit multiplexer selects different taps of the DLL according to the baseband digital phase data to generate desired phase modulated signal at the output. A high speed 5-bit digital delta-sigma modulator is additionally used to compensate for the phase truncation occurring in the 5-bit DLL. The phase modulator IC is implemented in 45nm CMOS SOI and achieves <;2% rms EVM while achieving 55dB rejection of close-to-carrier emissions for an 8Mb/s GMSK signal at 2.3GHz, with power consumption below 35mW.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124572675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508307
D. Adams, Yonina C. Eldar, B. Murmann
The Modulated Wideband Converter promises to improve receiver flexibility for cognitive radios by leveraging compressive sensing techniques. We present a prototype IC that adds signal reception to previously demonstrated signal detection. Refactoring the mixing sequence between detection and reception enables targeted reception and blocker rejection. We algorithmically design a three-level mixing sequence and additionally employ delay-based harmonic cancellation. When applied together in our 65-nm chip, we measure 62 dB of in-band blocker rejection, while receiving up to four channels between 0 and 900 MHz.
{"title":"A mixer frontend for a four-channel Modulated Wideband Converter with 62 dB blocker rejection","authors":"D. Adams, Yonina C. Eldar, B. Murmann","doi":"10.1109/RFIC.2016.7508307","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508307","url":null,"abstract":"The Modulated Wideband Converter promises to improve receiver flexibility for cognitive radios by leveraging compressive sensing techniques. We present a prototype IC that adds signal reception to previously demonstrated signal detection. Refactoring the mixing sequence between detection and reception enables targeted reception and blocker rejection. We algorithmically design a three-level mixing sequence and additionally employ delay-based harmonic cancellation. When applied together in our 65-nm chip, we measure 62 dB of in-band blocker rejection, while receiving up to four channels between 0 and 900 MHz.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117087599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508239
M. Buck, M. Grozing, R. Bieg, J. Digel, X.-Q. Du, P. Thomas, M. Berroth, M. Epp, J. Rauscher, M. Schlumpp
A pipelined folding-interpolating ADC with a distributed quantizer is presented. The low-mismatch analog frontend provides for excellent SFDR and SNDR without calibration or digital post processing. The algorithm of the digital coder relaxes the requirements on the interface between analog core and digital coder. The single-core ADC achieves 7.3 ENOB and a SFDR of 52.7 dBc in the 2nd Nyquist band at 6 GS/s with an overall power consumption of 10.2 W.
{"title":"A 6 GS/s 9.5 bit pipelined folding-interpolating ADC with 7.3 ENOB and 52.7 dBc SFDR in the 2nd Nyquist band in 0.25 µm SiGe-BiCMOS","authors":"M. Buck, M. Grozing, R. Bieg, J. Digel, X.-Q. Du, P. Thomas, M. Berroth, M. Epp, J. Rauscher, M. Schlumpp","doi":"10.1109/RFIC.2016.7508239","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508239","url":null,"abstract":"A pipelined folding-interpolating ADC with a distributed quantizer is presented. The low-mismatch analog frontend provides for excellent SFDR and SNDR without calibration or digital post processing. The algorithm of the digital coder relaxes the requirements on the interface between analog core and digital coder. The single-core ADC achieves 7.3 ENOB and a SFDR of 52.7 dBc in the 2nd Nyquist band at 6 GS/s with an overall power consumption of 10.2 W.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117198031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508254
Dang Liu, Xiaofeng Liu, W. Rhee, Zhihua Wang
This paper presents a 1Gb/s 6.5-to-8.5GHz transceiver for secure proximity communication systems. A prototype transceiver implemented in 65nm CMOS achieves the maximum data rate of 1Gb/s with the sensitivity of -53dBm and the communication range of 15cm. Consuming only 19.2mW, the proposed ultra-wideband (UWB) transceiver enables future applications such as smartphone-mirrored high-resolution display systems which require low power mainly for the transmitter in the smartphone, thus making it possible to further improve the transceiver performance with the complex receiver in the display equipment.
{"title":"A 19.2mW 1Gb/s secure proximity transceiver with ISI pre-correction and hysteresis energy detection","authors":"Dang Liu, Xiaofeng Liu, W. Rhee, Zhihua Wang","doi":"10.1109/RFIC.2016.7508254","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508254","url":null,"abstract":"This paper presents a 1Gb/s 6.5-to-8.5GHz transceiver for secure proximity communication systems. A prototype transceiver implemented in 65nm CMOS achieves the maximum data rate of 1Gb/s with the sensitivity of -53dBm and the communication range of 15cm. Consuming only 19.2mW, the proposed ultra-wideband (UWB) transceiver enables future applications such as smartphone-mirrored high-resolution display systems which require low power mainly for the transmitter in the smartphone, thus making it possible to further improve the transceiver performance with the complex receiver in the display equipment.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126203387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508247
T. Dinh, P. Descamps, D. Pasquet, D. Lesenechal, S. Wane
In this paper we present experimental characterization of packaged switch devices in terms of their RF attributes: isolation, insertion loss, power consumption, and linearity. Packaging and Board assembly significantly reduce their RF and mm-Wave performances. A broadband experimental setup is developed for the qualification of packaged switch devices accounting for deembedding effects both with on-board/on-package and on-chip probing. Module-based switch devices have been measured then, plastic molding, Si cap, and bonding wires have been sequentially removed to investigate their influences. Different challenges with packaged switch devices are identified and effective solutions are proposed for their qualification.
{"title":"Experimental characterization of packaged switch devices for RF and millimeter-Wave applications","authors":"T. Dinh, P. Descamps, D. Pasquet, D. Lesenechal, S. Wane","doi":"10.1109/RFIC.2016.7508247","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508247","url":null,"abstract":"In this paper we present experimental characterization of packaged switch devices in terms of their RF attributes: isolation, insertion loss, power consumption, and linearity. Packaging and Board assembly significantly reduce their RF and mm-Wave performances. A broadband experimental setup is developed for the qualification of packaged switch devices accounting for deembedding effects both with on-board/on-package and on-chip probing. Module-based switch devices have been measured then, plastic molding, Si cap, and bonding wires have been sequentially removed to investigate their influences. Different challenges with packaged switch devices are identified and effective solutions are proposed for their qualification.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131403908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508282
N. Sharma, W. Choi, K. O. Kenneth
A 160-310 GHz frequency doubler for rotational spectroscopy with a driver amplifier is demonstrated in a 65-nm bulk CMOS process. At 0-dBm input power, the measured output power (Pout) varies from 3 to -8 dBm. The wide operating range is attributed to wide bandwidth driver and matching structure based on broadband open and short leading to >40dB difference between fundamental and second harmonic power at the output. The doubler-amplifier combination has the comparable output power and a larger operating frequency range than 200-300 GHz COTS GaAs modules.
{"title":"160–310 GHz frequency doubler in 65-nm CMOS with 3-dBm peak output power for rotational spectroscopy","authors":"N. Sharma, W. Choi, K. O. Kenneth","doi":"10.1109/RFIC.2016.7508282","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508282","url":null,"abstract":"A 160-310 GHz frequency doubler for rotational spectroscopy with a driver amplifier is demonstrated in a 65-nm bulk CMOS process. At 0-dBm input power, the measured output power (Pout) varies from 3 to -8 dBm. The wide operating range is attributed to wide bandwidth driver and matching structure based on broadband open and short leading to >40dB difference between fundamental and second harmonic power at the output. The doubler-amplifier combination has the comparable output power and a larger operating frequency range than 200-300 GHz COTS GaAs modules.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"15 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120852842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508315
Eli Schwartz, S. Anderson, Alex Mostov, Ilya Sima, Udi Suissa, Ron Pongratz, Amit Ezer, A. Cohen, Michael Gulko, Nadav Snir, A. Elazari, A. Bauer
A new approach to PA design in CMOS for 802.11ac that achieves -35dB EVM with output power higher than 100mW and EVM floor of -47dB is demonstrated. The PA is designed to be operated as part of a configurable RF front-end module and meets the requirements for various WiFi standards including 802.11ac.
{"title":"A 20dBm configurable linear CMOS RF power amplifier for multi-standard transmitters","authors":"Eli Schwartz, S. Anderson, Alex Mostov, Ilya Sima, Udi Suissa, Ron Pongratz, Amit Ezer, A. Cohen, Michael Gulko, Nadav Snir, A. Elazari, A. Bauer","doi":"10.1109/RFIC.2016.7508315","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508315","url":null,"abstract":"A new approach to PA design in CMOS for 802.11ac that achieves -35dB EVM with output power higher than 100mW and EVM floor of -47dB is demonstrated. The PA is designed to be operated as part of a configurable RF front-end module and meets the requirements for various WiFi standards including 802.11ac.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130000301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/RFIC.2016.7508321
Sushil Subramanian, H. Hashemi
A 200 MSPS reconfigurable and blocker resilient analog-to-digital converter (ADC) is presented. The system consists of a discrete-time lossy differentiator frontend and a 6-bit noise shaping, pipeline ADC backend, which enables tolerance of a <;3 MHz narrowband blocker up to 40 dB stronger than the desired signal. Filtering in the presence of the blocker improves quantization by an additional 3 bits to accommodate the desired signal. With lower blocker power, the system defaults to Nyquist performance and an additional reconfiguration switch enables a 3-6 MHz, ΔΣ ADC. The system is designed in a 65 nm CMOS technology, has a total chip area of 1040 μm × 920 μm, and consumes 6.37 mW of power. Enabling blocker resilience improves the figure-of-merit (FOM) of the system from 474 fJ/lvl to 158 fJ/lvl.
{"title":"A 200 MSPS reconfigurable ADC with adjacent channel narrowband blocker resiliency","authors":"Sushil Subramanian, H. Hashemi","doi":"10.1109/RFIC.2016.7508321","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508321","url":null,"abstract":"A 200 MSPS reconfigurable and blocker resilient analog-to-digital converter (ADC) is presented. The system consists of a discrete-time lossy differentiator frontend and a 6-bit noise shaping, pipeline ADC backend, which enables tolerance of a <;3 MHz narrowband blocker up to 40 dB stronger than the desired signal. Filtering in the presence of the blocker improves quantization by an additional 3 bits to accommodate the desired signal. With lower blocker power, the system defaults to Nyquist performance and an additional reconfiguration switch enables a 3-6 MHz, ΔΣ ADC. The system is designed in a 65 nm CMOS technology, has a total chip area of 1040 μm × 920 μm, and consumes 6.37 mW of power. Enabling blocker resilience improves the figure-of-merit (FOM) of the system from 474 fJ/lvl to 158 fJ/lvl.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133798458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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