Pub Date : 1994-03-29DOI: 10.1109/SOUTHC.1994.498109
K. Shih, D. Klemer, J. Liou
This paper presents results of the use of a device-physics-based MESFET analysis code to predict the effects of process-induced variations on MESFET parameters. Such an approach is useful for predicting device yields and sensitivities of device parameters to variations in device fabrication processes such as gate recess depth and device dimensions. Our simulation is general in the sense that it can allow for arbitrary doping profiles and velocity-field characteristics.
{"title":"Prediction of GaAs MESFET process-induced variations using a device-physics-based analytical model","authors":"K. Shih, D. Klemer, J. Liou","doi":"10.1109/SOUTHC.1994.498109","DOIUrl":"https://doi.org/10.1109/SOUTHC.1994.498109","url":null,"abstract":"This paper presents results of the use of a device-physics-based MESFET analysis code to predict the effects of process-induced variations on MESFET parameters. Such an approach is useful for predicting device yields and sensitivities of device parameters to variations in device fabrication processes such as gate recess depth and device dimensions. Our simulation is general in the sense that it can allow for arbitrary doping profiles and velocity-field characteristics.","PeriodicalId":164672,"journal":{"name":"Conference Record Southcon","volume":"834 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133314079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-03-29DOI: 10.1109/SOUTHC.1994.498095
O. Crisalle, H. M. Mahon, D. Bonvin
The robust stability of control systems containing a plant with ellipsoidal parametric uncertainties can be analyzed using the critical-direction technique. This paper presents a succinct review of the analysis technique, and proposes two methods for synthesizing robust controllers. A simple water-heating control system with a discrete PI controller is used for illustrating the analysis and synthesis methods. The uncertainty in the plant parameters is quantified in terms of an ellipsoid derived from the results of standard parameter estimation methods. The nominal plant parameters are used to tune three candidate PI controllers using standard techniques, and then the robustness of each controller is analyzed. It is verified that the controllers cannot be stabilized from knowledge of the nominal process alone. Finally, two alternative robust control designs are realized via numerical optimization and are compared.
{"title":"Study of robust control designs using the critical-direction method for ellipsoidal uncertainties","authors":"O. Crisalle, H. M. Mahon, D. Bonvin","doi":"10.1109/SOUTHC.1994.498095","DOIUrl":"https://doi.org/10.1109/SOUTHC.1994.498095","url":null,"abstract":"The robust stability of control systems containing a plant with ellipsoidal parametric uncertainties can be analyzed using the critical-direction technique. This paper presents a succinct review of the analysis technique, and proposes two methods for synthesizing robust controllers. A simple water-heating control system with a discrete PI controller is used for illustrating the analysis and synthesis methods. The uncertainty in the plant parameters is quantified in terms of an ellipsoid derived from the results of standard parameter estimation methods. The nominal plant parameters are used to tune three candidate PI controllers using standard techniques, and then the robustness of each controller is analyzed. It is verified that the controllers cannot be stabilized from knowledge of the nominal process alone. Finally, two alternative robust control designs are realized via numerical optimization and are compared.","PeriodicalId":164672,"journal":{"name":"Conference Record Southcon","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133005500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-03-29DOI: 10.1109/SOUTHC.1994.498154
R. G. Deshmukh, G.N. Hawat
The objective of this paper is to analyze the behavior of sequential machines by experimental means. Experiments are concerned with state-identification to identify the initial and final state of the machine. A computer program is developed which accepts, as input, a state table of Mealy type (any number of states) machine and builds the successor trees and finds the minimized distinguishing, homing, and synchronizing sequences. The program identifies the levels of the nodes and also lists all groups at each successor node of the tree. Additionally, flags are set when a terminal node is reached or a solution is obtained. The program, written in Pascal, is executed on the Vax 11/780 computer.
{"title":"An algorithm to determine shortest length distinguishing, homing, and synchronizing sequences for sequential machines","authors":"R. G. Deshmukh, G.N. Hawat","doi":"10.1109/SOUTHC.1994.498154","DOIUrl":"https://doi.org/10.1109/SOUTHC.1994.498154","url":null,"abstract":"The objective of this paper is to analyze the behavior of sequential machines by experimental means. Experiments are concerned with state-identification to identify the initial and final state of the machine. A computer program is developed which accepts, as input, a state table of Mealy type (any number of states) machine and builds the successor trees and finds the minimized distinguishing, homing, and synchronizing sequences. The program identifies the levels of the nodes and also lists all groups at each successor node of the tree. Additionally, flags are set when a terminal node is reached or a solution is obtained. The program, written in Pascal, is executed on the Vax 11/780 computer.","PeriodicalId":164672,"journal":{"name":"Conference Record Southcon","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123555461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-03-29DOI: 10.1109/SOUTHC.1994.498124
R. Mercer, M. Ebel, Ronald F. DeMara
Nanomechanical computing elements which are scalable in terms of input size and depth of propagation path are analyzed using a bounded continuum model. Boolean logic functions of NOT, AND, OR, and XOR are realized using helical latch, reset spring, and translating rod assemblies. Building upon these components a design for two-level logic operations is presented. The helical latching mechanism calculates the Boolean output function as a positional displacement from a known reset state, which occurs exactly once during each instruction cycle. To balance forces a symmetrical rotor is used to counteract applied forces by replicating input rods. This has the beneficial side-effect of providing intrinsic fault-detection capability within a gate and also decreases the rotation required for a full cycle from 360 degrees to 180 degrees. This design is further enhanced to allow operations of arbitrary word length by subdividing the logic disc into sectors where each sector contains all the components necessary to operate on a single bit. The benefits of increasing the disc diameter needed for additional bits include a further reduction in disc cycle rotation as a result of subdividing the disc into sectors. Since the inputs are sampled sequentially, throughput of resultants can be increased directly by pipelining multiple bit operands. For n inputs per logic gate, the maximum speedup for a single level of logic is (n+2). Generally, speedup is bounded by (n+2)/p where p denotes the number of cycles between initiations of the pipe.
{"title":"Pipelined architecture for computational nanotechnology","authors":"R. Mercer, M. Ebel, Ronald F. DeMara","doi":"10.1109/SOUTHC.1994.498124","DOIUrl":"https://doi.org/10.1109/SOUTHC.1994.498124","url":null,"abstract":"Nanomechanical computing elements which are scalable in terms of input size and depth of propagation path are analyzed using a bounded continuum model. Boolean logic functions of NOT, AND, OR, and XOR are realized using helical latch, reset spring, and translating rod assemblies. Building upon these components a design for two-level logic operations is presented. The helical latching mechanism calculates the Boolean output function as a positional displacement from a known reset state, which occurs exactly once during each instruction cycle. To balance forces a symmetrical rotor is used to counteract applied forces by replicating input rods. This has the beneficial side-effect of providing intrinsic fault-detection capability within a gate and also decreases the rotation required for a full cycle from 360 degrees to 180 degrees. This design is further enhanced to allow operations of arbitrary word length by subdividing the logic disc into sectors where each sector contains all the components necessary to operate on a single bit. The benefits of increasing the disc diameter needed for additional bits include a further reduction in disc cycle rotation as a result of subdividing the disc into sectors. Since the inputs are sampled sequentially, throughput of resultants can be increased directly by pipelining multiple bit operands. For n inputs per logic gate, the maximum speedup for a single level of logic is (n+2). Generally, speedup is bounded by (n+2)/p where p denotes the number of cycles between initiations of the pipe.","PeriodicalId":164672,"journal":{"name":"Conference Record Southcon","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123885805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-03-29DOI: 10.1109/SOUTHC.1994.498100
P. Wiesner
As more engineers become self-employed or employed in small organizations, electronic media will deliver an increasingly flexible system of continuing education for updating engineers. Future engineers will have access to online educational services. This will bring an integration of video, audio, and voice to the home and place of business via a vast "electronic super-highway" and provide updates on technology and information relevant to career development. The challenge is for industry, universities, government, and professional societies to cooperate in developing a relevant curriculum for lifelong learning.
{"title":"Meeting educational needs through electronic delivery systems","authors":"P. Wiesner","doi":"10.1109/SOUTHC.1994.498100","DOIUrl":"https://doi.org/10.1109/SOUTHC.1994.498100","url":null,"abstract":"As more engineers become self-employed or employed in small organizations, electronic media will deliver an increasingly flexible system of continuing education for updating engineers. Future engineers will have access to online educational services. This will bring an integration of video, audio, and voice to the home and place of business via a vast \"electronic super-highway\" and provide updates on technology and information relevant to career development. The challenge is for industry, universities, government, and professional societies to cooperate in developing a relevant curriculum for lifelong learning.","PeriodicalId":164672,"journal":{"name":"Conference Record Southcon","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129902052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-03-29DOI: 10.1109/SOUTHC.1994.498112
A. Ortiz-Conde, F. Garcia Sanchez, J. Liou, J. Andrian, R. Laurence, P. E. Schmidt
A simple technique, based on integrating the current-voltage characteristics, is proposed to determine series resistance and other device parameters of a two-terminal device. The case of the diode is used to illustrate the usefulness of the technique.
{"title":"A method to extract parameters in a generalized two-terminal device","authors":"A. Ortiz-Conde, F. Garcia Sanchez, J. Liou, J. Andrian, R. Laurence, P. E. Schmidt","doi":"10.1109/SOUTHC.1994.498112","DOIUrl":"https://doi.org/10.1109/SOUTHC.1994.498112","url":null,"abstract":"A simple technique, based on integrating the current-voltage characteristics, is proposed to determine series resistance and other device parameters of a two-terminal device. The case of the diode is used to illustrate the usefulness of the technique.","PeriodicalId":164672,"journal":{"name":"Conference Record Southcon","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115198658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-03-29DOI: 10.1109/SOUTHC.1994.498153
C. Melear
The M68300 and M68HC16 families of microcontrollers have been available for several years. They are based on an Intermodule Bus concept where modules, such as CPUs or timers or serial ports, are connected together and communicate through a standardized bus. Using this overall design technique modules can be chosen from a library of modules and then, using CAD tools, the modules can be arranged in a "best fit" square and connected using the Intermodule Bus. The idea of running multiple tasks in the microcontroller world has a very great amount of merit when considering that many of the tasks are completely independent. The article discusses the advent of intelligent, programmable peripheral elements.
{"title":"Programming peripheral modules of the MC68300 and MC68HC16 microcontrollers","authors":"C. Melear","doi":"10.1109/SOUTHC.1994.498153","DOIUrl":"https://doi.org/10.1109/SOUTHC.1994.498153","url":null,"abstract":"The M68300 and M68HC16 families of microcontrollers have been available for several years. They are based on an Intermodule Bus concept where modules, such as CPUs or timers or serial ports, are connected together and communicate through a standardized bus. Using this overall design technique modules can be chosen from a library of modules and then, using CAD tools, the modules can be arranged in a \"best fit\" square and connected using the Intermodule Bus. The idea of running multiple tasks in the microcontroller world has a very great amount of merit when considering that many of the tasks are completely independent. The article discusses the advent of intelligent, programmable peripheral elements.","PeriodicalId":164672,"journal":{"name":"Conference Record Southcon","volume":"172 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115662307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-03-29DOI: 10.1109/SOUTHC.1994.498088
T. Li
This paper emphasizes the infrared sensor/detector packaging. Electro-optical (E-O) sensor packaging is a challenging task. By its nature, it requires one to complete two missions: 1) to expose the sensing element in order to interact with the environment "transparently" while detecting the surrounding and 2) to protect sensitive electronics from the harsh environment.
{"title":"Electro-optical sensor packaging overview","authors":"T. Li","doi":"10.1109/SOUTHC.1994.498088","DOIUrl":"https://doi.org/10.1109/SOUTHC.1994.498088","url":null,"abstract":"This paper emphasizes the infrared sensor/detector packaging. Electro-optical (E-O) sensor packaging is a challenging task. By its nature, it requires one to complete two missions: 1) to expose the sensing element in order to interact with the environment \"transparently\" while detecting the surrounding and 2) to protect sensitive electronics from the harsh environment.","PeriodicalId":164672,"journal":{"name":"Conference Record Southcon","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114189917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-03-29DOI: 10.1109/SOUTHC.1994.498165
A. Khan, I. Batarseh, K. Siri, J. Elias
In this paper, we present two modified boost converter topologies to be used as power factor correction circuits. Zero-voltage switching and proper transformer-core resetting are achieved utilizing the parasitic capacitance of the switch and the magnetization inductance of the transformer. Steady state analysis for the two circuits is given. To verify our theoretical approval, simulation results are reported.
{"title":"Boost power factor correction circuits","authors":"A. Khan, I. Batarseh, K. Siri, J. Elias","doi":"10.1109/SOUTHC.1994.498165","DOIUrl":"https://doi.org/10.1109/SOUTHC.1994.498165","url":null,"abstract":"In this paper, we present two modified boost converter topologies to be used as power factor correction circuits. Zero-voltage switching and proper transformer-core resetting are achieved utilizing the parasitic capacitance of the switch and the magnetization inductance of the transformer. Steady state analysis for the two circuits is given. To verify our theoretical approval, simulation results are reported.","PeriodicalId":164672,"journal":{"name":"Conference Record Southcon","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123914884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-03-29DOI: 10.1109/SOUTHC.1994.498132
M. Elbert, C. Mpagazehe, T. Weyant
The importance of product quality and reliability, time to market, cost and customer satisfaction continue to grow as the competitive battlefield expands. The most effective way to qualify a product and to assure that a product will meet its reliability and quality goals and be introduced to the market on time and within budget is through stress testing. Stress Test is the method where the products are subjected to the application of highly accelerated controlled stresses such as thermal, vibration, etc. Stress testing precipitates latent defects into identifiable defects. The experiences indicate that failures/symptoms brought out in Stress Test typically become field reliability problems if not corrected. Stress testing is now recognized as an essential element of design and manufacturing process that results in improved product reliability and quality and reduced overall design and manufacturing, warranty, and field service costs. The purpose of this paper is to present our approach in this area. A special stress testing strategy is developed and recommended.
{"title":"Stress testing and reliability","authors":"M. Elbert, C. Mpagazehe, T. Weyant","doi":"10.1109/SOUTHC.1994.498132","DOIUrl":"https://doi.org/10.1109/SOUTHC.1994.498132","url":null,"abstract":"The importance of product quality and reliability, time to market, cost and customer satisfaction continue to grow as the competitive battlefield expands. The most effective way to qualify a product and to assure that a product will meet its reliability and quality goals and be introduced to the market on time and within budget is through stress testing. Stress Test is the method where the products are subjected to the application of highly accelerated controlled stresses such as thermal, vibration, etc. Stress testing precipitates latent defects into identifiable defects. The experiences indicate that failures/symptoms brought out in Stress Test typically become field reliability problems if not corrected. Stress testing is now recognized as an essential element of design and manufacturing process that results in improved product reliability and quality and reduced overall design and manufacturing, warranty, and field service costs. The purpose of this paper is to present our approach in this area. A special stress testing strategy is developed and recommended.","PeriodicalId":164672,"journal":{"name":"Conference Record Southcon","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121953102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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