Pub Date : 2021-01-17DOI: 10.1109/sirf51851.2021.9383372
{"title":"SiRF 2021 Table of Contents","authors":"","doi":"10.1109/sirf51851.2021.9383372","DOIUrl":"https://doi.org/10.1109/sirf51851.2021.9383372","url":null,"abstract":"","PeriodicalId":166842,"journal":{"name":"2021 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":" 16","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120831799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-17DOI: 10.1109/SiRF51851.2021.9383330
B. Jann, Sanket Jain, A. Ravi, S. Patnaik, A. Natarajan
Power consumption of integrated mm-wave receiver (RX) arrays is a critical barrier for evolution from mm-wave phased arrays to full mm-wave MIMO arrays that support digital multi beam-forming. In this paper, we propose two low-power mm-wave 16nm FinFET RX front-ends that leverage a novel power and area-efficient multi-phase LO approach to enable low-power clock distribution. In the first approach, an injection locked oscillator uses multi-phase signals to produce desired mm-wave LO for the RF mixers. In the second approach, a novel sub-harmonic mixer is used to down-convert the mm-Wave signal using a multi-phase LO at 1/5th the input mm-wave frequency. The two RX implementations achieve 55dB (53dB) gain across an input bandwidth of 23-26GHz with in-band noise figure of 5.4dB (5dB) and consuming 82mW (67mW) power per element. A key contribution is state-of-the-art power consumption in LO distribution of 27mW (24mW) making these approaches amenable to large-scale phased arrays.
{"title":"28GHz RX frontends with sub-harmonic-based mm-wave LO Generation in 16nm FinFET","authors":"B. Jann, Sanket Jain, A. Ravi, S. Patnaik, A. Natarajan","doi":"10.1109/SiRF51851.2021.9383330","DOIUrl":"https://doi.org/10.1109/SiRF51851.2021.9383330","url":null,"abstract":"Power consumption of integrated mm-wave receiver (RX) arrays is a critical barrier for evolution from mm-wave phased arrays to full mm-wave MIMO arrays that support digital multi beam-forming. In this paper, we propose two low-power mm-wave 16nm FinFET RX front-ends that leverage a novel power and area-efficient multi-phase LO approach to enable low-power clock distribution. In the first approach, an injection locked oscillator uses multi-phase signals to produce desired mm-wave LO for the RF mixers. In the second approach, a novel sub-harmonic mixer is used to down-convert the mm-Wave signal using a multi-phase LO at 1/5th the input mm-wave frequency. The two RX implementations achieve 55dB (53dB) gain across an input bandwidth of 23-26GHz with in-band noise figure of 5.4dB (5dB) and consuming 82mW (67mW) power per element. A key contribution is state-of-the-art power consumption in LO distribution of 27mW (24mW) making these approaches amenable to large-scale phased arrays.","PeriodicalId":166842,"journal":{"name":"2021 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123666867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-17DOI: 10.1109/SiRF51851.2021.9383413
K. T. M. Shafi, Varuna Baipadi, V. Vanukuru
A potentially significant limitation of typical short structure in de-embedding launch line inductance with ground-signal-ground (GSG) padsets is revealed in this paper. It is shown that the calculated inductance (L) value with conventional open-short-pad (OSP) de-embedding is significantly higher than the actual value. With the help of electro-magnetic (EM) simulations, the mechanism behind this inaccurate short de-embedding for L calculation is demonstrated. A simple alternative short structure is proposed to alleviate this issue. The proposed structure is extensively validated using well calibrated EM simulations across inductor geometries. Finally, measured result of spiral inductor with GSG padsets validate the merit of the proposed approach.
{"title":"Layout Optimization of Short De-embedding Structure for Accurate On-Chip Inductor Characterization","authors":"K. T. M. Shafi, Varuna Baipadi, V. Vanukuru","doi":"10.1109/SiRF51851.2021.9383413","DOIUrl":"https://doi.org/10.1109/SiRF51851.2021.9383413","url":null,"abstract":"A potentially significant limitation of typical short structure in de-embedding launch line inductance with ground-signal-ground (GSG) padsets is revealed in this paper. It is shown that the calculated inductance (L) value with conventional open-short-pad (OSP) de-embedding is significantly higher than the actual value. With the help of electro-magnetic (EM) simulations, the mechanism behind this inaccurate short de-embedding for L calculation is demonstrated. A simple alternative short structure is proposed to alleviate this issue. The proposed structure is extensively validated using well calibrated EM simulations across inductor geometries. Finally, measured result of spiral inductor with GSG padsets validate the merit of the proposed approach.","PeriodicalId":166842,"journal":{"name":"2021 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125097661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-17DOI: 10.1109/SiRF51851.2021.9383369
Rumeng Wang, Jinge Li, C. Shi, Jinghong Chen, Runxi Zhang
This paper presents a mmW voltage-controlled oscillator (VCO) employing stacked-coupled switched differential inductor (SSDI) and hybrid analog-digital varactor array (HVA) to simultaneously achieve wide tuning range and low phase noise. A frequency co-tuned VCO buffer is also developed to minimize the VCO output power variation. Fabricated in a 55-nm CMOS process, the VCO achieves an ultra-wide frequency tuning range of 41.14% (24.48 to 37.16 GHz) and a low phase noise of -124.91 dBc/Hz at 10 MHz offset. The FoMT is -192.67 dBc/Hz and the output power variation is less than 3 dB over the entire tuning range.
{"title":"A 25–37GHz VCO Employing Stacked-Coupled Switched Inductor and Co-Tuned Buffer in 55nm CMOS for Multi-Band 5G mmW Applications","authors":"Rumeng Wang, Jinge Li, C. Shi, Jinghong Chen, Runxi Zhang","doi":"10.1109/SiRF51851.2021.9383369","DOIUrl":"https://doi.org/10.1109/SiRF51851.2021.9383369","url":null,"abstract":"This paper presents a mmW voltage-controlled oscillator (VCO) employing stacked-coupled switched differential inductor (SSDI) and hybrid analog-digital varactor array (HVA) to simultaneously achieve wide tuning range and low phase noise. A frequency co-tuned VCO buffer is also developed to minimize the VCO output power variation. Fabricated in a 55-nm CMOS process, the VCO achieves an ultra-wide frequency tuning range of 41.14% (24.48 to 37.16 GHz) and a low phase noise of -124.91 dBc/Hz at 10 MHz offset. The FoMT is -192.67 dBc/Hz and the output power variation is less than 3 dB over the entire tuning range.","PeriodicalId":166842,"journal":{"name":"2021 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132180331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-17DOI: 10.1109/SiRF51851.2021.9383419
M. V. Thayyil, Jan Plíva, Mengqi Cui, N. Joram, F. Ellinger
This work presents the design and characterization of a millimeter wave integrated quasi-circulator implemented in a 22 nm fully depleted silicon on insulator technology, targeting single antenna radio frequency identification systems. The design is based on a Wilkinson power divider and a common-gate loss compensation amplifier. Characterization results show that all ports are matched to 50Ω with magnitude of input reflection coefficients better than -10 dB. The measured transmit port to antenna port insertion loss is 5.7 dB, and the antenna port to receive port gain is 2 dB. The power amplifier port to loss compensation amplifier isolation is greater than 20 dB in the 57 GHz to 63 GHz frequency range, with a maximum of 32 dB. The circuit consumes 5.4mW power and occupies an area of 0.49 mm2. To the knowledge of the authors, the design has one of the best reported combinations of isolation, power consumption and occupied area among integrated quasi-circulators.
{"title":"A 60 GHz Low Power Integrated Quasi-Circulator in 22 nm FDSOI Technology","authors":"M. V. Thayyil, Jan Plíva, Mengqi Cui, N. Joram, F. Ellinger","doi":"10.1109/SiRF51851.2021.9383419","DOIUrl":"https://doi.org/10.1109/SiRF51851.2021.9383419","url":null,"abstract":"This work presents the design and characterization of a millimeter wave integrated quasi-circulator implemented in a 22 nm fully depleted silicon on insulator technology, targeting single antenna radio frequency identification systems. The design is based on a Wilkinson power divider and a common-gate loss compensation amplifier. Characterization results show that all ports are matched to 50Ω with magnitude of input reflection coefficients better than -10 dB. The measured transmit port to antenna port insertion loss is 5.7 dB, and the antenna port to receive port gain is 2 dB. The power amplifier port to loss compensation amplifier isolation is greater than 20 dB in the 57 GHz to 63 GHz frequency range, with a maximum of 32 dB. The circuit consumes 5.4mW power and occupies an area of 0.49 mm2. To the knowledge of the authors, the design has one of the best reported combinations of isolation, power consumption and occupied area among integrated quasi-circulators.","PeriodicalId":166842,"journal":{"name":"2021 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128784857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-17DOI: 10.1109/SiRF51851.2021.9383348
O. Foissey, F. Gianesello, V. Gidel, C. Durand, A. Gauthier, N. Guitard, P. Chevalier, M. Hello, J. A. Gonçalves, D. Gloria, V. Velayudhan, J. Lugo
In this paper, an innovative PIN diode architecture is proposed and implemented in a 55 nm BiCMOS technology. While ensuring a reverse breakdown voltage < -11 V, a state-of-the-art RON × COFF of 85 fs is achieved and benchmarked with the literature. Those excellent performances pave the way for the development of high performances and highly integrated 5G and 6G millimeter Wave (mmW) Front-End Modules (FEM) in advanced BiCMOS technologies.
{"title":"85 fs RON×COFF and CP1dB@28GHz > 25dBm Innovative PIN Diode Integrated in 55 nm BiCMOS Technology Targeting mmW 5G and 6G Front End Module","authors":"O. Foissey, F. Gianesello, V. Gidel, C. Durand, A. Gauthier, N. Guitard, P. Chevalier, M. Hello, J. A. Gonçalves, D. Gloria, V. Velayudhan, J. Lugo","doi":"10.1109/SiRF51851.2021.9383348","DOIUrl":"https://doi.org/10.1109/SiRF51851.2021.9383348","url":null,"abstract":"In this paper, an innovative PIN diode architecture is proposed and implemented in a 55 nm BiCMOS technology. While ensuring a reverse breakdown voltage < -11 V, a state-of-the-art RON × COFF of 85 fs is achieved and benchmarked with the literature. Those excellent performances pave the way for the development of high performances and highly integrated 5G and 6G millimeter Wave (mmW) Front-End Modules (FEM) in advanced BiCMOS technologies.","PeriodicalId":166842,"journal":{"name":"2021 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127611212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-17DOI: 10.1109/SiRF51851.2021.9383421
Amit Jha, Jieyin Zheng, C. Masse, P. Hurwitz, S. Chaudhry
Using a multiple gated transistor core (MGTR) with different channel lengths, a 5.4GHz LNA in 130nm SOI CMOS is demonstrated. Using a 1V supply and consuming 3mA current, LNA has 10.8dB gain, 0.65dB NF, 6dBm IIP3. The LNA is matched at input and output from 5-6GHz using high Q on-chip inductors in high resistive substrate. The LNA achieves state-of-the-art NF compared to LNAs employing MGTR and other linearization techniques, as well as the highest figure of merits, FOM2 & FOM3 in published LNAs.
采用不同通道长度的多门控晶体管核(MGTR)，在130nm SOI CMOS中演示了5.4GHz LNA。使用1V电源，消耗3mA电流，LNA具有10.8dB增益，0.65dB NF, 6dBm IIP3。LNA在5-6GHz的输入和输出范围内匹配，采用高Q片上电感，采用高电阻衬底。与使用MGTR和其他线性化技术的LNA相比，LNA实现了最先进的NF，以及已发表的LNA中最高的优点，FOM2和FOM3。
{"title":"A 5.4GHz 0.65dB NF 6dBm IIP3 MGTR LNA in 130nm SOI CMOS","authors":"Amit Jha, Jieyin Zheng, C. Masse, P. Hurwitz, S. Chaudhry","doi":"10.1109/SiRF51851.2021.9383421","DOIUrl":"https://doi.org/10.1109/SiRF51851.2021.9383421","url":null,"abstract":"Using a multiple gated transistor core (MGTR) with different channel lengths, a 5.4GHz LNA in 130nm SOI CMOS is demonstrated. Using a 1V supply and consuming 3mA current, LNA has 10.8dB gain, 0.65dB NF, 6dBm IIP3. The LNA is matched at input and output from 5-6GHz using high Q on-chip inductors in high resistive substrate. The LNA achieves state-of-the-art NF compared to LNAs employing MGTR and other linearization techniques, as well as the highest figure of merits, FOM2 & FOM3 in published LNAs.","PeriodicalId":166842,"journal":{"name":"2021 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134242351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-17DOI: 10.1109/SiRF51851.2021.9383397
Amit Jha, K. O
A measurement setup including a metal plate probe mounted on a micrometer-controlled positioner is used to quantify the effects of surrounding to voltage-controlled oscillator (VCO) characteristics. Including a metal ring shield around the inductor of LC-VCO and placing components underneath the inductor to reduce the circuit area lower the sensitivity of VCO performance to surroundings. It should be possible to incorporate a metal plate on top of the oscillator as part of packaging to shield the VCO from the surrounding with tolerable impact to the oscillator performance.
{"title":"Frequency Sensitivity of Integrated Oscillators to Nearby Conductors","authors":"Amit Jha, K. O","doi":"10.1109/SiRF51851.2021.9383397","DOIUrl":"https://doi.org/10.1109/SiRF51851.2021.9383397","url":null,"abstract":"A measurement setup including a metal plate probe mounted on a micrometer-controlled positioner is used to quantify the effects of surrounding to voltage-controlled oscillator (VCO) characteristics. Including a metal ring shield around the inductor of LC-VCO and placing components underneath the inductor to reduce the circuit area lower the sensitivity of VCO performance to surroundings. It should be possible to incorporate a metal plate on top of the oscillator as part of packaging to shield the VCO from the surrounding with tolerable impact to the oscillator performance.","PeriodicalId":166842,"journal":{"name":"2021 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129894369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-17DOI: 10.1109/sirf51851.2021.9383334
{"title":"SiRF 2021 Final Program","authors":"","doi":"10.1109/sirf51851.2021.9383334","DOIUrl":"https://doi.org/10.1109/sirf51851.2021.9383334","url":null,"abstract":"","PeriodicalId":166842,"journal":{"name":"2021 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121699783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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