Pub Date : 2012-04-23DOI: 10.1109/VTS.2012.6231100
Jinsuk Chung, N. Touba
An alternative to masking unknown (X) values before the compactor (i.e., X-masking) is to capture X's in the MISR and cancel them out after compaction (i.e., X-canceling). Existing X-canceling methodologies require a number of control bits to perform the X-canceling that is linear in the number of X's to be canceled. This paper describes a new methodology for X-canceling which can exploit the fact that the scan cells in which X's are captured tend to be highly correlated in order to significantly reduce the number of control bits required for X-canceling. X's tend to be generated in certain portions of the design, and hence certain scan cells capture X's with much higher frequency than other scan cells. Instead of custom generating the control bits to cancel out only the X's in one MISR signature, the proposed approach finds a general superset solution which can cancel out the X's for many MISR signatures. This allows the same control bits to be reused many times thereby significantly improving the amount of compression that can be obtained. Architectures for implementing superset X-canceling are described along with experimental results.
{"title":"Exploiting X-correlation in output compression via superset X-canceling","authors":"Jinsuk Chung, N. Touba","doi":"10.1109/VTS.2012.6231100","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231100","url":null,"abstract":"An alternative to masking unknown (X) values before the compactor (i.e., X-masking) is to capture X's in the MISR and cancel them out after compaction (i.e., X-canceling). Existing X-canceling methodologies require a number of control bits to perform the X-canceling that is linear in the number of X's to be canceled. This paper describes a new methodology for X-canceling which can exploit the fact that the scan cells in which X's are captured tend to be highly correlated in order to significantly reduce the number of control bits required for X-canceling. X's tend to be generated in certain portions of the design, and hence certain scan cells capture X's with much higher frequency than other scan cells. Instead of custom generating the control bits to cancel out only the X's in one MISR signature, the proposed approach finds a general superset solution which can cancel out the X's for many MISR signatures. This allows the same control bits to be reused many times thereby significantly improving the amount of compression that can be obtained. Architectures for implementing superset X-canceling are described along with experimental results.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114824879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VTS.2012.6231098
A. Czutro, M. Sauer, Tobias Schubert, I. Polian, B. Becker
Failures caused by phenomena such as crosstalk or power-supply noise are gaining in importance in advanced nanoscale technologies. The detection of such complex defects benefits from the satisfaction of certain constraints, for instance justifying specific transitions on neighbouring lines of the defect location. We present a SAT-based ATPG-tool that supports the enhanced conditional multiple-stuck-at fault model (ECMS@). This model can specify multiple fault locations along with a set of hard conditions imposed on arbitrary lines; hard conditions must hold in order for the fault effect to become active. Additionally, optimisation constraints that may be required for best coverage can be specified via a set of soft conditions. The introduced tool justifies as many of these conditions as possible, using a mechanism known as SAT with preferences. Several applications are discussed and evaluated by extensive experimental data. Furthermore, a novel fault-clustering technique is introduced, thanks to which the time required to classify all stuck-at faults in a suite of industrial benchmarks was reduced by up to 65%.
{"title":"SAT-ATPG using preferences for improved detection of complex defect mechanisms","authors":"A. Czutro, M. Sauer, Tobias Schubert, I. Polian, B. Becker","doi":"10.1109/VTS.2012.6231098","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231098","url":null,"abstract":"Failures caused by phenomena such as crosstalk or power-supply noise are gaining in importance in advanced nanoscale technologies. The detection of such complex defects benefits from the satisfaction of certain constraints, for instance justifying specific transitions on neighbouring lines of the defect location. We present a SAT-based ATPG-tool that supports the enhanced conditional multiple-stuck-at fault model (ECMS@). This model can specify multiple fault locations along with a set of hard conditions imposed on arbitrary lines; hard conditions must hold in order for the fault effect to become active. Additionally, optimisation constraints that may be required for best coverage can be specified via a set of soft conditions. The introduced tool justifies as many of these conditions as possible, using a mechanism known as SAT with preferences. Several applications are discussed and evaluated by extensive experimental data. Furthermore, a novel fault-clustering technique is introduced, thanks to which the time required to classify all stuck-at faults in a suite of industrial benchmarks was reduced by up to 65%.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114890875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VTS.2012.6231091
Francisco J. Galarza-Medina, J. L. Garcia-Gervacio, V. Champac, A. Orailoglu
Detection of Small Delay Defects (SDDs) is a major concern in modern circuits using nanometer technologies. They are difficult to test and an important source of test escapes, and even when SDDs do not produce functional failures, they represent a reliability risk. The detection of these defects aggravates in the presence of process variations. In this paper, a methodology to detect SDDs in the presence of process variations using delay correlation information between paths of a circuit is proposed. This methodology exploits the concept that for two highly correlated paths, an important part of the delay variance in one path can be described by the delay variance in the second path. The methodology has been further extended to consider multiple path correlation thus improving the detection of SDDs. This methodology is able to distinguish delay defects from process variations. A metric is also proposed to quantify the SDD screenable variance that represents the percentage of variance where a defect can be detected. A statistical timing analysis framework has been developed and implemented to compute timing information and Inter-Path Correlation (IPC). Spatial and structural correlation, and random dopant fluctuations are considered. Simulation results in 74LS85 and ISCAS85 benchmark circuits evince the feasibility of the proposed methodology.
{"title":"Small-delay defects detection under process variation using Inter-Path Correlation","authors":"Francisco J. Galarza-Medina, J. L. Garcia-Gervacio, V. Champac, A. Orailoglu","doi":"10.1109/VTS.2012.6231091","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231091","url":null,"abstract":"Detection of Small Delay Defects (SDDs) is a major concern in modern circuits using nanometer technologies. They are difficult to test and an important source of test escapes, and even when SDDs do not produce functional failures, they represent a reliability risk. The detection of these defects aggravates in the presence of process variations. In this paper, a methodology to detect SDDs in the presence of process variations using delay correlation information between paths of a circuit is proposed. This methodology exploits the concept that for two highly correlated paths, an important part of the delay variance in one path can be described by the delay variance in the second path. The methodology has been further extended to consider multiple path correlation thus improving the detection of SDDs. This methodology is able to distinguish delay defects from process variations. A metric is also proposed to quantify the SDD screenable variance that represents the percentage of variance where a defect can be detected. A statistical timing analysis framework has been developed and implemented to compute timing information and Inter-Path Correlation (IPC). Spatial and structural correlation, and random dopant fluctuations are considered. Simulation results in 74LS85 and ISCAS85 benchmark circuits evince the feasibility of the proposed methodology.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116338665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VTS.2012.6231086
O. Yaglioglu, B. Eldridge
Testing of Through Silicon Via (TSV) and Micro-Bump (MB) devices by physical connection through the TSVs presents unique challenges due to the very high density of the connections, and the potential impact of contact testing on subsequent assembly steps. In addition, the very high signal counts that are the main benefit of TSV connection schemes make conventional wafer probing, particularly for memory devices which demand very high parallelism at production wafer sort, largely impractical. We present a socket solution using FormFactor Nanopierce™ contactor for direct testing of TSV's and micro-bumps arrays which enables creation of known good TSV dies for high yield stacking and known good TSV stacks for shipment to system assemblers to achieve high yield assembly. Combining this socket solution with existing full wafer contact probe solutions enables a complete TSV test flow. In addition, standard TSV interface designs and patterns can enable standard sockets. The FormFactor NanoPierce™ contactor is highly scalable and easy to fabricate at very dense pitches down to 20μm. The contactor relies on many small contact points within one contact pad and good electrical connection can be achieved at low contact forces with minimal surface damage. We present test result on both Au pads and SnAg bumps performed at 40μm × 50μm pitch array wide I/O JEDEC pattern. The resistance per contact is ~3 Ohms with 25μm overtravel, and an estimated inductance of 0.1nH per contact. Test results show no detectable damage on the contactor, and small damage on 20μm SnAg bumps.
{"title":"Direct connection and testing of TSV and microbump devices using NanoPierce™ contactor for 3D-IC integration","authors":"O. Yaglioglu, B. Eldridge","doi":"10.1109/VTS.2012.6231086","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231086","url":null,"abstract":"Testing of Through Silicon Via (TSV) and Micro-Bump (MB) devices by physical connection through the TSVs presents unique challenges due to the very high density of the connections, and the potential impact of contact testing on subsequent assembly steps. In addition, the very high signal counts that are the main benefit of TSV connection schemes make conventional wafer probing, particularly for memory devices which demand very high parallelism at production wafer sort, largely impractical. We present a socket solution using FormFactor Nanopierce™ contactor for direct testing of TSV's and micro-bumps arrays which enables creation of known good TSV dies for high yield stacking and known good TSV stacks for shipment to system assemblers to achieve high yield assembly. Combining this socket solution with existing full wafer contact probe solutions enables a complete TSV test flow. In addition, standard TSV interface designs and patterns can enable standard sockets. The FormFactor NanoPierce™ contactor is highly scalable and easy to fabricate at very dense pitches down to 20μm. The contactor relies on many small contact points within one contact pad and good electrical connection can be achieved at low contact forces with minimal surface damage. We present test result on both Au pads and SnAg bumps performed at 40μm × 50μm pitch array wide I/O JEDEC pattern. The resistance per contact is ~3 Ohms with 25μm overtravel, and an estimated inductance of 0.1nH per contact. Test results show no detectable damage on the contactor, and small damage on 20μm SnAg bumps.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123702670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VTS.2012.6231087
Yong-Xiao Chen, Yu-Jen Huang, Jin-Fu Li
Three-dimensional (3D) integration using through-silicon via (TSV) is an emerging technique for integrated circuit (IC) designs. A 3D IC consists of multiple dies vertically connected by TSVs. To ensure the yield of 3D ICs, each die should be tested before it is stacked, i.e., the pre-bond test. Typically, test pads are implemented in the die under test for the pre-bond test due to the limitation of current probing technologies. However, the additional test pads incur additional die area. In this paper, therefore, we propose a test cost optimization technique for the pre-bond test of 3D ICs. This technique attempts to minimize the number required power pads of each die in a wafer and the overall test time of the wafer. Simulation results show that reducing power pads can effectively reduce the number of required test pads and the wafer test time.
{"title":"Test cost optimization technique for the pre-bond test of 3D ICs","authors":"Yong-Xiao Chen, Yu-Jen Huang, Jin-Fu Li","doi":"10.1109/VTS.2012.6231087","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231087","url":null,"abstract":"Three-dimensional (3D) integration using through-silicon via (TSV) is an emerging technique for integrated circuit (IC) designs. A 3D IC consists of multiple dies vertically connected by TSVs. To ensure the yield of 3D ICs, each die should be tested before it is stacked, i.e., the pre-bond test. Typically, test pads are implemented in the die under test for the pre-bond test due to the limitation of current probing technologies. However, the additional test pads incur additional die area. In this paper, therefore, we propose a test cost optimization technique for the pre-bond test of 3D ICs. This technique attempts to minimize the number required power pads of each die in a wafer and the overall test time of the wafer. Simulation results show that reducing power pads can effectively reduce the number of required test pads and the wafer test time.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130858654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VTS.2012.6231106
Lixing Zhao, V. Agrawal
Given the test output from a defective digital circuit, we identify one or more faulty signal nets that may have caused the observed output results. Although we make no assumption about the actual defect, our diagnosis is based upon a dictionary pre-generated by simulating the test vectors for their detection of collapsed single stuck-at and transition faults at each primary output. First, novel three-stage candidate filtering system and candidate ranking system are proposed to reduce and rank candidate faults. A more balanced ranking method compared to previous works and a ranking strategy which combined both overall and per-test performance together are used in these two systems. Then, the ranked candidate list is expanded by uncollapsing faults. A rank for every candidate net is calculated based on the number of top-ranked suspected faults on it. Experiments were conducted by injecting multiple stuck-at or transition delay faults on either single or double nets in certain ISCAS85 circuit. When tests generated by targeting single stuck-at and transition faults were used, our diagnosis algorithm shows good diagnosability and resolution in identifying single and double faulty nets.
{"title":"Net diagnosis using stuck-at and transition fault models","authors":"Lixing Zhao, V. Agrawal","doi":"10.1109/VTS.2012.6231106","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231106","url":null,"abstract":"Given the test output from a defective digital circuit, we identify one or more faulty signal nets that may have caused the observed output results. Although we make no assumption about the actual defect, our diagnosis is based upon a dictionary pre-generated by simulating the test vectors for their detection of collapsed single stuck-at and transition faults at each primary output. First, novel three-stage candidate filtering system and candidate ranking system are proposed to reduce and rank candidate faults. A more balanced ranking method compared to previous works and a ranking strategy which combined both overall and per-test performance together are used in these two systems. Then, the ranked candidate list is expanded by uncollapsing faults. A rank for every candidate net is calculated based on the number of top-ranked suspected faults on it. Experiments were conducted by injecting multiple stuck-at or transition delay faults on either single or double nets in certain ISCAS85 circuit. When tests generated by targeting single stuck-at and transition faults were used, our diagnosis algorithm shows good diagnosability and resolution in identifying single and double faulty nets.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120963481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VTS.2012.6231075
N. Akkouche, S. Mir, E. Simeu, M. Slamani
Ordering of analog/RF tests is important for the identification of redundant tests. Most methods for test ordering are based on a representative set of defective devices. However, at the beginning of production testing, there is little or no data on defective devices. Obtaining this data through defect and fault simulation is unrealistic for most advanced analog/RF devices. In this work, we will present a method for analog/RF test ordering that uses only data from a small set of functional circuits. A statistical model of the device under test is constructed from this data. This model is next used for sampling a large number of virtual circuits which will also include defective ones. These virtual defective circuits are then used for ordering analog/RF tests using feature selection techniques. Experimental results for an IBM RF front-end have demonstrated the validity of this technique for test grading and compaction.
{"title":"Analog/RF test ordering in the early stages of production testing","authors":"N. Akkouche, S. Mir, E. Simeu, M. Slamani","doi":"10.1109/VTS.2012.6231075","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231075","url":null,"abstract":"Ordering of analog/RF tests is important for the identification of redundant tests. Most methods for test ordering are based on a representative set of defective devices. However, at the beginning of production testing, there is little or no data on defective devices. Obtaining this data through defect and fault simulation is unrealistic for most advanced analog/RF devices. In this work, we will present a method for analog/RF test ordering that uses only data from a small set of functional circuits. A statistical model of the device under test is constructed from this data. This model is next used for sampling a large number of virtual circuits which will also include defective ones. These virtual defective circuits are then used for ordering analog/RF tests using feature selection techniques. Experimental results for an IBM RF front-end have demonstrated the validity of this technique for test grading and compaction.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133160088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VTS.2012.6231060
P. Pouyan, E. Amat, A. Rubio
Process variations and device aging have a significant impact on the reliability and performance of nano scale integrated circuits. Proactive reconfiguration is an emerging technique to extend the lifetime of embedded SRAM memories. This work introduces a novel version that modifies and enhances the advantages of this method by considering the process variability impact on the memory components. Our results show between 30% and 45% SRAM lifetime increases over the existing proactive reconfiguration technique and between 1.7X and ~10X improvement over the non-proactive reconfiguration.
{"title":"Process variability-aware proactive reconfiguration technique for mitigating aging effects in nano scale SRAM lifetime","authors":"P. Pouyan, E. Amat, A. Rubio","doi":"10.1109/VTS.2012.6231060","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231060","url":null,"abstract":"Process variations and device aging have a significant impact on the reliability and performance of nano scale integrated circuits. Proactive reconfiguration is an emerging technique to extend the lifetime of embedded SRAM memories. This work introduces a novel version that modifies and enhances the advantages of this method by considering the process variability impact on the memory components. Our results show between 30% and 45% SRAM lifetime increases over the existing proactive reconfiguration technique and between 1.7X and ~10X improvement over the non-proactive reconfiguration.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122150630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VTS.2012.6231081
Dzmitry Maliuk, Nathan Kupp, Y. Makris
A recently proposed Built-In Self-Test (BIST) method for analog/RF circuits requires stimuli generator, measurement acquisition, and decision making circuits to be integrated on-chip along with the Device Under Test (DUT). Practical implementation of this approach hinges on the ability to meet strict area and power constraints of the circuits dedicated to test. In this work, we investigate a cost-efficient implementation of a neural classifier, which is the central component of this BIST method. We present the design of a reconfigurable analog neural network (ANN) experimentation platform and address the key questions concerning its cost-efficiency: a fully analog implementation with strict area and power budgets, a learning ability of the proposed architecture, fast dynamic programming of the weight memory during training, and high precision non-volatile storage of weight coefficients during operation or standby. Using this platform, we implement an ontogenic neural network (ONN) along with the corresponding training algorithms. Finally, we demonstrate the learning ability of the proposed architecture with a real-world case study wherein we train the ANN to predict the results of production specification testing for a large number of RF transceiver chips fabricated by Texas Instruments.
{"title":"Towards a fully stand-alone analog/RF BIST: A cost-effective implementation of a neural classifier","authors":"Dzmitry Maliuk, Nathan Kupp, Y. Makris","doi":"10.1109/VTS.2012.6231081","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231081","url":null,"abstract":"A recently proposed Built-In Self-Test (BIST) method for analog/RF circuits requires stimuli generator, measurement acquisition, and decision making circuits to be integrated on-chip along with the Device Under Test (DUT). Practical implementation of this approach hinges on the ability to meet strict area and power constraints of the circuits dedicated to test. In this work, we investigate a cost-efficient implementation of a neural classifier, which is the central component of this BIST method. We present the design of a reconfigurable analog neural network (ANN) experimentation platform and address the key questions concerning its cost-efficiency: a fully analog implementation with strict area and power budgets, a learning ability of the proposed architecture, fast dynamic programming of the weight memory during training, and high precision non-volatile storage of weight coefficients during operation or standby. Using this platform, we implement an ontogenic neural network (ONN) along with the corresponding training algorithms. Finally, we demonstrate the learning ability of the proposed architecture with a real-world case study wherein we train the ANN to predict the results of production specification testing for a large number of RF transceiver chips fabricated by Texas Instruments.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124179548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VTS.2012.6231102
K. Miyase, Masao Aso, Ryou Ootsuka, X. Wen, H. Furukawa, Yuta Yamato, K. Enokimoto, S. Kajihara
Excessive capture power in at-speed scan testing may cause yield loss due to timing failures. Although reducing the number of clock domains that capture test responses simultaneously is a practical and scalable solution for reducing capture power, no available capture-safety checking metric can assess its effect in an accurate-enough manner, especially when multiple clock domains capture test responses in a short period of time. This paper proposes a novel CLEAR (CLock-Edge-Arrival-Relation-based) capture-safety checking method that, for the first time, takes clock edge arrival times for different clock domains into consideration. The accuracy and usefulness of the proposed method have been clearly demonstrated by simulation-based evaluation with the largest ITC'99 benchmark circuit as well as real-chip-based evaluation with an industrial chip embedded with on-chip delay measurement circuitry.
{"title":"A novel capture-safety checking method for multi-clock designs and accuracy evaluation with delay capture circuits","authors":"K. Miyase, Masao Aso, Ryou Ootsuka, X. Wen, H. Furukawa, Yuta Yamato, K. Enokimoto, S. Kajihara","doi":"10.1109/VTS.2012.6231102","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231102","url":null,"abstract":"Excessive capture power in at-speed scan testing may cause yield loss due to timing failures. Although reducing the number of clock domains that capture test responses simultaneously is a practical and scalable solution for reducing capture power, no available capture-safety checking metric can assess its effect in an accurate-enough manner, especially when multiple clock domains capture test responses in a short period of time. This paper proposes a novel CLEAR (CLock-Edge-Arrival-Relation-based) capture-safety checking method that, for the first time, takes clock edge arrival times for different clock domains into consideration. The accuracy and usefulness of the proposed method have been clearly demonstrated by simulation-based evaluation with the largest ITC'99 benchmark circuit as well as real-chip-based evaluation with an industrial chip embedded with on-chip delay measurement circuitry.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124050854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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