Pub Date : 2012-04-23DOI: 10.1109/VTS.2012.6231074
H. Ayari, F. Azaïs, S. Bernard, M. Comte, M. Renovell, V. Kerzérho, O. Potin, C. Kelma
In this paper, we investigate an alternate test strategy for RF integrated circuits based on DC measurements. A methodology to select the appropriate DC parameters is presented, that allows precise estimation of the DUT performances while minimizing the number of measurements to be carried out. The method is demonstrated both on simulation test data from a Low-Noise Amplifier (LNA) and production test data from a Power Amplifier (PA). Results indicate that good prediction of the RF performances can be achieved using only a reduced number of DC measurements.
{"title":"Smart selection of indirect parameters for DC-based alternate RF IC testing","authors":"H. Ayari, F. Azaïs, S. Bernard, M. Comte, M. Renovell, V. Kerzérho, O. Potin, C. Kelma","doi":"10.1109/VTS.2012.6231074","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231074","url":null,"abstract":"In this paper, we investigate an alternate test strategy for RF integrated circuits based on DC measurements. A methodology to select the appropriate DC parameters is presented, that allows precise estimation of the DUT performances while minimizing the number of measurements to be carried out. The method is demonstrated both on simulation test data from a Low-Noise Amplifier (LNA) and production test data from a Power Amplifier (PA). Results indicate that good prediction of the RF performances can be achieved using only a reduced number of DC measurements.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115216151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VTS.2012.6231103
Yang Zhao, Lisa Grenier, Amitava Majumdar
While IC speed binning is commonplace today, power binning is a relatively new practice and doing that on an automatic test equipment (ATE), without the aid of functional patterns, is even more rare. As with speed binning, power binning depends on measuring power of multiple components in each IC and using the measurements in a model to predict actual power dissipation of the chip. Power dissipated by embedded SRAMs, especially under activity levels found in normal operation, is critical to power binning. This paper describes a method for measuring the normal functional power of embedded SRAMs by re-using memory BIST and JTAG circuitry in an ATE environment, contributing to power binning at wafer probe.
{"title":"Power Characterization of Embedded SRAMs for Power Binning","authors":"Yang Zhao, Lisa Grenier, Amitava Majumdar","doi":"10.1109/VTS.2012.6231103","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231103","url":null,"abstract":"While IC speed binning is commonplace today, power binning is a relatively new practice and doing that on an automatic test equipment (ATE), without the aid of functional patterns, is even more rare. As with speed binning, power binning depends on measuring power of multiple components in each IC and using the measurements in a model to predict actual power dissipation of the chip. Power dissipated by embedded SRAMs, especially under activity levels found in normal operation, is critical to power binning. This paper describes a method for measuring the normal functional power of embedded SRAMs by re-using memory BIST and JTAG circuitry in an ATE environment, contributing to power binning at wafer probe.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122505685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Three-dimensional (3D) integration has recently become a popular technology for integrated circuits (IC). 3D IC with the passive silicon interposer is currently the main trend in the industry, especially for processor-memory integration. Evaluating the economic efficiency of test operations in the interposer-based 3D IC thus is important. We propose a cost model for the Die-to-Wafer (D2W) and Die-to-Die (D2D) stacking, including manufacturing cost and test cost. A tool which is based on the proposed cost model is developed. We use this tool for cost analysis and for finding the most cost effective test flow. The results show that, in some applications, test flows including the iterative known-good stack (KGS) test and the pre-bond interposer test significantly reduce the cost, when the KGS test yield is lower than 98.2% and the pre-bond interposer test yield is lower than 99.38%. A Shmoo plot is depicted to show the lower bound of the yield of the final package level test, given the number of stacked dies and the final yield. For different applications, the proposed model evaluates the critical yield or cost values, which helps the designers to determine the most cost effective test flow and the system architecture.
{"title":"Cost modeling and analysis for interposer-based three-dimensional IC","authors":"Ying-Wen Chou, Po-Yuan Chen, Mincent Lee, Cheng-Wen Wu","doi":"10.1109/VTS.2012.6231088","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231088","url":null,"abstract":"Three-dimensional (3D) integration has recently become a popular technology for integrated circuits (IC). 3D IC with the passive silicon interposer is currently the main trend in the industry, especially for processor-memory integration. Evaluating the economic efficiency of test operations in the interposer-based 3D IC thus is important. We propose a cost model for the Die-to-Wafer (D2W) and Die-to-Die (D2D) stacking, including manufacturing cost and test cost. A tool which is based on the proposed cost model is developed. We use this tool for cost analysis and for finding the most cost effective test flow. The results show that, in some applications, test flows including the iterative known-good stack (KGS) test and the pre-bond interposer test significantly reduce the cost, when the KGS test yield is lower than 98.2% and the pre-bond interposer test yield is lower than 99.38%. A Shmoo plot is depicted to show the lower bound of the yield of the final package level test, given the number of stacked dies and the final yield. For different applications, the proposed model evaluates the critical yield or cost values, which helps the designers to determine the most cost effective test flow and the system architecture.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131766110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VTS.2012.6231070
A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel
Memory design and test represent very important issues. Memories are designed to exploit the technology limits to reach the highest storage density and high-speed access. The main consequence is that memory devices are statistically more likely to be affected by manufacturing defects. The challenge of testing SRAM memories consists in providing realistic fault models and test solutions with minimal application time. Due to the complexity of the memory device, fault modeling is not trivial. Classical memory test solutions cover the so-called `static faults' (such as stuck-at, transition, and coupling faults) but are not sufficient to cover faults that have emerged in latest VDSM technologies and which are referred to as `dynamic faults'. This tutorial aims at introduce and guide to new test approaches developed so far for dealing with dynamic faults in the latest generation of SRAM memories.
{"title":"Advanced test methods for SRAMs","authors":"A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel","doi":"10.1109/VTS.2012.6231070","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231070","url":null,"abstract":"Memory design and test represent very important issues. Memories are designed to exploit the technology limits to reach the highest storage density and high-speed access. The main consequence is that memory devices are statistically more likely to be affected by manufacturing defects. The challenge of testing SRAM memories consists in providing realistic fault models and test solutions with minimal application time. Due to the complexity of the memory device, fault modeling is not trivial. Classical memory test solutions cover the so-called `static faults' (such as stuck-at, transition, and coupling faults) but are not sufficient to cover faults that have emerged in latest VDSM technologies and which are referred to as `dynamic faults'. This tutorial aims at introduce and guide to new test approaches developed so far for dealing with dynamic faults in the latest generation of SRAM memories.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134159892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VTS.2012.6231092
J. Chun, Siew Mooi Lim, Shao Chee Ong, Jae Wook Lee, J. Abraham
Conventional test for high speed serial links requires expensive test equipment to meet the standard <; 10-12 bit error rate (BER) requirement. Although timing margining loop-back tests are cost effective, phase interpolator (PI) circuitry needs to be tested for test completeness. Our method provides an efficient linearity test capability for the PI circuitry. In the proposed scheme, a sliding window search algorithm is used to extract differential nonlinearity (DNL) and integral nonlinearity (INL), based on a jitter distribution obtained from undersampling. Various simulations were performed to evaluate the accuracy and robustness of the method. They indicate that the proposed algorithm provides an accurate estimation of linearities of the PI. We also implemented our algorithm in a conventional low cost high volume manufacturing (HVM) tester platform to show feasibility and validity of the proposed technique.
{"title":"Test of phase interpolators in high speed I/Os using a sliding window search","authors":"J. Chun, Siew Mooi Lim, Shao Chee Ong, Jae Wook Lee, J. Abraham","doi":"10.1109/VTS.2012.6231092","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231092","url":null,"abstract":"Conventional test for high speed serial links requires expensive test equipment to meet the standard <; 10-12 bit error rate (BER) requirement. Although timing margining loop-back tests are cost effective, phase interpolator (PI) circuitry needs to be tested for test completeness. Our method provides an efficient linearity test capability for the PI circuitry. In the proposed scheme, a sliding window search algorithm is used to extract differential nonlinearity (DNL) and integral nonlinearity (INL), based on a jitter distribution obtained from undersampling. Various simulations were performed to evaluate the accuracy and robustness of the method. They indicate that the proposed algorithm provides an accurate estimation of linearities of the PI. We also implemented our algorithm in a conventional low cost high volume manufacturing (HVM) tester platform to show feasibility and validity of the proposed technique.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124671394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VTS.2012.6231099
I. Pomeranz
The conventional detection conditions for transition faults require a transition at the fault site for activating a fault. The hazard-based detection conditions allow a transition fault to be activated by a pulse. Earlier, the hazard-based detection conditions were used for obtaining more accurate estimates of transition fault coverage and for more accurate defect diagnosis. This paper considers their use for test compaction. The procedure described in this paper replaces the conventional detection conditions with the hazard-based detection conditions for some faults. The use of the hazard-based detection conditions allows each test to detect more faults, thus allowing the number of tests to be reduced.
{"title":"Static test compaction for transition faults under the hazard-based detection conditions","authors":"I. Pomeranz","doi":"10.1109/VTS.2012.6231099","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231099","url":null,"abstract":"The conventional detection conditions for transition faults require a transition at the fault site for activating a fault. The hazard-based detection conditions allow a transition fault to be activated by a pulse. Earlier, the hazard-based detection conditions were used for obtaining more accurate estimates of transition fault coverage and for more accurate defect diagnosis. This paper considers their use for test compaction. The procedure described in this paper replaces the conventional detection conditions with the hazard-based detection conditions for some faults. The use of the hazard-based detection conditions allows each test to detect more faults, thus allowing the number of tests to be reduced.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130091762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VTS.2012.6231084
S. Chakravarty, Narendra Devta-Prasanna, A. Gunda, Junxia Ma, Fan Yang, H. Guo, R. Lai, D. Li
Researchers, based primarily on theoretical analysis of different coverage metric, have proposed the need to cover small delay defect (SDD). There is very little silicon data justifying the need to add SDD tests to the manufacturing flow. This paper attempts to fill this gap. A high volume manufacturing experiment to ascertain the added screening capability of defective parts and infant mortality of FAST_TDF tests are described. Quantitative silicon data are presented.
{"title":"Silicon evaluation of faster than at-speed transition delay tests","authors":"S. Chakravarty, Narendra Devta-Prasanna, A. Gunda, Junxia Ma, Fan Yang, H. Guo, R. Lai, D. Li","doi":"10.1109/VTS.2012.6231084","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231084","url":null,"abstract":"Researchers, based primarily on theoretical analysis of different coverage metric, have proposed the need to cover small delay defect (SDD). There is very little silicon data justifying the need to add SDD tests to the manufacturing flow. This paper attempts to fill this gap. A high volume manufacturing experiment to ascertain the added screening capability of defective parts and infant mortality of FAST_TDF tests are described. Quantitative silicon data are presented.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"58 12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126199652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VTS.2012.6231096
Geewhun Seok, Hong Kim, B. Mohammad
Demands for low defects per million (DPM) rates are increasing as process technology scaling is able to increase transistor density and add more functionality to the integrated circuits. For stuck at fault and delay testing, Scan-based testing in conjunction with ATPG is the preferred approach to reduces DPM compared to functional testing. However embedded memories have been a challenge to ATPG gate level simulation due to limitation of gate level generation method and the additional logic needed to prevent unknowns (X's) to be propagated from memory during ATPG testing, this X-propagation becomes more of an issue when the design has a test compressor. This paper examines the challenges of ATPG memory write through method on the design with chip test compression logic and proposes new design strategy and ATPG pattern generation method. The proposed design will make the memory look like a one dimensional set of registers and ATPG pattern generation method will support write through mode without Xs propagation.
{"title":"Write-through method for embedded memory with compression Scan-based testing","authors":"Geewhun Seok, Hong Kim, B. Mohammad","doi":"10.1109/VTS.2012.6231096","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231096","url":null,"abstract":"Demands for low defects per million (DPM) rates are increasing as process technology scaling is able to increase transistor density and add more functionality to the integrated circuits. For stuck at fault and delay testing, Scan-based testing in conjunction with ATPG is the preferred approach to reduces DPM compared to functional testing. However embedded memories have been a challenge to ATPG gate level simulation due to limitation of gate level generation method and the additional logic needed to prevent unknowns (X's) to be propagated from memory during ATPG testing, this X-propagation becomes more of an issue when the design has a test compressor. This paper examines the challenges of ATPG memory write through method on the design with chip test compression logic and proposes new design strategy and ATPG pattern generation method. The proposed design will make the memory look like a one dimensional set of registers and ATPG pattern generation method will support write through mode without Xs propagation.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115316958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VTS.2012.6231082
S. Askari, M. Nourani, Mini Rawat
Negative Bias Temperature Instability (NBTI) degrades the life-time of both the analog and digital circuits significantly and has become a major concern in nanoscale regime. In analog circuits, the DC biasing voltage is always present irrespective of the input signal. Therefore, coupled with high operating temperature (due to digital switching and high packaging density of SoC) and constant DC bias there would be continuous NBTI stress in analog circuits with minor or almost no recovery. Moreover, mismatch and input referred offset voltage caused by NBTI in differential pairs, current sources and cascode stages can cause instantaneous failure or catastrophic failure after certain time period. The problem of NBTI is usually addressed by leaving large design margins or employing adaptive body bias/adaptive voltage scaling based calibration algorithms using on-chip sensors or monitors. We present an ultra low power and small area on-chip NBTI sensor which can be used for accurately sensing the NBTI degradation in analog circuits. We have shown that the temporal degradation in threshold voltage of pMOS transistor in analog circuits has high correlation to the variation of reference voltage of our NBTI sensor which can be exploited for accurate calibration of analog circuits. Measurement results are also provided for the proposed sensor fabricated in commercially available 65nm process.
{"title":"An on-chip NBTI monitor for estimating analog circuit degradation","authors":"S. Askari, M. Nourani, Mini Rawat","doi":"10.1109/VTS.2012.6231082","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231082","url":null,"abstract":"Negative Bias Temperature Instability (NBTI) degrades the life-time of both the analog and digital circuits significantly and has become a major concern in nanoscale regime. In analog circuits, the DC biasing voltage is always present irrespective of the input signal. Therefore, coupled with high operating temperature (due to digital switching and high packaging density of SoC) and constant DC bias there would be continuous NBTI stress in analog circuits with minor or almost no recovery. Moreover, mismatch and input referred offset voltage caused by NBTI in differential pairs, current sources and cascode stages can cause instantaneous failure or catastrophic failure after certain time period. The problem of NBTI is usually addressed by leaving large design margins or employing adaptive body bias/adaptive voltage scaling based calibration algorithms using on-chip sensors or monitors. We present an ultra low power and small area on-chip NBTI sensor which can be used for accurately sensing the NBTI degradation in analog circuits. We have shown that the temporal degradation in threshold voltage of pMOS transistor in analog circuits has high correlation to the variation of reference voltage of our NBTI sensor which can be exploited for accurate calibration of analog circuits. Measurement results are also provided for the proposed sensor fabricated in commercially available 65nm process.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128659960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VTS.2012.6231071
J. Rajski, J. Tyszer, Grzegorz Mrugalski, B. Nadeau-Dostie
This paper presents a new pseudorandom test pattern generator with preselected toggling (PRESTO) activity. It is comprised of a linear finite state machine (a linear feedback shift register or a ring generator) driving an appropriate phase shifter and armed with a number of features that allows this device to produce binary sequences with low toggling (switching) rates while preserving test coverage achievable by the best-to-date conventional BIST-based PRPGs with negligible impact on test application time.
{"title":"Test generator with preselected toggling for low power built-in self-test","authors":"J. Rajski, J. Tyszer, Grzegorz Mrugalski, B. Nadeau-Dostie","doi":"10.1109/VTS.2012.6231071","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231071","url":null,"abstract":"This paper presents a new pseudorandom test pattern generator with preselected toggling (PRESTO) activity. It is comprised of a linear finite state machine (a linear feedback shift register or a ring generator) driving an appropriate phase shifter and armed with a number of features that allows this device to produce binary sequences with low toggling (switching) rates while preserving test coverage achievable by the best-to-date conventional BIST-based PRPGs with negligible impact on test application time.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"180 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125819513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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