Pub Date : 2012-04-23DOI: 10.1109/VTS.2012.6231078
A. Ghofrani, Ritesh Parikh, S. Shamshiri, A. DeOrio, K. Cheng, V. Bertacco
We propose a comprehensive yet low-cost solution for online detection and diagnosis of permanent faults in on-chip networks. Using error syndrome collection and packet/flit-counting techniques, high-resolution defect diagnosis is feasible in both datapath and control logic of the on-chip network without injecting any test traffic or incurring significant performance overhead.
{"title":"Comprehensive online defect diagnosis in on-chip networks","authors":"A. Ghofrani, Ritesh Parikh, S. Shamshiri, A. DeOrio, K. Cheng, V. Bertacco","doi":"10.1109/VTS.2012.6231078","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231078","url":null,"abstract":"We propose a comprehensive yet low-cost solution for online detection and diagnosis of permanent faults in on-chip networks. Using error syndrome collection and packet/flit-counting techniques, high-resolution defect diagnosis is feasible in both datapath and control logic of the on-chip network without injecting any test traffic or incurring significant performance overhead.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"238 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116110279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VTS.2012.6231058
P. Papavramidou, M. Nicolaidis
In modern SoCs embedded memories should be repaired after fabrication to achieve acceptable yield. They should also be protected by ECC against field failures to achieve acceptable reliability. To avoid paying the area and power penalties of both approaches, we can use ECC to fix both fabrication and field failures. However, we show that efficient implementation of this approach may require special diagnosis hardware or new memory test algorithm that exhibit the so-called “single-read double-fault detection” property defined in this paper. We also propose test algorithms satisfying this property.
{"title":"Test algorithms for ECC-based memory repair in nanotechnologies","authors":"P. Papavramidou, M. Nicolaidis","doi":"10.1109/VTS.2012.6231058","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231058","url":null,"abstract":"In modern SoCs embedded memories should be repaired after fabrication to achieve acceptable yield. They should also be protected by ECC against field failures to achieve acceptable reliability. To avoid paying the area and power penalties of both approaches, we can use ECC to fix both fabrication and field failures. However, we show that efficient implementation of this approach may require special diagnosis hardware or new memory test algorithm that exhibit the so-called “single-read double-fault detection” property defined in this paper. We also propose test algorithms satisfying this property.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121976411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VTS.2012.6231104
P. Song, F. Stellari
This paper details tester-based optical and electrical diagnostic system and techniques that aim at diagnosing various types of problems that exist in today's VLSI chips, especially during initial bring-up stage. The versatility of the electrical test creates flexible test controls while optical diagnostic tools, such as emission-based systems, provide a deep understanding of what is going on inside the chip. Tightly integrating both methods produces a powerful diagnostic system and it also opens a door for creating a series of new diagnostic techniques for resolving new families of problems as illustrated in this paper with several examples.
{"title":"Tester-based optical and electrical diagnostic system and techniques","authors":"P. Song, F. Stellari","doi":"10.1109/VTS.2012.6231104","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231104","url":null,"abstract":"This paper details tester-based optical and electrical diagnostic system and techniques that aim at diagnosing various types of problems that exist in today's VLSI chips, especially during initial bring-up stage. The versatility of the electrical test creates flexible test controls while optical diagnostic tools, such as emission-based systems, provide a deep understanding of what is going on inside the chip. Tightly integrating both methods produces a powerful diagnostic system and it also opens a door for creating a series of new diagnostic techniques for resolving new families of problems as illustrated in this paper with several examples.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127813518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VTS.2012.6231105
S. Prabhu, M. Hsiao, L. Lingappan, V. Gangaram
A diagnostic test pattern generator using a Satisfiability Modulo Theory (SMT) solver is proposed. Rather than targeting a single fault pair at a time, the proposed SMT approach can distinguish multiple fault pairs in a single instance. Several heuristics are proposed to constrain the SMT formula to further reduce the search space, including fault selection, excitation constraint, reduced primary output vector, and cone-of-influence reduction. Experimental results for the ISCAS85 and full-scan versions of ISCAS89 benchmark circuits show that fewer diagnostic vectors are generated compared with conventional diagnostic test generation methods. Up to 73% reduction in the number of vectors generated can be achieved in large circuits.
{"title":"A SMT-based diagnostic test generation method for combinational circuits","authors":"S. Prabhu, M. Hsiao, L. Lingappan, V. Gangaram","doi":"10.1109/VTS.2012.6231105","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231105","url":null,"abstract":"A diagnostic test pattern generator using a Satisfiability Modulo Theory (SMT) solver is proposed. Rather than targeting a single fault pair at a time, the proposed SMT approach can distinguish multiple fault pairs in a single instance. Several heuristics are proposed to constrain the SMT formula to further reduce the search space, including fault selection, excitation constraint, reduced primary output vector, and cone-of-influence reduction. Experimental results for the ISCAS85 and full-scan versions of ISCAS89 benchmark circuits show that fewer diagnostic vectors are generated compared with conventional diagnostic test generation methods. Up to 73% reduction in the number of vectors generated can be achieved in large circuits.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126508671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VTS.2012.6231067
V. Prasanth, Virendra Singh, R. Parekhji
Ensuring reliable operation over an extended period of time is one of the biggest challenges facing present day electronic systems. The increased vulnerability of the components to atmospheric particle strikes poses a big threat in attaining the reliability required for various mission critical applications. Various soft error mitigation methodologies exist to address this reliability challenge. A general solution to this problem is to arrive at a soft error mitigation methodology with an acceptable implementation overhead and error tolerance level. This implementation overhead can then be reduced by taking advantage of various derating effects like logical derating, electrical derating and timing window derating, and/or making use of application redundancy, e.g. redundancy in firmware/software executing on the so designed robust hardware. In this paper, we analyze the impact of various derating factors and show how they can be profitably employed to reduce the hardware overhead to implement a given level of soft error robustness. This analysis is performed on a set of benchmark circuits using the delayed capture methodology. Experimental results show up to 23% reduction in the hardware overhead when considering individual and combined derating factors.
{"title":"Derating based hardware optimizations in soft error tolerant designs","authors":"V. Prasanth, Virendra Singh, R. Parekhji","doi":"10.1109/VTS.2012.6231067","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231067","url":null,"abstract":"Ensuring reliable operation over an extended period of time is one of the biggest challenges facing present day electronic systems. The increased vulnerability of the components to atmospheric particle strikes poses a big threat in attaining the reliability required for various mission critical applications. Various soft error mitigation methodologies exist to address this reliability challenge. A general solution to this problem is to arrive at a soft error mitigation methodology with an acceptable implementation overhead and error tolerance level. This implementation overhead can then be reduced by taking advantage of various derating effects like logical derating, electrical derating and timing window derating, and/or making use of application redundancy, e.g. redundancy in firmware/software executing on the so designed robust hardware. In this paper, we analyze the impact of various derating factors and show how they can be profitably employed to reduce the hardware overhead to implement a given level of soft error robustness. This analysis is performed on a set of benchmark circuits using the delayed capture methodology. Experimental results show up to 23% reduction in the hardware overhead when considering individual and combined derating factors.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114097944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VTS.2012.6231064
W. Yueh, S. Chatterjee, A. Trivedi, S. Mukhopadhyay
This paper analyzes the supply crosstalk between logic cores and SRAMs on separate tiers in a 3D die-stack using a distributed RLC based 3D power grid model. The analysis shows that due to the supply cross-talk power variation in cores modulates the performances and parametric failures in SRAM.
{"title":"On the parametric failures of SRAM in a 3D-die stack considering tier-to-tier supply cross-talk","authors":"W. Yueh, S. Chatterjee, A. Trivedi, S. Mukhopadhyay","doi":"10.1109/VTS.2012.6231064","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231064","url":null,"abstract":"This paper analyzes the supply crosstalk between logic cores and SRAMs on separate tiers in a 3D die-stack using a distributed RLC based 3D power grid model. The analysis shows that due to the supply cross-talk power variation in cores modulates the performances and parametric failures in SRAM.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117162127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VTS.2012.6231080
A. Nassery, Srinath Byregowda, S. Ozev, M. Verhelst, M. Slamani
Built-in-Self-Test (BiST) for transmitters is a desirable choice since it eliminates the reliance on expensive instrumentation to do RF signal analysis. Existing on-chip resources, such as power or envelope detectors or small additional circuitry can be used for BiST purposes. However, due to limited bandwidth, measurement of complex specifications, such as IQ imbalance is challenging. Since these parameters are most amenable for digital compensation, their characterization and monitoring are desirable. In this paper, we propose a BiST technique for transmitter IQ imbalance using a self-mixing envelope detector. We first derive an analytical expression for the output signal. Using this expression, we devise test signals to isolate the effects of gain and phase imbalance, DC offsets, and time skews from other parameters of the system. Once isolated, these parameters are calculated easily with a few mathematical operations. Simulations and hardware measurements show that the technique can provide accurate characterization of IQ imbalances.
{"title":"Built-in-Self Test of transmitter I/Q mismatch using self-mixing envelope detector","authors":"A. Nassery, Srinath Byregowda, S. Ozev, M. Verhelst, M. Slamani","doi":"10.1109/VTS.2012.6231080","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231080","url":null,"abstract":"Built-in-Self-Test (BiST) for transmitters is a desirable choice since it eliminates the reliance on expensive instrumentation to do RF signal analysis. Existing on-chip resources, such as power or envelope detectors or small additional circuitry can be used for BiST purposes. However, due to limited bandwidth, measurement of complex specifications, such as IQ imbalance is challenging. Since these parameters are most amenable for digital compensation, their characterization and monitoring are desirable. In this paper, we propose a BiST technique for transmitter IQ imbalance using a self-mixing envelope detector. We first derive an analytical expression for the output signal. Using this expression, we devise test signals to isolate the effects of gain and phase imbalance, DC offsets, and time skews from other parameters of the system. Once isolated, these parameters are calculated easily with a few mathematical operations. Simulations and hardware measurements show that the technique can provide accurate characterization of IQ imbalances.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"197 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122503217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VTS.2012.6231072
H. Kim, J. Abraham
This paper presents a Built-In Self-Test (BIST) scheme to measure high speed double data rate (DDR) memory output timing using low cost testers. This technique uses an on-chip pattern generator to generate a time delay between data and data-strobe or clock. The time delay is controlled precisely using a phase interpolator based cycle-by-cycle control method. A novel method for testing the resolution of phase interpolator, which does not need any extra hardware, is also presented. Using the test resolution, a timing pass/fail flag is set and the timing margin is quantified as a multiple of the test clock cycle. Since these test results have high observability, output per-pin timing performance can be diagnosed easily, which is especially good for testing parallel memory interfaces. Moreover, these features make our scheme compatible with low-cost testers and decreases the time-to-market for the chip. The BIST circuit has been implemented using the 0.18-μm CMOS process, and chip measurement results are presented. We obtained a test resolution of 10 ps for testing output timing. Using the fabricated test chip, this paper shows the effects of switching noise, per-pin skews and slew-rate change on output timing variations.
{"title":"A Built-In Self-Test scheme for DDR memory output timing test and measurement","authors":"H. Kim, J. Abraham","doi":"10.1109/VTS.2012.6231072","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231072","url":null,"abstract":"This paper presents a Built-In Self-Test (BIST) scheme to measure high speed double data rate (DDR) memory output timing using low cost testers. This technique uses an on-chip pattern generator to generate a time delay between data and data-strobe or clock. The time delay is controlled precisely using a phase interpolator based cycle-by-cycle control method. A novel method for testing the resolution of phase interpolator, which does not need any extra hardware, is also presented. Using the test resolution, a timing pass/fail flag is set and the timing margin is quantified as a multiple of the test clock cycle. Since these test results have high observability, output per-pin timing performance can be diagnosed easily, which is especially good for testing parallel memory interfaces. Moreover, these features make our scheme compatible with low-cost testers and decreases the time-to-market for the chip. The BIST circuit has been implemented using the 0.18-μm CMOS process, and chip measurement results are presented. We obtained a test resolution of 10 ps for testing output timing. Using the fabricated test chip, this paper shows the effects of switching noise, per-pin skews and slew-rate change on output timing variations.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128119816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-01DOI: 10.1109/VTS.2012.6231085
Michihiro Shintani, Takashi Sato
Post-fabrication performance compensation and adaptive delay testing are effective means to improve yield and reliability of LSIs. In these methods, process parameter estimation plays a key role. In this paper, we propose a novel technique for accurate on-chip process parameter estimation. The proposed technique is based on Bayes' theorem, in which on-chip parameters, such as threshold voltages, are estimated by current signatures obtained within a regular IDDQ testing. No additional circuit and additional measurements are required for the purpose of estimation. Numerical experiments demonstrate that the proposed technique can achieve less than 10 mV accuracy in estimating threshold voltages.
{"title":"A Bayesian-based process parameter estimation using IDDQ current signature","authors":"Michihiro Shintani, Takashi Sato","doi":"10.1109/VTS.2012.6231085","DOIUrl":"https://doi.org/10.1109/VTS.2012.6231085","url":null,"abstract":"Post-fabrication performance compensation and adaptive delay testing are effective means to improve yield and reliability of LSIs. In these methods, process parameter estimation plays a key role. In this paper, we propose a novel technique for accurate on-chip process parameter estimation. The proposed technique is based on Bayes' theorem, in which on-chip parameters, such as threshold voltages, are estimated by current signatures obtained within a regular IDDQ testing. No additional circuit and additional measurements are required for the purpose of estimation. Numerical experiments demonstrate that the proposed technique can achieve less than 10 mV accuracy in estimating threshold voltages.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"60 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134128439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This tutorial is most suitable for DFT and Test Engineers, Validation and Verification engineers, Researchers and students in DFT, testing and validation, hardware security.
本教程最适合DFT和测试工程师，验证和验证工程师，DFT研究人员和学生，测试和验证，硬件安全。
{"title":"Tutorial 1","authors":"R. Karri, Peilin Song, O. Sinanoglu","doi":"10.1109/ats.2006.260981","DOIUrl":"https://doi.org/10.1109/ats.2006.260981","url":null,"abstract":"This tutorial is most suitable for DFT and Test Engineers, Validation and Verification engineers, Researchers and students in DFT, testing and validation, hardware security.","PeriodicalId":169611,"journal":{"name":"2012 IEEE 30th VLSI Test Symposium (VTS)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115777639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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