Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984895
Xiaoxuan Li, Xintong Zhu, Yi Liu, Xiaodong Li, R. Chockalingam, R. R. Nistala, Zhi Qiang Mo
Thick polyimide layer has been used as buffer layer to absorb stress imposed by molding compounds for many years. This paper studied the adhesion strength of the thick polyimide layer under different process conditions. The stress was induced by indentation, and delamination was confirmed by FIB and SEM imaging. The calculated adhesion energy for polyimide film was highest, around 30 J/m2, for the wafer processed with an extra pad protection layer Nblok (Nitrogen-doped barrier on top of copper, SiCN) plasma clean before the spin coating of polyimide film.
{"title":"Application of Nano-indentation method to characterize adhesion strength of polyimide film","authors":"Xiaoxuan Li, Xintong Zhu, Yi Liu, Xiaodong Li, R. Chockalingam, R. R. Nistala, Zhi Qiang Mo","doi":"10.1109/IPFA47161.2019.8984895","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984895","url":null,"abstract":"Thick polyimide layer has been used as buffer layer to absorb stress imposed by molding compounds for many years. This paper studied the adhesion strength of the thick polyimide layer under different process conditions. The stress was induced by indentation, and delamination was confirmed by FIB and SEM imaging. The calculated adhesion energy for polyimide film was highest, around 30 J/m2, for the wafer processed with an extra pad protection layer Nblok (Nitrogen-doped barrier on top of copper, SiCN) plasma clean before the spin coating of polyimide film.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130433903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984810
H. Tan, Xintong Zhu, P. Ang, Yuzhe Zhao, K. Menon, Yanlin Pan, C. Chen, P. K. Tan
Low propagation loss waveguides are always preferred when making Si-photonics waveguide devices. However, light scattering due to sidewall roughness of waveguide contributes to the majority of signal losses. To reduce the loss, a reliable approach to measure the sidewall roughness is critical to fine-tune the fabrication process. In this paper, we report a direct sidewall roughness measurement method by using Atomic Force Microscopy (AFM) incorporated with a special scanning mode (Peakforce Tapping mode) and a point-terminated probe. This method has been successfully applied to measure the sidewall roughness of Si-Photonics waveguides for production process monitoring. The present method can also be applied to characterize the sidewall roughness of other nanostructures with similar requirements or situations.
{"title":"An Improved Analysis Method on Si-Photonics Waveguide Sidewall Roughness","authors":"H. Tan, Xintong Zhu, P. Ang, Yuzhe Zhao, K. Menon, Yanlin Pan, C. Chen, P. K. Tan","doi":"10.1109/IPFA47161.2019.8984810","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984810","url":null,"abstract":"Low propagation loss waveguides are always preferred when making Si-photonics waveguide devices. However, light scattering due to sidewall roughness of waveguide contributes to the majority of signal losses. To reduce the loss, a reliable approach to measure the sidewall roughness is critical to fine-tune the fabrication process. In this paper, we report a direct sidewall roughness measurement method by using Atomic Force Microscopy (AFM) incorporated with a special scanning mode (Peakforce Tapping mode) and a point-terminated probe. This method has been successfully applied to measure the sidewall roughness of Si-Photonics waveguides for production process monitoring. The present method can also be applied to characterize the sidewall roughness of other nanostructures with similar requirements or situations.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133486949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984919
H. Tan, J. Leo, S. M. Parab, K. Menon, Yuzhe Zhao, Yanlin Pan, C. Chen, P. K. Tan
Sample preparation plays a critical role in the failure analysis process of modern IC chips. The common problem in sample preparation is over-polishing. To reduce this problem, an AI-assisted monitoring system can be deployed, which can evaluate the progress of sample polishing process and suggest the steps following up. However, to build such an AI system, a tremendous number of images with proper classification are needed. To prepare these images, a reliable endpoint detection method for image analysis is necessary. In this paper, two endpoint detection methods are studied, and grayscale line profile analysis is discussed in detail. The current results are very promising for further development.
{"title":"Endpoint Detection Methods in Implementing AI-assisted Polishing Process","authors":"H. Tan, J. Leo, S. M. Parab, K. Menon, Yuzhe Zhao, Yanlin Pan, C. Chen, P. K. Tan","doi":"10.1109/IPFA47161.2019.8984919","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984919","url":null,"abstract":"Sample preparation plays a critical role in the failure analysis process of modern IC chips. The common problem in sample preparation is over-polishing. To reduce this problem, an AI-assisted monitoring system can be deployed, which can evaluate the progress of sample polishing process and suggest the steps following up. However, to build such an AI system, a tremendous number of images with proper classification are needed. To prepare these images, a reliable endpoint detection method for image analysis is necessary. In this paper, two endpoint detection methods are studied, and grayscale line profile analysis is discussed in detail. The current results are very promising for further development.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131686252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984885
Chi Zhang, Sheng Li, Siyang Liu, Jiaxing Wei, Wangran Wu, Weifeng Sun
The shifts of electrical parameters for p-GaN high electron mobility transistor (HEMT) under high off-state bias stress with negative gate voltage are investigated in this paper. Comparing to the conventional off-state bias stress with zero gate voltage, a more significant positive shift of threshold voltage and a more evident decrease of gate leakage current were observed under negative gate bias stress condition. The dominant degradation mechanism is suggested that electron traps induced by high electric field at gate-source access region capture more electrons in the barrier layer with the increasing negative gate bias. This work is of significance for the researches on the long-term reliability of the practical system using p-GaN HEMT device.
{"title":"Electrical Degradations of p-GaN HEMT under High Off-state Bias Stress with Negative Gate Voltage","authors":"Chi Zhang, Sheng Li, Siyang Liu, Jiaxing Wei, Wangran Wu, Weifeng Sun","doi":"10.1109/IPFA47161.2019.8984885","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984885","url":null,"abstract":"The shifts of electrical parameters for p-GaN high electron mobility transistor (HEMT) under high off-state bias stress with negative gate voltage are investigated in this paper. Comparing to the conventional off-state bias stress with zero gate voltage, a more significant positive shift of threshold voltage and a more evident decrease of gate leakage current were observed under negative gate bias stress condition. The dominant degradation mechanism is suggested that electron traps induced by high electric field at gate-source access region capture more electrons in the barrier layer with the increasing negative gate bias. This work is of significance for the researches on the long-term reliability of the practical system using p-GaN HEMT device.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115450801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
LDMOS is widely used as an ESD protection device. In high voltage BCD technology. However, due to the use of low concentration medium voltage well in HV process, the LDMOS is easily damaged by the Kirk effect under ESD stress, and the robustness is very low. A novel LDMOS is proposed in this work by using a high concentration well to surround the drain intraditional LDMOS, which, achieves a high ESD robustness with a current level of 0.76A,and the Ron is reduced from the original 25Ω to 6.25Ω. In other hand ,in order to save the area, the conventional LDMOS-SCR has been improved by the drain terminal segment, which make the improved LDMOS-SCR maintain a high robustness while the device area is smaller than that of the conventional LDMOS-SCR, thereby improving the area efficiency.
{"title":"Improved LDMOS for ESD Protection of High Voltage BCD Process","authors":"Shen Hong-yu, Dong Shu-rong, XU Ze-kun, HU Tao, Guo-Chih Wei, Huang Wei","doi":"10.1109/IPFA47161.2019.8984830","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984830","url":null,"abstract":"LDMOS is widely used as an ESD protection device. In high voltage BCD technology. However, due to the use of low concentration medium voltage well in HV process, the LDMOS is easily damaged by the Kirk effect under ESD stress, and the robustness is very low. A novel LDMOS is proposed in this work by using a high concentration well to surround the drain intraditional LDMOS, which, achieves a high ESD robustness with a current level of 0.76A,and the Ron is reduced from the original 25Ω to 6.25Ω. In other hand ,in order to save the area, the conventional LDMOS-SCR has been improved by the drain terminal segment, which make the improved LDMOS-SCR maintain a high robustness while the device area is smaller than that of the conventional LDMOS-SCR, thereby improving the area efficiency.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124231574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984817
Hao Gan, Lin Shi, Xiuqun Zhang, Hongsheng Dai
This paper introduces a typical corrosion phenomenon of the Integrated Circuits. A three-terminal adjustable shunt regulator outputted abnormal voltage on a PCBA because its Vref pin was open. Bonding pad corrosion was confirmed by SEM&EDX analysis. The pad was electrical open to the surrounding schematic. After a whole investigation, several lots of wafers were confirmed to be contaminated by silicone oil which was introduced during the demolding process. Delamination occurred between the molding compound and die. Plating solution which contained chlorine and sulphur percolated into package during Tin Plating.Supplier of the regulator was recommended to improve the demolding process. Besides, routine reliability monitoring(such as C-SAM, HAST) can be executed in quality control process to eliminate this failure mode in customer’s application.
{"title":"A Study of Bonding Pad Corrosion Caused by Contamination","authors":"Hao Gan, Lin Shi, Xiuqun Zhang, Hongsheng Dai","doi":"10.1109/IPFA47161.2019.8984817","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984817","url":null,"abstract":"This paper introduces a typical corrosion phenomenon of the Integrated Circuits. A three-terminal adjustable shunt regulator outputted abnormal voltage on a PCBA because its Vref pin was open. Bonding pad corrosion was confirmed by SEM&EDX analysis. The pad was electrical open to the surrounding schematic. After a whole investigation, several lots of wafers were confirmed to be contaminated by silicone oil which was introduced during the demolding process. Delamination occurred between the molding compound and die. Plating solution which contained chlorine and sulphur percolated into package during Tin Plating.Supplier of the regulator was recommended to improve the demolding process. Besides, routine reliability monitoring(such as C-SAM, HAST) can be executed in quality control process to eliminate this failure mode in customer’s application.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117167946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984887
Hui Xiao, D. Luo, Weiming Li
Board-level thermal-mechanical reliability is one major concern in CBGAs. A typical early fault case of some aviation equipment was studied in this paper. The failure phenomenon was manifested as malfunction of the main board in the flight control computer. The results of fault location showed that there was interconnection failure in the CBGA module in the main board. A serial of experimental technologies were used for the failure analysis, such as 3D X-ray inspection, microsectioning, optical microscope, scanning electron microscope (SEM), etc. The results showed that some Pb37Sn63 solder joints’ through cracking in the CBGA assembly was the immediate cause of the equipment’s malfunction. The main reason for the cracking was thermal-mechanical fatigue with microstructure coarsening degradation, resulting in early failure of the main board. It is suggested to carry out components’ board-level application verification in aviation equipment and other high reliability field.
{"title":"Failure Analysis of Solder Joint Cracking in a CBGA Assembly Applied for Aviation Equipment","authors":"Hui Xiao, D. Luo, Weiming Li","doi":"10.1109/IPFA47161.2019.8984887","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984887","url":null,"abstract":"Board-level thermal-mechanical reliability is one major concern in CBGAs. A typical early fault case of some aviation equipment was studied in this paper. The failure phenomenon was manifested as malfunction of the main board in the flight control computer. The results of fault location showed that there was interconnection failure in the CBGA module in the main board. A serial of experimental technologies were used for the failure analysis, such as 3D X-ray inspection, microsectioning, optical microscope, scanning electron microscope (SEM), etc. The results showed that some Pb37Sn63 solder joints’ through cracking in the CBGA assembly was the immediate cause of the equipment’s malfunction. The main reason for the cracking was thermal-mechanical fatigue with microstructure coarsening degradation, resulting in early failure of the main board. It is suggested to carry out components’ board-level application verification in aviation equipment and other high reliability field.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129463460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984863
T. Han, Kuo Shuen Chao, Huang Kuan Chieh
TAF is a necessary value for calculating the operation Lifetime of IC product. The activation energy (Ea) is the parameter value required to calculate the TAF. Each company has different ways of obtaining activation energy (Ea). Some used function test pass/fail and also current change. Our method is based on the characteristics of SRAM products and the memory unit data storage capacity was used. The activation energy (Ea) value was calculated by analyzing the decay of the lowest operating voltage of the data after two kinds of accelerations at high temperature and high bias. After the experiment, we obtained the activation energy (Ea) value of 0.81eV. The relevant research are all in this paper.
{"title":"Calculating Activation Energy (Ea) of SRAM Product Using The Vmin Variation Method","authors":"T. Han, Kuo Shuen Chao, Huang Kuan Chieh","doi":"10.1109/IPFA47161.2019.8984863","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984863","url":null,"abstract":"TAF is a necessary value for calculating the operation Lifetime of IC product. The activation energy (Ea) is the parameter value required to calculate the TAF. Each company has different ways of obtaining activation energy (Ea). Some used function test pass/fail and also current change. Our method is based on the characteristics of SRAM products and the memory unit data storage capacity was used. The activation energy (Ea) value was calculated by analyzing the decay of the lowest operating voltage of the data after two kinds of accelerations at high temperature and high bias. After the experiment, we obtained the activation energy (Ea) value of 0.81eV. The relevant research are all in this paper.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129691144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984793
Jie Zheng, Ying Yang, Jianghua Shen, Lili Ma, Sheng-zong He
The wire breakage of a no-cleaning process PCBA occurs at the beginning of the application. Through visual inspection, cross-section, SEM & EDS, and ion chromatography analysis, it was found that the high content of ions (bromide ion) on the surface of the solder source side caused corrosion and fracture of the conductors of wave soldering surface, this article also analyzes the source of bromide ion.
{"title":"The Case of Failure Analysis of the PCBA Wire Corrosion under High Reliability Requirements","authors":"Jie Zheng, Ying Yang, Jianghua Shen, Lili Ma, Sheng-zong He","doi":"10.1109/IPFA47161.2019.8984793","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984793","url":null,"abstract":"The wire breakage of a no-cleaning process PCBA occurs at the beginning of the application. Through visual inspection, cross-section, SEM & EDS, and ion chromatography analysis, it was found that the high content of ions (bromide ion) on the surface of the solder source side caused corrosion and fracture of the conductors of wave soldering surface, this article also analyzes the source of bromide ion.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128208206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984763
Wu Mengxue, Z. Lei, Liu Jiahui, H. Younan, Li Xiaomin
The dopant detection limit of SIMS instrument is a critical factor in semiconductor implant process monitoring and control. However, after various substrates are tested in the chamber, possible cross-contamination may lead to change of the detection limit, resulting in the inaccurate measurements and conclusions. In this paper, the cross-contamination effect is simulated with Phosphorus contaminant sputtered over the SIMS chamber. The degree of the cross-contamination is quantified and correlated with the detection limits. One of the failure cases is schematically illustrated and studied.
{"title":"Study of cross contamination between InP substrate and Silicon substrate during Phosphorus depth profile measurement","authors":"Wu Mengxue, Z. Lei, Liu Jiahui, H. Younan, Li Xiaomin","doi":"10.1109/IPFA47161.2019.8984763","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984763","url":null,"abstract":"The dopant detection limit of SIMS instrument is a critical factor in semiconductor implant process monitoring and control. However, after various substrates are tested in the chamber, possible cross-contamination may lead to change of the detection limit, resulting in the inaccurate measurements and conclusions. In this paper, the cross-contamination effect is simulated with Phosphorus contaminant sputtered over the SIMS chamber. The degree of the cross-contamination is quantified and correlated with the detection limits. One of the failure cases is schematically illustrated and studied.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132391889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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