Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984865
L. W. Lee, Mohamad Esa Azlin MohdNoor, M. M. Raj
(Al) based metallization has been widely used in semiconductor due to the process ability and the material behavior. However, pure Al based material cannot be used due to the hillock issue, void formation and also Al spiking caused by interaction with silicon. Thus, small amount of Copper (Cu) and Silicon (Si) precipitates were introduced into the Al layer to resolve these issues. Nowadays the bond pads metallization has becoming thinner owing to the recent semiconductor needs thus the presence of big Si precipitates will have risk leading to cratering issue in wire-bonding process. Here in, we report for the first time on how to quantify the Si precipitates counts and Si precipitates size in Al based metallization through failure analysis methods.
{"title":"Silicon Precipitates Counts and Size Study in Aluminium Bond Pads","authors":"L. W. Lee, Mohamad Esa Azlin MohdNoor, M. M. Raj","doi":"10.1109/IPFA47161.2019.8984865","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984865","url":null,"abstract":"(Al) based metallization has been widely used in semiconductor due to the process ability and the material behavior. However, pure Al based material cannot be used due to the hillock issue, void formation and also Al spiking caused by interaction with silicon. Thus, small amount of Copper (Cu) and Silicon (Si) precipitates were introduced into the Al layer to resolve these issues. Nowadays the bond pads metallization has becoming thinner owing to the recent semiconductor needs thus the presence of big Si precipitates will have risk leading to cratering issue in wire-bonding process. Here in, we report for the first time on how to quantify the Si precipitates counts and Si precipitates size in Al based metallization through failure analysis methods.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"421 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129042246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984841
R. Mendaros
The advent of the 65nm silicon fabrication technology node and smaller geometries; particularly for static random-access memory (SRAM) array, posed several Failure Analysis (FA) challenges such as the fault isolation capability limitations, physical FA (PFA) approach identification intricacy, defect node localization complexity and defect to fail mode correlation difficulty. To address these challenges, device defect modeling (DDM) process through software simulations and building of defect databases were introduced. Through the aid of the DDM process, defect sites were reduced to a single transistor or node from the SRAM array. Defect models were derived from the simulation process that guided analysts in identifying the suitable PFA approach. DDM process was effective in the failure mechanism to failure mode simulations. The DDM process was likewise instrumental in building defect databases for SRAM layout designs. These databases contained relevant information such as circuit simulation results, fabrication material stacking, suggested fault isolation techniques and potential defect locations that served as references for analysts.
{"title":"Enhancing the SRAM Failure Analysis Process","authors":"R. Mendaros","doi":"10.1109/IPFA47161.2019.8984841","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984841","url":null,"abstract":"The advent of the 65nm silicon fabrication technology node and smaller geometries; particularly for static random-access memory (SRAM) array, posed several Failure Analysis (FA) challenges such as the fault isolation capability limitations, physical FA (PFA) approach identification intricacy, defect node localization complexity and defect to fail mode correlation difficulty. To address these challenges, device defect modeling (DDM) process through software simulations and building of defect databases were introduced. Through the aid of the DDM process, defect sites were reduced to a single transistor or node from the SRAM array. Defect models were derived from the simulation process that guided analysts in identifying the suitable PFA approach. DDM process was effective in the failure mechanism to failure mode simulations. The DDM process was likewise instrumental in building defect databases for SRAM layout designs. These databases contained relevant information such as circuit simulation results, fabrication material stacking, suggested fault isolation techniques and potential defect locations that served as references for analysts.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129213655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984849
Jianan Wei, Hongxia Guo, Fengqi Zhang, G. Guo, Chaohui He
The single event effects (SEE) in ferroelectric random access memories (FRAM) are investigated and the error modes are analyzed using heavy ions. Under the irradiation of heavy ions with high linear energy transfer (LET) values, data upsets are dominated by "0" to "1" upsets of which the cross section is larger than that of "1" to "0" upsets by an order of magnitude and most upsets are detected in addresses with the all "1" error pattern (FFFFH). In addition, most of the upsets occur in events that involve several consecutively accessed addresses. With the increase of ion LET, the percentage of the data upsets in events involving more than 10 consecutively accessed addresses increases monotonically.
{"title":"Analysis of SEE modes in ferroelectric random access memory using heavy ions","authors":"Jianan Wei, Hongxia Guo, Fengqi Zhang, G. Guo, Chaohui He","doi":"10.1109/IPFA47161.2019.8984849","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984849","url":null,"abstract":"The single event effects (SEE) in ferroelectric random access memories (FRAM) are investigated and the error modes are analyzed using heavy ions. Under the irradiation of heavy ions with high linear energy transfer (LET) values, data upsets are dominated by \"0\" to \"1\" upsets of which the cross section is larger than that of \"1\" to \"0\" upsets by an order of magnitude and most upsets are detected in addresses with the all \"1\" error pattern (FFFFH). In addition, most of the upsets occur in events that involve several consecutively accessed addresses. With the increase of ion LET, the percentage of the data upsets in events involving more than 10 consecutively accessed addresses increases monotonically.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126537372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984867
Link Chang, Rick HC Wang, Andy Chang, Simon T. C. Wang, Yu Pang Chang, C. G. Song
As the analysis of SRAM Memory Built In Self Test (MBIST), some failure modes such as single bit (SB) or dual bit (DB) failure can be localized accurately. The inspection area of SRAM SB/DB is around 1~2um2. Traditionally, we can use the Focus Ion Beam (FIB) for cross section (X-S) checking as a much quicker inspection. However, X-S FIB inspection is not suitable to analyze some other failure modes such as bit line (BL) failure, which has a larger inspection area, around 200um2. We usually use the Scanning Electron Microscope (SEM) and I-Beam Voltage Contrast (VC) methods to have a plane-view check along the failed BL to find any abnormality. Sometimes a tiny defect is not easy to observe by plane-view checking. In this paper, three alternative methods, Low kV Electron Beam (E-Beam), Electron Beam Absorbed Current (EBAC) and Laser Voltage Image (LVI) are used in three real cases, and achieve a goal of higher hit rate and shorter cycle time.
{"title":"The Solutions of Bit Line Failure Analysis: Low kV E-Beam, EBAC and LVI","authors":"Link Chang, Rick HC Wang, Andy Chang, Simon T. C. Wang, Yu Pang Chang, C. G. Song","doi":"10.1109/IPFA47161.2019.8984867","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984867","url":null,"abstract":"As the analysis of SRAM Memory Built In Self Test (MBIST), some failure modes such as single bit (SB) or dual bit (DB) failure can be localized accurately. The inspection area of SRAM SB/DB is around 1~2um2. Traditionally, we can use the Focus Ion Beam (FIB) for cross section (X-S) checking as a much quicker inspection. However, X-S FIB inspection is not suitable to analyze some other failure modes such as bit line (BL) failure, which has a larger inspection area, around 200um2. We usually use the Scanning Electron Microscope (SEM) and I-Beam Voltage Contrast (VC) methods to have a plane-view check along the failed BL to find any abnormality. Sometimes a tiny defect is not easy to observe by plane-view checking. In this paper, three alternative methods, Low kV Electron Beam (E-Beam), Electron Beam Absorbed Current (EBAC) and Laser Voltage Image (LVI) are used in three real cases, and achieve a goal of higher hit rate and shorter cycle time.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"27 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114105316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984861
Li-mei Rong, Yugang Yin, Jinze He, Jiangfeng Du, T. Luo, Rong‐Ping Yang, Kun Gao, Qi Yu, Jiao Xu, Guang-hong Zhao
This paper discusses the local optical properties and the morphologies of interface and oxide layer of SiO2/SiC. The cross-section morphology of the SiO2/SiC after polishing and etching was illustrated by scanning electron microscopy, and the refractive index was characterized by ellipsometry. The ellipsometry based on multilayer interface model is better than that based on single-interface model in reflecting the gap layer and the different typical interface layers across the interface. A correlation is found between morphology and refractive index under the temperature range from 600 °C to 900 °C. The capacitance model including multilayer interface is established for sensitivity component in pressure sensor, and the maximum rate of capacitance drift is 3.56%.
{"title":"Correlation Analysis and Characterization of Micromorphology and Optoelectronic Properties of SiO2/SiC in Pressure Sensor","authors":"Li-mei Rong, Yugang Yin, Jinze He, Jiangfeng Du, T. Luo, Rong‐Ping Yang, Kun Gao, Qi Yu, Jiao Xu, Guang-hong Zhao","doi":"10.1109/IPFA47161.2019.8984861","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984861","url":null,"abstract":"This paper discusses the local optical properties and the morphologies of interface and oxide layer of SiO2/SiC. The cross-section morphology of the SiO2/SiC after polishing and etching was illustrated by scanning electron microscopy, and the refractive index was characterized by ellipsometry. The ellipsometry based on multilayer interface model is better than that based on single-interface model in reflecting the gap layer and the different typical interface layers across the interface. A correlation is found between morphology and refractive index under the temperature range from 600 °C to 900 °C. The capacitance model including multilayer interface is established for sensitivity component in pressure sensor, and the maximum rate of capacitance drift is 3.56%.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114119234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ipfa47161.2019.8984873
{"title":"IPFA 2019 Author Index","authors":"","doi":"10.1109/ipfa47161.2019.8984873","DOIUrl":"https://doi.org/10.1109/ipfa47161.2019.8984873","url":null,"abstract":"","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"347 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120883173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984826
H. Younan
IN our previous paper, we discussed the differences between EDS and AES and concluded that EDS couldn’t be used to determine F level on A Normal Al bondpad. In this paper, we will discuss how we can determine fluorine contamination level on a normal Al bondpad and propose to use AES/XPS to analyse fluorine level on a normal Al bondpad in wafer fabrication.
在我们之前的论文中，我们讨论了EDS和AES的区别，并得出EDS不能用于测定A Normal Al键垫上的F电平的结论。本文将讨论如何确定普通铝键合板上的氟污染水平，并提出使用AES/XPS分析晶圆制造中普通铝键合板上的氟污染水平。
{"title":"How To Determine Fluorine Contamination Level On A Normal Al Bondpad?","authors":"H. Younan","doi":"10.1109/IPFA47161.2019.8984826","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984826","url":null,"abstract":"IN our previous paper, we discussed the differences between EDS and AES and concluded that EDS couldn’t be used to determine F level on A Normal Al bondpad. In this paper, we will discuss how we can determine fluorine contamination level on a normal Al bondpad and propose to use AES/XPS to analyse fluorine level on a normal Al bondpad in wafer fabrication.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"28 47","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113941477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984814
Jinli Zhang, Hailong You, Renxu Jia
This paper presents a new method for characterizing device reliability hazard by using wafer-level spatial analysis. The method is based on the combination of the LOF algorithm and KNN algorithm, which can effectively identify and quantify the reliability of the device and detect local outliers. Outlier devices often have serious reliability hazard. This approach takes into account variations in device measurement data due to process variations on the wafer, increasing device reliability and saving cost. The method is verified using the electrical parameter measurements of devices. The results are compared with traditional method.
{"title":"Reliability hazard characterization of wafer-level spatial metrology parameters based on LOF-KNN method","authors":"Jinli Zhang, Hailong You, Renxu Jia","doi":"10.1109/IPFA47161.2019.8984814","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984814","url":null,"abstract":"This paper presents a new method for characterizing device reliability hazard by using wafer-level spatial analysis. The method is based on the combination of the LOF algorithm and KNN algorithm, which can effectively identify and quantify the reliability of the device and detect local outliers. Outlier devices often have serious reliability hazard. This approach takes into account variations in device measurement data due to process variations on the wafer, increasing device reliability and saving cost. The method is verified using the electrical parameter measurements of devices. The results are compared with traditional method.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124917488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984800
Lan Yin Lee, Kok Keng Chua
Time domain reflectometry (TDR) has gained attention in electrical verification for electronic components over the years. TDR works by sending a series of short pulses through a transmission line under investigation, and measures the reflections that result from a signal travelling through a transmission environment. [1], [2] It is often being used for short or open failures defect localization, to isolate whether the short/ open failure is in the die region or package region. With the enhancement of process technology and increase of layers in the package/ silicon die, and due to limitation of reference medium, the results produced by using TDR can only be used as a rough guide, i.e. based on the TDR results, we can only narrow the open/ short failure to be in the die or package, we could not tell which layer of package the short/open is. This paper demonstrates some successful cases with the incorporation of mathematics together with the use of TDR machine. Open failure can be accurately localized down to specific substrate layer via mathematics calculation. Physical failure analysis further confirmed the accuracy of this method by showing the defect at that specific layer in those cases.
{"title":"Enhanced Package Fault Isolation Method Using Time Domain Reflectometry (TDR) Incorporation with Mathematics","authors":"Lan Yin Lee, Kok Keng Chua","doi":"10.1109/IPFA47161.2019.8984800","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984800","url":null,"abstract":"Time domain reflectometry (TDR) has gained attention in electrical verification for electronic components over the years. TDR works by sending a series of short pulses through a transmission line under investigation, and measures the reflections that result from a signal travelling through a transmission environment. [1], [2] It is often being used for short or open failures defect localization, to isolate whether the short/ open failure is in the die region or package region. With the enhancement of process technology and increase of layers in the package/ silicon die, and due to limitation of reference medium, the results produced by using TDR can only be used as a rough guide, i.e. based on the TDR results, we can only narrow the open/ short failure to be in the die or package, we could not tell which layer of package the short/open is. This paper demonstrates some successful cases with the incorporation of mathematics together with the use of TDR machine. Open failure can be accurately localized down to specific substrate layer via mathematics calculation. Physical failure analysis further confirmed the accuracy of this method by showing the defect at that specific layer in those cases.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125303998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984846
Peter Chua Thin Wei, Foo Loke Sheng, Ng Kim Choo, K. Serrels, Kuyt Ku, Curt Lin, Tang Chih-yi
Scan design, being part of the most commonly practiced form of Design for Testability (DFT) has been developed to enable software based diagnosis for scan chain failures. Tessent Diagnosis helps to narrow down the reported failures to a suspected failing chain [1] - [5]. Unfortunately, scan chains can consist of hundreds to thousands of individual latches that can represent potential defect candidates and are typically distributed across the entire chip. Implementing global fault isolation techniques, which includes Photon Emission Microscopy (PEM) analysis, can lead to a collection of numerous anomalous emission spots. Cross mapping both the PEM results and the hundreds to thousands of individual scan cells to the CAD layout is both time-consuming and labor intensive. Moreover, selective cross mapping does not reveal the scan latches in chronological order, which is important for any scan chain analysis. One possible solution is to spatially map the scan latch list from the diagnosis file to the CAD layout to visualize the scan latch distribution quickly. This paper describes the use of this Scan Cell Visualizer through the use of case studies to demonstrate improved layout mapping efficiency and reduced overall failure analysis cycle time.
{"title":"Increased Fault Isolation Efficiency by Using Scan Cell Visualizer for Scan Chain Failures","authors":"Peter Chua Thin Wei, Foo Loke Sheng, Ng Kim Choo, K. Serrels, Kuyt Ku, Curt Lin, Tang Chih-yi","doi":"10.1109/IPFA47161.2019.8984846","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984846","url":null,"abstract":"Scan design, being part of the most commonly practiced form of Design for Testability (DFT) has been developed to enable software based diagnosis for scan chain failures. Tessent Diagnosis helps to narrow down the reported failures to a suspected failing chain [1] - [5]. Unfortunately, scan chains can consist of hundreds to thousands of individual latches that can represent potential defect candidates and are typically distributed across the entire chip. Implementing global fault isolation techniques, which includes Photon Emission Microscopy (PEM) analysis, can lead to a collection of numerous anomalous emission spots. Cross mapping both the PEM results and the hundreds to thousands of individual scan cells to the CAD layout is both time-consuming and labor intensive. Moreover, selective cross mapping does not reveal the scan latches in chronological order, which is important for any scan chain analysis. One possible solution is to spatially map the scan latch list from the diagnosis file to the CAD layout to visualize the scan latch distribution quickly. This paper describes the use of this Scan Cell Visualizer through the use of case studies to demonstrate improved layout mapping efficiency and reduced overall failure analysis cycle time.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"52 47","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114005911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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