Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984834
Zhe Zhang, Runsheng Wang, Yangyuan Wang, Ru Huang
In this paper, the channel doping concentration (Nch) dependence of negative bias temperature instability (NBTI) reliability and variability is comprehensively studied using ‘atomistic’ TCAD simulations. The ΔVth distributions and current density distributions at different Nch are investigated. It is helpful for understanding of NBTI degradation in nanoscale devices.
{"title":"Impacts of Channel Doping on NBTI Reliability and Variability in Nanoscale FinFETs","authors":"Zhe Zhang, Runsheng Wang, Yangyuan Wang, Ru Huang","doi":"10.1109/IPFA47161.2019.8984834","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984834","url":null,"abstract":"In this paper, the channel doping concentration (Nch) dependence of negative bias temperature instability (NBTI) reliability and variability is comprehensively studied using ‘atomistic’ TCAD simulations. The ΔVth distributions and current density distributions at different Nch are investigated. It is helpful for understanding of NBTI degradation in nanoscale devices.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123994555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984909
W. Hsieh, Henry Lin, Vincent Chen, Irene Ou, Y. Lou
In this report, a novel probe marker discoloration corrosion on Al pad, with donut/circle shape, was found. This probe marker discoloration corrosion was found at the stage of blue tape. Back to check the wafer process, no clear corrosion was found before CP probing test. In order to identify the microstructure & components of this probe marker discoloration corrosion, SEM/EDS, TEM/EELS & AES analysis were applied. These structure & surface analysis results indicated this discoloration is a combination of Aluminum, Fluorine and Oxygen. No Fluoride was detected on the normal region of Al pad. All these results implied the role of fluorine element to induce this probe marker discoloration corrosion. The source of F element is critical in this case, so the testing and storage conditions would be supposed to be important for the formation of probe marker discoloration corrosion. The HAST testing with condition of temperature 130°C and RH 85% for 21 hours, all the chip samples were simulated to have been exposed in air without N2 cabinet storage or MBB bag storage for 1 year. This HAST test result showed none of exhibition of discoloration or existed discoloration chips being deteriorated. Another storage test based on regular full wafer FOSB storage showed existed discoloration chips being deteriorated. This FOSB storage test indicated the source of corrosive F element maybe come from wafer itself. The EDS element mapping data indicated the F element enriched Al pad on wafer extreme edge area was clearly identified. The source of F element was found. And the storage of processed wafer would play a key role in the formation of discoloration corrosion.
{"title":"The probe marker discoloration on Al pad and wafer storage","authors":"W. Hsieh, Henry Lin, Vincent Chen, Irene Ou, Y. Lou","doi":"10.1109/IPFA47161.2019.8984909","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984909","url":null,"abstract":"In this report, a novel probe marker discoloration corrosion on Al pad, with donut/circle shape, was found. This probe marker discoloration corrosion was found at the stage of blue tape. Back to check the wafer process, no clear corrosion was found before CP probing test. In order to identify the microstructure & components of this probe marker discoloration corrosion, SEM/EDS, TEM/EELS & AES analysis were applied. These structure & surface analysis results indicated this discoloration is a combination of Aluminum, Fluorine and Oxygen. No Fluoride was detected on the normal region of Al pad. All these results implied the role of fluorine element to induce this probe marker discoloration corrosion. The source of F element is critical in this case, so the testing and storage conditions would be supposed to be important for the formation of probe marker discoloration corrosion. The HAST testing with condition of temperature 130°C and RH 85% for 21 hours, all the chip samples were simulated to have been exposed in air without N2 cabinet storage or MBB bag storage for 1 year. This HAST test result showed none of exhibition of discoloration or existed discoloration chips being deteriorated. Another storage test based on regular full wafer FOSB storage showed existed discoloration chips being deteriorated. This FOSB storage test indicated the source of corrosive F element maybe come from wafer itself. The EDS element mapping data indicated the F element enriched Al pad on wafer extreme edge area was clearly identified. The source of F element was found. And the storage of processed wafer would play a key role in the formation of discoloration corrosion.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127678845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984917
C. Hung, Jung-Chien Cheng, B. Tsui
SiC is suitable for high-power and high-temperature applications due to its’ wide energy bandgap and high thermal conductivity. Most literature focus on SiC nMOSFET due to higher electron mobility than hole. In this work, we fabricated 4HSiC pMOSFET using TiAl alloy as contact metal to reduce the contact resistivity. However, ultrahigh leakage current was measured among all terminals of the pMOSFET. By comparing with different contact schemes, the failure mechanism is attributed to Al spiking into the underneath poly-Si and SiO2 during the metallization process. Using suitable blocking layer such as LPCVD Si3N4 (300 nm) or PECVD Si3N4 (100 nm) on SiO2 (200 nm) can avoid Al spiking so that conventional pattern topology and TiAl metallization process can be used on device fabrication.
{"title":"Failure Analysis on TiAl Metallization Process for Ohmic Contact on 4H-SiC pMOSFET","authors":"C. Hung, Jung-Chien Cheng, B. Tsui","doi":"10.1109/IPFA47161.2019.8984917","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984917","url":null,"abstract":"SiC is suitable for high-power and high-temperature applications due to its’ wide energy bandgap and high thermal conductivity. Most literature focus on SiC nMOSFET due to higher electron mobility than hole. In this work, we fabricated 4HSiC pMOSFET using TiAl alloy as contact metal to reduce the contact resistivity. However, ultrahigh leakage current was measured among all terminals of the pMOSFET. By comparing with different contact schemes, the failure mechanism is attributed to Al spiking into the underneath poly-Si and SiO2 during the metallization process. Using suitable blocking layer such as LPCVD Si3N4 (300 nm) or PECVD Si3N4 (100 nm) on SiO2 (200 nm) can avoid Al spiking so that conventional pattern topology and TiAl metallization process can be used on device fabrication.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123789325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984860
Yuzhu Sun, Daisy Lu, D. Mark, C. Di, Jenny Fan, N. Leslie
LVx, including Laser Voltage Imaging(LVI) and Laser Voltage Probing(LVP), is an indispensable optical failure analysis tool set for design debug and yield ramp-up. Although LVI and LVP together provide a good coverage for failure analysis cases involving scan-chain functionality testing, their applicability remains limited when addressing pulsed signals from logic circuits with ever growing complexity. Laser Voltage Tracing(LVT), as a recent addition to the LVx suite, provides a global map, highlighting the active region with low duty-cycle voltage transition pattern. In this paper, we present a case study of the detection of timing abnormality for a waveform feature with <0.1% duty cycle by applying LVT. Complemented by LVP and Soft Defect Localization (SDL), the fault was localized down to two interconnected logic gates. Resistive interconnection was confirmed with Physical Failure Analysis(PFA).
{"title":"Optical Failure Analysis on Pulsed Signals Embedded in Logic Cloud – A Case Study of Laser Voltage Tracing","authors":"Yuzhu Sun, Daisy Lu, D. Mark, C. Di, Jenny Fan, N. Leslie","doi":"10.1109/IPFA47161.2019.8984860","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984860","url":null,"abstract":"LVx, including Laser Voltage Imaging(LVI) and Laser Voltage Probing(LVP), is an indispensable optical failure analysis tool set for design debug and yield ramp-up. Although LVI and LVP together provide a good coverage for failure analysis cases involving scan-chain functionality testing, their applicability remains limited when addressing pulsed signals from logic circuits with ever growing complexity. Laser Voltage Tracing(LVT), as a recent addition to the LVx suite, provides a global map, highlighting the active region with low duty-cycle voltage transition pattern. In this paper, we present a case study of the detection of timing abnormality for a waveform feature with <0.1% duty cycle by applying LVT. Complemented by LVP and Soft Defect Localization (SDL), the fault was localized down to two interconnected logic gates. Resistive interconnection was confirmed with Physical Failure Analysis(PFA).","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126585342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984900
Lua Winson, P. Angeline, G. Ranganathan, A. Girish, Ravikumar Venkat Krishnan
Analog circuits are traditionally harder to debug using light assisted device alteration (LADA) also known as dynamic laser stimulation (DLS), as the circuitry are too sensitive to carrier generations. This paper showcases a successful post-silicon debug on analog circuitries (start-up circuit) using nanosecond pulse-on-demand laser to perform DLS leading into root cause identification on a marginality issue in a sub-20nm FinFET technology device.
{"title":"Root Cause Analysis on Analog Circuit Using TR-LADA","authors":"Lua Winson, P. Angeline, G. Ranganathan, A. Girish, Ravikumar Venkat Krishnan","doi":"10.1109/IPFA47161.2019.8984900","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984900","url":null,"abstract":"Analog circuits are traditionally harder to debug using light assisted device alteration (LADA) also known as dynamic laser stimulation (DLS), as the circuitry are too sensitive to carrier generations. This paper showcases a successful post-silicon debug on analog circuitries (start-up circuit) using nanosecond pulse-on-demand laser to perform DLS leading into root cause identification on a marginality issue in a sub-20nm FinFET technology device.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125857606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984790
Shuxian Chen, Feng Lin, Bin Yang, Chunxu Li, Yu Huang
With the continuous expansion of power ICs in various industrial and consumer levels, the requirements for Laterally-Double-Diffused MOS(LDMOS) characteristics are getting more and more aggressive. BVon characteristics of LDMOS is rather critical for wide Safe Operation Area (SOA), requesting in higher-end fields such as automotive electronics. In this paper, based on the modular design of the 0.18μm Bipolar-CMOS-DMOS (BCD) medium and high voltage process platform, the process platform should not only consider the impact of the introduction of high-voltage process on CMOS, but also the impact of the special Back- End-Oxide-Layer(BEOL) process customized for embeds Non-Volatile Memory (E-NVM) on high-voltage devices. For the problem of insufficient on-state breakdown voltage (BVon) and poor on-chip uniformity of NLDMOS, we studied the influence mechanism about BEOL process on NLDMOS BVon characteristic.
{"title":"A new study of backend process on 0.18um BCD NLDMOS on-state BV characteristics","authors":"Shuxian Chen, Feng Lin, Bin Yang, Chunxu Li, Yu Huang","doi":"10.1109/IPFA47161.2019.8984790","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984790","url":null,"abstract":"With the continuous expansion of power ICs in various industrial and consumer levels, the requirements for Laterally-Double-Diffused MOS(LDMOS) characteristics are getting more and more aggressive. BVon characteristics of LDMOS is rather critical for wide Safe Operation Area (SOA), requesting in higher-end fields such as automotive electronics. In this paper, based on the modular design of the 0.18μm Bipolar-CMOS-DMOS (BCD) medium and high voltage process platform, the process platform should not only consider the impact of the introduction of high-voltage process on CMOS, but also the impact of the special Back- End-Oxide-Layer(BEOL) process customized for embeds Non-Volatile Memory (E-NVM) on high-voltage devices. For the problem of insufficient on-state breakdown voltage (BVon) and poor on-chip uniformity of NLDMOS, we studied the influence mechanism about BEOL process on NLDMOS BVon characteristic.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125511685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984819
Xuejian Qian, Li Tian, Gaojie Wen, Hao Zhang, Xiaocui Li
Due to metal layers coverage, many signals couldn’t be measured by mechanical probe test to perform electrical isolation. And usually EMMI[1] (Emission Microscope) or OBIRCH[2] (Optical Beam Induced Resistor Change) analysis can’t directly highlight the real defect for function failure. It’s difficult to isolate Zener diode failure because the current path which through others device. We can’t test the Zener diode leakage directly unless to cut the circuit to isolate the Zener diode alone. In the paper we proposed one novel and effective method for locating Zener diode defect on device level to avoid the irreversible destructive test. The main idea was that if there is a defect on Zener diode in spite we can’t find a leakage effected by others circuit but we can find the voltage is abnormal. Then we can use the function EMMI[3] to location the defect instead of cut the circuit to isolate the Zener diode alone. After PFA (Physical Failure Analysis), the defect was found. Thus, we believe the advantage measurement method is novel, effective and save cycle time. It was beneficial to our FA for Zener diode on device level in electrical failure isolation.
{"title":"Advanced Method to Locate The Defect on Zener Diode to Avoid Cutting The Circuit in Failure Analysis","authors":"Xuejian Qian, Li Tian, Gaojie Wen, Hao Zhang, Xiaocui Li","doi":"10.1109/IPFA47161.2019.8984819","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984819","url":null,"abstract":"Due to metal layers coverage, many signals couldn’t be measured by mechanical probe test to perform electrical isolation. And usually EMMI[1] (Emission Microscope) or OBIRCH[2] (Optical Beam Induced Resistor Change) analysis can’t directly highlight the real defect for function failure. It’s difficult to isolate Zener diode failure because the current path which through others device. We can’t test the Zener diode leakage directly unless to cut the circuit to isolate the Zener diode alone. In the paper we proposed one novel and effective method for locating Zener diode defect on device level to avoid the irreversible destructive test. The main idea was that if there is a defect on Zener diode in spite we can’t find a leakage effected by others circuit but we can find the voltage is abnormal. Then we can use the function EMMI[3] to location the defect instead of cut the circuit to isolate the Zener diode alone. After PFA (Physical Failure Analysis), the defect was found. Thus, we believe the advantage measurement method is novel, effective and save cycle time. It was beneficial to our FA for Zener diode on device level in electrical failure isolation.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126871346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984862
Guoliang Ma, Yanqing Zhang, Heyi Li, Chaoming Liu, Chunhua Qi, Yidan Wei, Tianqi Wang, S. Dong, Mingxue Huo
The conductivity recombination mechanism of different ions irradiation was investigated in n-type 4H-SiC Schottky diode. The incident ions were selected as 1 MeV electrons, 25 MeV C and 40 MeV Si ions, respectively. The primaiy knocked-on atoms (PKAs) distribution in the irradiated 4H-SiC is calculated by SRIM code. After irradiation, the carrier concentration changed significantly. Compared with virous particles irradiation, it is indicated that the carrier removal rates under these three irradiation conditions are greatly different. Based on the theoretical analysis, different conductivity compensation brought by different defect status is the major reason for the significant difference in carrier removal rate.
{"title":"Effect of Primary Knocked-on Atoms on Conductivity Compensation in N-type 4H-SiC Irradiated by 1 MeV Electrons, 25 MeV C Ions and 40 MeV Si Ions","authors":"Guoliang Ma, Yanqing Zhang, Heyi Li, Chaoming Liu, Chunhua Qi, Yidan Wei, Tianqi Wang, S. Dong, Mingxue Huo","doi":"10.1109/IPFA47161.2019.8984862","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984862","url":null,"abstract":"The conductivity recombination mechanism of different ions irradiation was investigated in n-type 4H-SiC Schottky diode. The incident ions were selected as 1 MeV electrons, 25 MeV C and 40 MeV Si ions, respectively. The primaiy knocked-on atoms (PKAs) distribution in the irradiated 4H-SiC is calculated by SRIM code. After irradiation, the carrier concentration changed significantly. Compared with virous particles irradiation, it is indicated that the carrier removal rates under these three irradiation conditions are greatly different. Based on the theoretical analysis, different conductivity compensation brought by different defect status is the major reason for the significant difference in carrier removal rate.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"67 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132738851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984899
J. F. Zhang, R. Gao, Z. Ji, W. Zhang
Negative bias temperature instability (NBTI) is a well known ageing process for CMOS technologies. Many early works were focused on large devices where device-to-device variations (DDV) are negligible. As device sizes downscale to nanometers, DDV becomes substantial. NBTI is a stochastic process and causes a time-dependent DDV. Characterizing the NBTI-generated defects in nanoscale devices has two main challenges. First, current fluctuates with time and this introduces uncertainties in measurements. Second, the test time is long and costly: to characterize the NBTI-induced DDV, it is essential to repeat the same test on multiple devices. This work reviews recent progresses in addressing these issues. Based on the As-grown-Generation (AG) model, it will be shown that the measurement uncertainties are dominated by As-grown hole traps and can be removed by subtracting the average value. To reduce the test time, the voltage step stress (VSS) technique is combined with the Stress-Discharge -Recharge (SDR) method. This VSS-SDR technique reduces test time to within one hour per device. The model extracted by VSS-SDR is verified by comparing its prediction with the test data obtained under conventional constant voltage stress.
{"title":"Challenge and solution for characterizing NBTI-generated defects in nanoscale devices","authors":"J. F. Zhang, R. Gao, Z. Ji, W. Zhang","doi":"10.1109/IPFA47161.2019.8984899","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984899","url":null,"abstract":"Negative bias temperature instability (NBTI) is a well known ageing process for CMOS technologies. Many early works were focused on large devices where device-to-device variations (DDV) are negligible. As device sizes downscale to nanometers, DDV becomes substantial. NBTI is a stochastic process and causes a time-dependent DDV. Characterizing the NBTI-generated defects in nanoscale devices has two main challenges. First, current fluctuates with time and this introduces uncertainties in measurements. Second, the test time is long and costly: to characterize the NBTI-induced DDV, it is essential to repeat the same test on multiple devices. This work reviews recent progresses in addressing these issues. Based on the As-grown-Generation (AG) model, it will be shown that the measurement uncertainties are dominated by As-grown hole traps and can be removed by subtracting the average value. To reduce the test time, the voltage step stress (VSS) technique is combined with the Stress-Discharge -Recharge (SDR) method. This VSS-SDR technique reduces test time to within one hour per device. The model extracted by VSS-SDR is verified by comparing its prediction with the test data obtained under conventional constant voltage stress.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129003164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984828
N. Chinone, T. Matsumoto, K. Koshikawa
We will demonstrate the capability of lock-in thermography (LIT) for fault localization in a packaged power semiconductor device by using high-emissivity film. Different types of films were investigated to explore suitable type of film for LIT. Pasting the selected film on the heatsink of a packaged device increased the signal-to-noise ratio of LIT analysis, which enhanced the nondestructive localization ability of LIT.
{"title":"Enhancement of localization capability of lock-in thermography for power semiconductor devices by searching high-emissivity films","authors":"N. Chinone, T. Matsumoto, K. Koshikawa","doi":"10.1109/IPFA47161.2019.8984828","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984828","url":null,"abstract":"We will demonstrate the capability of lock-in thermography (LIT) for fault localization in a packaged power semiconductor device by using high-emissivity film. Different types of films were investigated to explore suitable type of film for LIT. Pasting the selected film on the heatsink of a packaged device increased the signal-to-noise ratio of LIT analysis, which enhanced the nondestructive localization ability of LIT.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"312 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124438276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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