The effect of irradiation on monolayer MoS2 FET (field effect transistor) with 1 MeV electron beams was investigated. Raman spectroscopy and X-ray photoelectron spectroscopy (XPS) was measured before and after irradiation. The results show that electron irradiation produces a strong desulfurization effect. The electrical characteristics of the device were measured with fluence condition of 1.0×1012 and 3.0×1012cm-2. The channel leakage increases after irradiation while transfer and output current decrease. This phenomenon can be attributed to the combination of the states at the SiO2/MoS2 interfaces and Coulomb scattering. Our study will enhance the understanding of the influence of 1 MeV electron on MoS2-based nanoelectronics devices.
{"title":"Irradiation Effects of 1 MeV Electron on Monolayer MoS2 Field Effect Transistors","authors":"Yanqing Zhang, Chunhua Qi, S. Dong, Mingxue Huo, Guoliang Ma, Xuesong Zheng, Zhengyong Hua, Jiaming Zhou, Heyi Li, Chaoming Liu, Yidan Wei, Tianqi Wang","doi":"10.1109/IPFA47161.2019.8984891","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984891","url":null,"abstract":"The effect of irradiation on monolayer MoS2 FET (field effect transistor) with 1 MeV electron beams was investigated. Raman spectroscopy and X-ray photoelectron spectroscopy (XPS) was measured before and after irradiation. The results show that electron irradiation produces a strong desulfurization effect. The electrical characteristics of the device were measured with fluence condition of 1.0×1012 and 3.0×1012cm-2. The channel leakage increases after irradiation while transfer and output current decrease. This phenomenon can be attributed to the combination of the states at the SiO2/MoS2 interfaces and Coulomb scattering. Our study will enhance the understanding of the influence of 1 MeV electron on MoS2-based nanoelectronics devices.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122643639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984813
Li Lu, Ran Ye, Siyang Liu, Weifeng Sun
Electrical parameters degradations of silicon-on-insulator (SOI) lateral insulated-gate bipolar transistor (LIGBT) under repetitive electrostatic discharge (ESD) stresses have been investigated. After the repetitive ESD stresses, the degradation of threshold voltage (Vth) can be neglected due to the intact channel region. The decrease of on-resistance (Ron) is dominated by hot holes injection into the field oxide at the bird’s beak. Moreover, the saturation current (Ice,sat) is decreased dramatically because of hot holes injection and interface states generation at the poly-gate edge. Finally, a novel structure with an additional P-type region beneath the poly-gate edge has been proposed to suppress the device degradation under repetitive ESD stresses.
{"title":"Investigation of Electrical Parameters Degradations for 600V SOI-LIGBT under Repetitive ESD Stresses","authors":"Li Lu, Ran Ye, Siyang Liu, Weifeng Sun","doi":"10.1109/IPFA47161.2019.8984813","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984813","url":null,"abstract":"Electrical parameters degradations of silicon-on-insulator (SOI) lateral insulated-gate bipolar transistor (LIGBT) under repetitive electrostatic discharge (ESD) stresses have been investigated. After the repetitive ESD stresses, the degradation of threshold voltage (Vth) can be neglected due to the intact channel region. The decrease of on-resistance (Ron) is dominated by hot holes injection into the field oxide at the bird’s beak. Moreover, the saturation current (Ice,sat) is decreased dramatically because of hot holes injection and interface states generation at the poly-gate edge. Finally, a novel structure with an additional P-type region beneath the poly-gate edge has been proposed to suppress the device degradation under repetitive ESD stresses.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131418154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In the space radiation environment, the chip in the spacecraft is susceptible to radiation effects, which leading to the errors of the device. Therefore, the detection and repair of the errors is particularly important. Aiming at the soft and hard errors of memory cell caused by single event effect in space radiation environment, a memory architecture based on ECC circuit and BISR circuit is proposed to detect errors online, distinguish between soft and hard errors and repair them, so as to reduce the accumulation of errors. And the memory structure uses repair circuit and redundant memory to repair soft errors and hard errors respectively. The simulation results show that in normal read-write mode, the proposed memory structure not only can repair soft errors, but also can repair hard errors, and can detect unrepairable hard errors. It means that the proposed method is effective. when the memory size is 39 x 64K, the area of the ECC and the BIRA circuit is about 13.95% of the entire memory chip.
在空间辐射环境下，航天器中的芯片容易受到辐射效应的影响，从而导致器件的误差。因此，错误的检测和修复就显得尤为重要。针对空间辐射环境下单事件效应导致的存储单元软硬错误，提出了一种基于ECC电路和BISR电路的存储体系结构，能够在线检测错误，区分软硬错误并进行修复，从而减少错误的积累。存储结构采用修复电路和冗余存储器分别对软错误和硬错误进行修复。仿真结果表明，在正常读写模式下，该存储结构不仅能修复软错误，还能修复硬错误，并能检测出不可修复的硬错误。说明该方法是有效的。当存储器尺寸为39 x 64K时，ECC和BIRA电路的面积约占整个存储器芯片的13.95%。
{"title":"Design and Verification of SRAM Self-Detection Repair Based on ECC and BISR Circuit","authors":"Yanqing Zhang, Yinghun Piao, Mingxue Huo, Tianqi Wang, Guoliang Ma, Chaoming Liu, Jianning Ma, Kairui Guo, Chunhua Qi","doi":"10.1109/IPFA47161.2019.8984845","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984845","url":null,"abstract":"In the space radiation environment, the chip in the spacecraft is susceptible to radiation effects, which leading to the errors of the device. Therefore, the detection and repair of the errors is particularly important. Aiming at the soft and hard errors of memory cell caused by single event effect in space radiation environment, a memory architecture based on ECC circuit and BISR circuit is proposed to detect errors online, distinguish between soft and hard errors and repair them, so as to reduce the accumulation of errors. And the memory structure uses repair circuit and redundant memory to repair soft errors and hard errors respectively. The simulation results show that in normal read-write mode, the proposed memory structure not only can repair soft errors, but also can repair hard errors, and can detect unrepairable hard errors. It means that the proposed method is effective. when the memory size is 39 x 64K, the area of the ECC and the BIRA circuit is about 13.95% of the entire memory chip.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131642777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984816
Ajiang Li, Shaohong Li, Long Zhang, Jing Zhu, Tian Tian, Yanqin Zou, Guichuang Zhu, Weifeng Sun
The reverse recovery failure of the inherent diode in Separated-Shorted-Anode lateral insulated gate bipolar transistor (SSA-LIGBT) is investigated through Sentaurus TCAD. During reverse recovery process, high current commutating rate di/dt will result in large reverse recovery current peak. It is found that large reverse recovery current peak flowing through the P-body can easily trigger the parasitic NPN transistor at the emitter side. Subsequently, the triggered NPN transistor finally results in the reverse recovery failure of the inherent diode in SSA-LIGBT. A novel structure with double integrated NMOS is proposed to achieve high reverse recovery robustness. Furthermore, the new structure can eliminate Negative Differential Resistance regime completely at the same time.
{"title":"A Novel Reverse Conducting SOI-LIGBT with Double Integrated NMOS for Enhanced Reverse Recovery","authors":"Ajiang Li, Shaohong Li, Long Zhang, Jing Zhu, Tian Tian, Yanqin Zou, Guichuang Zhu, Weifeng Sun","doi":"10.1109/IPFA47161.2019.8984816","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984816","url":null,"abstract":"The reverse recovery failure of the inherent diode in Separated-Shorted-Anode lateral insulated gate bipolar transistor (SSA-LIGBT) is investigated through Sentaurus TCAD. During reverse recovery process, high current commutating rate di/dt will result in large reverse recovery current peak. It is found that large reverse recovery current peak flowing through the P-body can easily trigger the parasitic NPN transistor at the emitter side. Subsequently, the triggered NPN transistor finally results in the reverse recovery failure of the inherent diode in SSA-LIGBT. A novel structure with double integrated NMOS is proposed to achieve high reverse recovery robustness. Furthermore, the new structure can eliminate Negative Differential Resistance regime completely at the same time.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131101228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984918
Wang Bisheng, Lois Liao Jinzhi, Zhang Xi, Li Xiaomin, H. Younan, Tee Weikok, Yee Boonhwa, Mao Songlin, Yao Qinghong
Wire bond industry is transitioning from Au (gold) bonding wire to Cu (copper) bonding wire, due to the high cost of Au and comparatively much lower cost and good electricity conductivity of Cu. Whilst Cu is less reliable than Au. Cu is susceptible to corrosion especially under the presence of moisture and Cl (chloride). In this work, Au and Cu wires were ball bonded to Al pad and molded with EMC (epoxy mold compound) with different ranges of Cl. Cl was purposely added into EMC to trigger the failure. All EMC samples were prepared with pH range of 5 – 7. Reliability tests bHAST (biased highly accelerated stress test) and HTS (high temperature storage test) were conducted. The results showed that under dry condition, Cl was not easy to attack the wire bond, and failure did not occur unless high content of Cl (up to 500ppm) was present. On the contrary, under humid environment, even several ppm content of Cl would cause failure of Cu-Al wire bond. By comparison, under humid environment, as Au-Al wire bond formed corrosion products which locked the Cl, therefore Cl could not repeatedly serve as a catalyst. Au-Al failure occurred only with high ppm content of Cl (up to 500ppm). In addition, it is found that Cl will promote the Au-Al IMC growth in HTS and bHAST.
{"title":"Comparison of Cl effect on Au-Al and Cu-Al HTS and bHAST wire bond reliability performance","authors":"Wang Bisheng, Lois Liao Jinzhi, Zhang Xi, Li Xiaomin, H. Younan, Tee Weikok, Yee Boonhwa, Mao Songlin, Yao Qinghong","doi":"10.1109/IPFA47161.2019.8984918","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984918","url":null,"abstract":"Wire bond industry is transitioning from Au (gold) bonding wire to Cu (copper) bonding wire, due to the high cost of Au and comparatively much lower cost and good electricity conductivity of Cu. Whilst Cu is less reliable than Au. Cu is susceptible to corrosion especially under the presence of moisture and Cl (chloride). In this work, Au and Cu wires were ball bonded to Al pad and molded with EMC (epoxy mold compound) with different ranges of Cl. Cl was purposely added into EMC to trigger the failure. All EMC samples were prepared with pH range of 5 – 7. Reliability tests bHAST (biased highly accelerated stress test) and HTS (high temperature storage test) were conducted. The results showed that under dry condition, Cl was not easy to attack the wire bond, and failure did not occur unless high content of Cl (up to 500ppm) was present. On the contrary, under humid environment, even several ppm content of Cl would cause failure of Cu-Al wire bond. By comparison, under humid environment, as Au-Al wire bond formed corrosion products which locked the Cl, therefore Cl could not repeatedly serve as a catalyst. Au-Al failure occurred only with high ppm content of Cl (up to 500ppm). In addition, it is found that Cl will promote the Au-Al IMC growth in HTS and bHAST.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128080919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984868
XU Ze-kun, Shen Hong-yu, HU Tao, Guo-Chih Wei, Dong Shu-rong
A novel silicon-controlled rectifier (SCR) named VSCR with simple layout structure is proposed in this paper. With an embedded SCR structure in a traditional diode by using p-type ESD implantation, the proposed device achieves a high ESD robustness with a current level of 33.0 mA/μm. In addition, VSCR also have low trigger voltage and high holding voltage which make it suitable for ESD protection of 28-nm CMOS process. This paper also use a gate-monitor in parallel with the VSCR to obtain the true failure current of the device, which further proves that the structure can be used for ESD protection of the Core circuit under the 28-nm process.
{"title":"Vertical silicon-controlled rectifier for ESD protection under 28nm ps process","authors":"XU Ze-kun, Shen Hong-yu, HU Tao, Guo-Chih Wei, Dong Shu-rong","doi":"10.1109/IPFA47161.2019.8984868","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984868","url":null,"abstract":"A novel silicon-controlled rectifier (SCR) named VSCR with simple layout structure is proposed in this paper. With an embedded SCR structure in a traditional diode by using p-type ESD implantation, the proposed device achieves a high ESD robustness with a current level of 33.0 mA/μm. In addition, VSCR also have low trigger voltage and high holding voltage which make it suitable for ESD protection of 28-nm CMOS process. This paper also use a gate-monitor in parallel with the VSCR to obtain the true failure current of the device, which further proves that the structure can be used for ESD protection of the Core circuit under the 28-nm process.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133242753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984838
Feibo Du, Xiaoyu Dong, Chengjin Yang, Yichen Xu, Zhiwei Liu, Jizhi Liu, J. Liou
A robust dual directional SCR (RDDSCR) is proposed to suppress the current saturation effect in conventional dual directional SCR (DDSCR). By introducing a new current path with low resistance, the self-heating effect in NWELL regions of RDDSCR can be well avoided. The ESD I-V characteristics of RDDSCR and DDSCR are measured with the transmission line pulsing (TLP) tester. Moreover, TCAD simulation is also carried out to explore the physics mechanism in depth. Compared with DDSCR, the new RDDSCR possesses an improvement in failure current of 16.5% and an increase in holding voltage of about 2V. Furthermore, the influence of the external resistance on ESD performance of RDDSCR is also studied, where the resistance value of zero has been demonstrated to be a better option. Compared with the existing optimization methods, RDDSCR method has been proven to be more efficient in inhibiting current saturation effect of DDSCR without any compromise on turn-on characteristic.
{"title":"A Robust Dual Directional SCR without Current Saturation Effect for ESD Applications","authors":"Feibo Du, Xiaoyu Dong, Chengjin Yang, Yichen Xu, Zhiwei Liu, Jizhi Liu, J. Liou","doi":"10.1109/IPFA47161.2019.8984838","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984838","url":null,"abstract":"A robust dual directional SCR (RDDSCR) is proposed to suppress the current saturation effect in conventional dual directional SCR (DDSCR). By introducing a new current path with low resistance, the self-heating effect in NWELL regions of RDDSCR can be well avoided. The ESD I-V characteristics of RDDSCR and DDSCR are measured with the transmission line pulsing (TLP) tester. Moreover, TCAD simulation is also carried out to explore the physics mechanism in depth. Compared with DDSCR, the new RDDSCR possesses an improvement in failure current of 16.5% and an increase in holding voltage of about 2V. Furthermore, the influence of the external resistance on ESD performance of RDDSCR is also studied, where the resistance value of zero has been demonstrated to be a better option. Compared with the existing optimization methods, RDDSCR method has been proven to be more efficient in inhibiting current saturation effect of DDSCR without any compromise on turn-on characteristic.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"247 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114279106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984852
Kevin Joshua S. Cala, Junald C. Saludares, Wendel A. Basbas
A practical alternative for soft defect localization (SDL) and fault isolation of dynamic failures is presented. The approach utilizes an existing optical beam induced resistance change (OBIRCH) hardware without a dynamic laser stimulation (DLS) add-on kit, coupled with an exhaustive electrical sample prep step which involves code modification. The technique was proven effective in localizing failures pertaining to resistive interconnects which are rather difficult to analyze using conventional static techniques.
{"title":"Practical Dynamic Laser Stimulation Technique and Code Modification: A Soft Defect Localization Approach for Microcontroller Self-Test Failures","authors":"Kevin Joshua S. Cala, Junald C. Saludares, Wendel A. Basbas","doi":"10.1109/IPFA47161.2019.8984852","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984852","url":null,"abstract":"A practical alternative for soft defect localization (SDL) and fault isolation of dynamic failures is presented. The approach utilizes an existing optical beam induced resistance change (OBIRCH) hardware without a dynamic laser stimulation (DLS) add-on kit, coupled with an exhaustive electrical sample prep step which involves code modification. The technique was proven effective in localizing failures pertaining to resistive interconnects which are rather difficult to analyze using conventional static techniques.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123300870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984822
Meng Zhang, Xiaotong Ma, Zhendong Jiang, Sunbin Deng, Guijun Li, Rongsheng Chen, Yan Yan, M. Wong, H. Kwok
Light-illumination-induced degradation and its long-term recovery in indium-tin-zinc oxide (ITZO) thin-film transistors (TFTs) are investigated. Negative threshold voltage shift and subthreshold degradation are observed under light of 546.1 nm with 14.92 mW/cm2. Short-term recovery and long-term recovery of ITZO TFT exhibit two different characteristics. Incorporated with TCAD simulations, the degradation mechanism and recovery mechanism are tentatively discussed.
{"title":"Light-Illumination-Induced Degradation and Its Long-Term Recovery in Indium-Tin-Zinc Oxide Thin-Film Transistors","authors":"Meng Zhang, Xiaotong Ma, Zhendong Jiang, Sunbin Deng, Guijun Li, Rongsheng Chen, Yan Yan, M. Wong, H. Kwok","doi":"10.1109/IPFA47161.2019.8984822","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984822","url":null,"abstract":"Light-illumination-induced degradation and its long-term recovery in indium-tin-zinc oxide (ITZO) thin-film transistors (TFTs) are investigated. Negative threshold voltage shift and subthreshold degradation are observed under light of 546.1 nm with 14.92 mW/cm2. Short-term recovery and long-term recovery of ITZO TFT exhibit two different characteristics. Incorporated with TCAD simulations, the degradation mechanism and recovery mechanism are tentatively discussed.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122718026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984915
Yang Wang, Dandan Jia, Xijun Chen, Xiangliang Jin
This paper presents a detailed study of turn-on uniformity under electrostatic discharge events in single-finger and multi-finger traditional DDSCR devices. Since the structure of the multi-finger DDSCR device is not completely symmetrical, the electric field strength of each finger breakdown junction is different, resulting in different impact ionization rates. Therefore, each finger of device cannot be turned on at the same time, and the turned-on finger enters the snap back region and pull down the voltage of the device. If the ESD failure voltage Vt2 of the multi-finger device is less than the trigger voltage Vt1, then other fingers will not turn on until the device fails, and the ESD current can be only discharged through the partial area. The transmission line pulse (TLP) test results show that the failure currents It2 of the single-finger, 2-finger and 4-finger DDSCR devices are 6.22A, 11.83A and 13.33A, respectively, and the 4-finger device cannot be uniformly turned on.
{"title":"Analysis of Turn-on Uniformity of Multi-finger DDSCR Devices under ESD Stress","authors":"Yang Wang, Dandan Jia, Xijun Chen, Xiangliang Jin","doi":"10.1109/IPFA47161.2019.8984915","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984915","url":null,"abstract":"This paper presents a detailed study of turn-on uniformity under electrostatic discharge events in single-finger and multi-finger traditional DDSCR devices. Since the structure of the multi-finger DDSCR device is not completely symmetrical, the electric field strength of each finger breakdown junction is different, resulting in different impact ionization rates. Therefore, each finger of device cannot be turned on at the same time, and the turned-on finger enters the snap back region and pull down the voltage of the device. If the ESD failure voltage Vt2 of the multi-finger device is less than the trigger voltage Vt1, then other fingers will not turn on until the device fails, and the ESD current can be only discharged through the partial area. The transmission line pulse (TLP) test results show that the failure currents It2 of the single-finger, 2-finger and 4-finger DDSCR devices are 6.22A, 11.83A and 13.33A, respectively, and the 4-finger device cannot be uniformly turned on.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123847401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：