Pub Date : 1900-01-01DOI: 10.23919/SNW.2019.8782958
K. Peng, Tsung-Lin Huang, T. George, Horng-Chih Lin, Pei-Wen Li
We report the tunability of the sizes and inter-dot spacings of Ge coupled quantum dots (QDs) using nano-spacer technology in combination with selective oxidation of Si0.85Ge0.15. Spherical-shaped Ge QDs were formed at each sidewall corner of the nano-patterned Si3N4 ridges by thermal oxidation of poly-SiGe spacer layers encapsulating the Si3N4 nano-ridges. The diameters of the Ge spherical QDs are essentially determined by geometrical height, width, and length of the nano-spacer islands of poly-SiGe, which are tunable by adjusting the process times of their deposition and etch back. The inter-dot spacing between the Ge DQDs are controllable by adjusting the widths of the lithographically-patterned Si3N4 ridges and the thermal oxidation times. Our self-organization and self-alignment approach achieved high symmetry within the Ge DQDs in terms of the individual QD sizes as well as the coupling barriers between the QDs and external electrodes in close proximity.
{"title":"Feasibility of Ge Double Quantum Dots With High Symmetry and Tunability in Size and Inter-Dot Spacing","authors":"K. Peng, Tsung-Lin Huang, T. George, Horng-Chih Lin, Pei-Wen Li","doi":"10.23919/SNW.2019.8782958","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782958","url":null,"abstract":"We report the tunability of the sizes and inter-dot spacings of Ge coupled quantum dots (QDs) using nano-spacer technology in combination with selective oxidation of Si0.85Ge0.15. Spherical-shaped Ge QDs were formed at each sidewall corner of the nano-patterned Si3N4 ridges by thermal oxidation of poly-SiGe spacer layers encapsulating the Si3N4 nano-ridges. The diameters of the Ge spherical QDs are essentially determined by geometrical height, width, and length of the nano-spacer islands of poly-SiGe, which are tunable by adjusting the process times of their deposition and etch back. The inter-dot spacing between the Ge DQDs are controllable by adjusting the widths of the lithographically-patterned Si3N4 ridges and the thermal oxidation times. Our self-organization and self-alignment approach achieved high symmetry within the Ge DQDs in terms of the individual QD sizes as well as the coupling barriers between the QDs and external electrodes in close proximity.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115761853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.23919/SNW.2019.8782939
Shen-Yang Lee, Han-Wei Chen, C. Shen, P. Kuo, C. Chung, Yu-En Huang, Hsin-Yu Chen, T. Chao
We have experimentally demonstrated fully suspended nanowire (NW) gate-all-around (GAA) negative-capacitance (NC) field-effect transistors (FETs) with ultrasmall channel dimensions (5-nm $times 12.5 -$nm); they exhibit a remarkable $mathrm{I}_{on}-mathrm{I}_{off}$ ratio of over 1010. This work, for the first time, experimentally studies and compares the structures of metal-ferroelectric-metal-insulator-semiconductor (MFMIS) and metal-ferroelectric-insulator-semiconductor (MFIS) NCFETs. The GAA with the MFMIS structure has a higher on-state current owing to the metallic equal-potential layer and superior S.S $._{min}$ of 39.22 mV/decade. A ZrO2 seed-layer is inserted under HfZr $_{1-x}, mathrm{O}_{x}($ HZO) to improve the ferroelectric crystallinity. Consequently, post-metal annealing (PMA), the conventional crystallization annealing step, can be omitted in the presence of o-phase. The gate current $(mathrm{I}_{G})$ is monitored to verify the multi-domain HZO. A negative DIBL of -160 mV/V is observed because of the strong NC effect corresponding to previous simulated results.
{"title":"Experimental Demonstration of Performance Enhancement of MFMIS and MFIS for 5-nm × 12.5-nm Poly-Si Nanowire Gate-All-Around Negative Capacitance FETs Featuring Seed-Layer and PMA-Free Process","authors":"Shen-Yang Lee, Han-Wei Chen, C. Shen, P. Kuo, C. Chung, Yu-En Huang, Hsin-Yu Chen, T. Chao","doi":"10.23919/SNW.2019.8782939","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782939","url":null,"abstract":"We have experimentally demonstrated fully suspended nanowire (NW) gate-all-around (GAA) negative-capacitance (NC) field-effect transistors (FETs) with ultrasmall channel dimensions (5-nm $times 12.5 -$nm); they exhibit a remarkable $mathrm{I}_{on}-mathrm{I}_{off}$ ratio of over 1010. This work, for the first time, experimentally studies and compares the structures of metal-ferroelectric-metal-insulator-semiconductor (MFMIS) and metal-ferroelectric-insulator-semiconductor (MFIS) NCFETs. The GAA with the MFMIS structure has a higher on-state current owing to the metallic equal-potential layer and superior S.S $._{min}$ of 39.22 mV/decade. A ZrO2 seed-layer is inserted under HfZr $_{1-x}, mathrm{O}_{x}($ HZO) to improve the ferroelectric crystallinity. Consequently, post-metal annealing (PMA), the conventional crystallization annealing step, can be omitted in the presence of o-phase. The gate current $(mathrm{I}_{G})$ is monitored to verify the multi-domain HZO. A negative DIBL of -160 mV/V is observed because of the strong NC effect corresponding to previous simulated results.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123828148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.23919/SNW.2019.8782951
C. Chiang, P. Husan, Y. Lou, F. L. Li, E. Hsieh, C. H. Liu, S. Chung
We develop experimental approaches to quantitatively extract the negative capacitance of MIM in a gate stacked NCFET. It was found that the NC effect is highly dependent on the grain and dipole behaviors with different annealing temperature. Also, to achieve a better design of high-performance NCFET, we explore not only the capacitance matching between ferroelectric HZO MIM and MOSFET but also how effective mobility is affected by HZO dipoles. For capacitance matching, we observe a 50x enhancement of overall gate capacitance triggered by NC effect, while, however, it adversely generated the degradation of the mobility. This mobility degradation is induced by the remote scattering from the ferroelectric HZO dipoles. Fortunately, if suitable polarization can be formed to align the HZO dipoles, the effects of remote scattering can be mitigated. From a trade-off between gate capacitance and the mobility, an NCFET with desirable performance can be achieved.
{"title":"The Understanding of Gate Capacitance Matching on Achieving a High Performance NC MOSFET with Sufficient Mobility","authors":"C. Chiang, P. Husan, Y. Lou, F. L. Li, E. Hsieh, C. H. Liu, S. Chung","doi":"10.23919/SNW.2019.8782951","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782951","url":null,"abstract":"We develop experimental approaches to quantitatively extract the negative capacitance of MIM in a gate stacked NCFET. It was found that the NC effect is highly dependent on the grain and dipole behaviors with different annealing temperature. Also, to achieve a better design of high-performance NCFET, we explore not only the capacitance matching between ferroelectric HZO MIM and MOSFET but also how effective mobility is affected by HZO dipoles. For capacitance matching, we observe a 50x enhancement of overall gate capacitance triggered by NC effect, while, however, it adversely generated the degradation of the mobility. This mobility degradation is induced by the remote scattering from the ferroelectric HZO dipoles. Fortunately, if suitable polarization can be formed to align the HZO dipoles, the effects of remote scattering can be mitigated. From a trade-off between gate capacitance and the mobility, an NCFET with desirable performance can be achieved.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"308 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134484204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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