Pub Date : 2019-06-01DOI: 10.23919/SNW.2019.8782962
E. Prati, M. Celebrano, L. Ghirardini, M. Finazzi, G. Ferrari, T. Shinada, Keinan Gi, Y. Chiba, A. Abdelghafar, M. Yano, T. Tanii
We report on the photocurrent induced by 1550 nm laser irradiation in a Er-doped micron-scale silicon transistor. The erbium defects, activated in the channel of the transistor thanks to oxygen codoping, make it possible to observe a resonant photocurrent at telecom wavelength and at room temperature by using a supercontinuum laser source working in the $mumathrm {W}$ range. By exploiting a back-gate, the transistor is tuned to exploit only the electrons lying in the Er-O states. We estimate a relatively small number of photoexcited atoms $(sim 4times 10^{4})$ making Er-dpoed silicon a candidate for designing resonance-based frequency selective single photon detectors at 1550 nm for quantum communications.
{"title":"Resonant Photocurrent at 1550 nm in an Erbium Low-Doped Silicon Transistor at Room Temperature","authors":"E. Prati, M. Celebrano, L. Ghirardini, M. Finazzi, G. Ferrari, T. Shinada, Keinan Gi, Y. Chiba, A. Abdelghafar, M. Yano, T. Tanii","doi":"10.23919/SNW.2019.8782962","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782962","url":null,"abstract":"We report on the photocurrent induced by 1550 nm laser irradiation in a Er-doped micron-scale silicon transistor. The erbium defects, activated in the channel of the transistor thanks to oxygen codoping, make it possible to observe a resonant photocurrent at telecom wavelength and at room temperature by using a supercontinuum laser source working in the $mumathrm {W}$ range. By exploiting a back-gate, the transistor is tuned to exploit only the electrons lying in the Er-O states. We estimate a relatively small number of photoexcited atoms $(sim 4times 10^{4})$ making Er-dpoed silicon a candidate for designing resonance-based frequency selective single photon detectors at 1550 nm for quantum communications.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126665366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/SNW.2019.8782957
Ryoongbin Lee, Junil Lee, Sangwan Kim, Kitae Lee, Sihyun Kim, Soyoun Kim, Yunho Choi, Byung-Gook Park
In this study, we suggest an improvement method for high ON/OFF ratio and steep subthreshold swing (SS) which are suitable for gate-all-around (GAA) SiGe tunnel field-effect Transistor (TFET). Through technology-computer-aided-design (TCAD) simulation, the effect of Ge condensation on the device performance is examined. Furthermore, SiGe nanowire (NW) channel with high Ge ratio (over 70%) is successfully formed and the advantage of gradually-distributed Ge throughout the SiGe NW is also investigated.
{"title":"Ge Condensation Process for High ON/OFF Ratio of SiGe Gate-All-Around Nanowire Tunnel Field-Effect Transistor","authors":"Ryoongbin Lee, Junil Lee, Sangwan Kim, Kitae Lee, Sihyun Kim, Soyoun Kim, Yunho Choi, Byung-Gook Park","doi":"10.23919/SNW.2019.8782957","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782957","url":null,"abstract":"In this study, we suggest an improvement method for high ON/OFF ratio and steep subthreshold swing (SS) which are suitable for gate-all-around (GAA) SiGe tunnel field-effect Transistor (TFET). Through technology-computer-aided-design (TCAD) simulation, the effect of Ge condensation on the device performance is examined. Furthermore, SiGe nanowire (NW) channel with high Ge ratio (over 70%) is successfully formed and the advantage of gradually-distributed Ge throughout the SiGe NW is also investigated.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124376911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/SNW.2019.8782898
T. Endoh
In this invited Plenary-talk, technologies regarding to STT-MRAM and NVLogic such as NV-AI VLSIs with CMOS/MTJ Hybrid technology are reviewed with our recent research results including fabricated chips
{"title":"Ultra-Low Power Brain-Inspired Processors and Neuromorphic Processors With CMOS/MTJ Hybrid Technology","authors":"T. Endoh","doi":"10.23919/SNW.2019.8782898","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782898","url":null,"abstract":"In this invited Plenary-talk, technologies regarding to STT-MRAM and NVLogic such as NV-AI VLSIs with CMOS/MTJ Hybrid technology are reviewed with our recent research results including fabricated chips","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"15 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120859741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/SNW.2019.8782970
C. Chu, G. Luo, Kehuey Wu, Shih-Hong Chen, Chieng-Chung Hsu, Bo-Yuan Chen, Kun‐Lin Lin, Wen-Fa Wu, W. Yeh
Horizontally five stacked pure-Ge nanosheets (NSs) GAA FETs are demonstrated. In this device process, we intentionally grow large mismatch Ge/Si multilayers rather than Ge/GeSi multilayers as the starting material, because the large difference of material properties between Ge/Si is beneficial to the selective etching process. In order to avoid island growth, the flat Ge/Si multilayers are grown at a low temperature. Due to the excellent selective etching, the shape of Ge NSs almost keeps unchanged after etching. Additionally we found the dislocations in suspended Ge sheets are more easily to remove than the case that Ge layers are still tied with Si layers. Since the stacked NSs channels is tall and the pitch between channels is short, the conventional wrap-around contact (WAC) is not applicable. Here for the first time we propose the conformal monolayer doping (MLD) method for source/drain doping of tall NSs FETs.
{"title":"The GAAFETs with Five Stacked Ge Nano-sheets Made by 2D Ge/Si Multilayer Epitaxy, Excellent Selective Etching, and Conformal Monolayer Doping","authors":"C. Chu, G. Luo, Kehuey Wu, Shih-Hong Chen, Chieng-Chung Hsu, Bo-Yuan Chen, Kun‐Lin Lin, Wen-Fa Wu, W. Yeh","doi":"10.23919/SNW.2019.8782970","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782970","url":null,"abstract":"Horizontally five stacked pure-Ge nanosheets (NSs) GAA FETs are demonstrated. In this device process, we intentionally grow large mismatch Ge/Si multilayers rather than Ge/GeSi multilayers as the starting material, because the large difference of material properties between Ge/Si is beneficial to the selective etching process. In order to avoid island growth, the flat Ge/Si multilayers are grown at a low temperature. Due to the excellent selective etching, the shape of Ge NSs almost keeps unchanged after etching. Additionally we found the dislocations in suspended Ge sheets are more easily to remove than the case that Ge layers are still tied with Si layers. Since the stacked NSs channels is tall and the pitch between channels is short, the conventional wrap-around contact (WAC) is not applicable. Here for the first time we propose the conformal monolayer doping (MLD) method for source/drain doping of tall NSs FETs.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126564292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/SNW.2019.8782950
Daiki Kojima, Toshiki Nakamura, K. Takeuchi
Read-disturb Modeled Artificial Neural Network Coupled LDPC ECC (RDNN-LDPC) is proposed to correct errors of read-hot data for 3D-TLC NAND flash. Conventional ANN-LDPC is optimized to correct errors of read-cold data. However, ANN-LDPC does not correct errors of read-hot data. To correct errors of read-hot data, this paper analyzes how input parameter and model change. As a result, measured results of proposed RDNN-LDPC extend acceptable read cycle of 3D-TLC NAND flash by 10-times.
{"title":"Error Crrection for Read-hot Data in 3D-TLC NAND Flash by Read-disturb Modeled Artificial Neural Network Coupled LDPC ECC","authors":"Daiki Kojima, Toshiki Nakamura, K. Takeuchi","doi":"10.23919/SNW.2019.8782950","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782950","url":null,"abstract":"Read-disturb Modeled Artificial Neural Network Coupled LDPC ECC (RDNN-LDPC) is proposed to correct errors of read-hot data for 3D-TLC NAND flash. Conventional ANN-LDPC is optimized to correct errors of read-cold data. However, ANN-LDPC does not correct errors of read-hot data. To correct errors of read-hot data, this paper analyzes how input parameter and model change. As a result, measured results of proposed RDNN-LDPC extend acceptable read cycle of 3D-TLC NAND flash by 10-times.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126840225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we propose a machine-learning assisted modeling framework in design-technology co-optimization (DTCO) flow. Neural network (NN) based surrogate model is used as an alternative of compact model of new devices without prior knowledge of device physics to predict device and circuit electrical characteristics. This modeling framework is demonstrated and verified in FinFET with high predicted accuracy in device and circuit level. Details about the data handling and prediction results are discussed. Moreover, same framework is applied to new mechanism device tunnel FET (TFET) to predict device and circuit characteristics. This work provides new modeling method for DTCO flow.
{"title":"New-Generation Design-Technology Co-Optimization (DTCO): Machine-Learning Assisted Modeling Framework","authors":"Zhe Zhang, Runsheng Wang, Cheng Chen, Qianqian Huang, Yangyuan Wang, Cheng Hu, Dehuang Wu, Joddy W. Wang, Ru Huang","doi":"10.23919/SNW.2019.8782897","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782897","url":null,"abstract":"In this paper, we propose a machine-learning assisted modeling framework in design-technology co-optimization (DTCO) flow. Neural network (NN) based surrogate model is used as an alternative of compact model of new devices without prior knowledge of device physics to predict device and circuit electrical characteristics. This modeling framework is demonstrated and verified in FinFET with high predicted accuracy in device and circuit level. Details about the data handling and prediction results are discussed. Moreover, same framework is applied to new mechanism device tunnel FET (TFET) to predict device and circuit characteristics. This work provides new modeling method for DTCO flow.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"255 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116735519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Stochastic computing (SC) presents high error tolerance and low hardware cost, and has great potential in applications such as neural networks and image processing. However, the bitstream generator, which converts a binary number to bitstreams, occupies a large area and energy consumption, thus weakening the superiority of SC. In this paper, we propose a novel technique for generating bitstreams in parallel, which needs only one clock for conversion and significantly reduces the hardware cost. Synthesis results demonstrate that the proposed parallel bitstream generator improves 2.5× area and 712× energy consumption.
{"title":"A Parallel Bitstream Generator for Stochastic Computing","authors":"Yawen Zhang, Runsheng Wang, Xinyue Zhang, Zherui Zhang, Jiahao Song, Zuodong Zhang, Y. Wang, Ru Huang","doi":"10.23919/SNW.2019.8782977","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782977","url":null,"abstract":"Stochastic computing (SC) presents high error tolerance and low hardware cost, and has great potential in applications such as neural networks and image processing. However, the bitstream generator, which converts a binary number to bitstreams, occupies a large area and energy consumption, thus weakening the superiority of SC. In this paper, we propose a novel technique for generating bitstreams in parallel, which needs only one clock for conversion and significantly reduces the hardware cost. Synthesis results demonstrate that the proposed parallel bitstream generator improves 2.5× area and 712× energy consumption.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"205 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126157799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-21DOI: 10.23919/SNW.2019.8782973
Nobuhiko Kurata, T. Oya
We propose a new single-electron (SE) circuit mimicking a behavior of bubble film. The SE device that can operate using individual electrons by controlling a quantum effect (Coulomb blockade) has tunnel junctions as a main component [1]. It is known that it has many advantages, including extremely low power consumption, being high integrability. However, there is a problem that an optimal information-processing way has not been established, although many applications for SE devices have been proposed up to now. As a candidate of the way, we draw inspiration from a natural phenomenon, i.e., behaviors shown in soap bubble films, that can be regarded as a form of information processing. The bubble film forms a special structure caused that the surface tension of the film has the minimum energy. From the perspective of engineering, it can be assumed to solve a certain nonlinear problem that is the shortest Steiner problem using this property. For example, when two plastic boards are prepared, placed face to face, connected each other using a few plastic pillars, immersed in the bubble liquid, and pulled up, then the bubble film shrinks depend on the placed pillars. It is known that this shrunken form of the file shows the solution of the shortest Steiner problem [2]. In this study, we aim to design a new information-processing system on the SE devices that can solve the shortest Steiner problem by mimicking the behavior of the bubble film.
{"title":"Design of Multi-Layer Single-Electron Information-Processing Circuit Mimicking Behavior of Bubble Film for Solving Nonlinear Problem","authors":"Nobuhiko Kurata, T. Oya","doi":"10.23919/SNW.2019.8782973","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782973","url":null,"abstract":"We propose a new single-electron (SE) circuit mimicking a behavior of bubble film. The SE device that can operate using individual electrons by controlling a quantum effect (Coulomb blockade) has tunnel junctions as a main component [1]. It is known that it has many advantages, including extremely low power consumption, being high integrability. However, there is a problem that an optimal information-processing way has not been established, although many applications for SE devices have been proposed up to now. As a candidate of the way, we draw inspiration from a natural phenomenon, i.e., behaviors shown in soap bubble films, that can be regarded as a form of information processing. The bubble film forms a special structure caused that the surface tension of the film has the minimum energy. From the perspective of engineering, it can be assumed to solve a certain nonlinear problem that is the shortest Steiner problem using this property. For example, when two plastic boards are prepared, placed face to face, connected each other using a few plastic pillars, immersed in the bubble liquid, and pulled up, then the bubble film shrinks depend on the placed pillars. It is known that this shrunken form of the file shows the solution of the shortest Steiner problem [2]. In this study, we aim to design a new information-processing system on the SE devices that can solve the shortest Steiner problem by mimicking the behavior of the bubble film.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133688187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.23919/SNW.2019.8782904
Yu-An Huang, Yu-Hsiang Yeh, Horng-Chih Lin, Pei-Wen Li
We employed Sentaurus TCAD simulation to explore the impacts of major structural parameters on the electrical characteristics of poly-Si TFTs with T-gate and air spacers. The effects and trade-off between the source/drain (S/D) junctions relative to T-gate are discussed with the aim to find insightful information for the design and fabrication of real devices. Influences of the gate geometry on the parasitic capacitances of the T-gate devices are also simulated.
{"title":"Structual Design of T-gate, Air-spacer Poly-Si TFTs for RF applications","authors":"Yu-An Huang, Yu-Hsiang Yeh, Horng-Chih Lin, Pei-Wen Li","doi":"10.23919/SNW.2019.8782904","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782904","url":null,"abstract":"We employed Sentaurus TCAD simulation to explore the impacts of major structural parameters on the electrical characteristics of poly-Si TFTs with T-gate and air spacers. The effects and trade-off between the source/drain (S/D) junctions relative to T-gate are discussed with the aim to find insightful information for the design and fabrication of real devices. Influences of the gate geometry on the parasitic capacitances of the T-gate devices are also simulated.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"606 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122208106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.23919/SNW.2019.8782963
Che-Lun Fan, Kuei-Yang Tseng, You-Sheng Liu, P. Su
Using TCAD atomistic simulation, this work investigates the ferroelectric layer granularity of double-gate (DG) negative-capacitance FETs (NCFET) by considering both position and number fluctuations. Our study indicates that the impacts of the ferroelectric ratio on threshold voltage (VT) and subthreshold swing (SS) variations exhibit non-monotonic characteristics, and it is important to include the number fluctuation of the ferroelectric grain to accurately account for the overall variation. In addition, smaller grain size not only reduces the VT and SS variations, but also improves the mean value of the subthreshold swing.
{"title":"Investigation of Ferroelectric Granularity for Double-Gate Negative-Capacitance FETs Considering Position and Number Fluctuations","authors":"Che-Lun Fan, Kuei-Yang Tseng, You-Sheng Liu, P. Su","doi":"10.23919/SNW.2019.8782963","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782963","url":null,"abstract":"Using TCAD atomistic simulation, this work investigates the ferroelectric layer granularity of double-gate (DG) negative-capacitance FETs (NCFET) by considering both position and number fluctuations. Our study indicates that the impacts of the ferroelectric ratio on threshold voltage (VT) and subthreshold swing (SS) variations exhibit non-monotonic characteristics, and it is important to include the number fluctuation of the ferroelectric grain to accurately account for the overall variation. In addition, smaller grain size not only reduces the VT and SS variations, but also improves the mean value of the subthreshold swing.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123922658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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