Pub Date : 2019-06-01DOI: 10.23919/SNW.2019.8782965
L. Bolotov, N. Uchida, W. Chang, T. Maeda, S. Migita
This work addresses nanoscale measurements of mechanical properties of ultra-thin insulator films by a dynamic indentation atomic force microscopy (DI-AFM). The ability of the DI-AFM is discussed to clarify some challenges in quantitative evaluation of stiffness and elastic modulus of 10 nm films on Ge and S.i.
{"title":"Elastic Response of 10-nm Insulator Films Measured by Dynamic Indentation for Nano-scale Electron Device Fabrication","authors":"L. Bolotov, N. Uchida, W. Chang, T. Maeda, S. Migita","doi":"10.23919/SNW.2019.8782965","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782965","url":null,"abstract":"This work addresses nanoscale measurements of mechanical properties of ultra-thin insulator films by a dynamic indentation atomic force microscopy (DI-AFM). The ability of the DI-AFM is discussed to clarify some challenges in quantitative evaluation of stiffness and elastic modulus of 10 nm films on Ge and S.i.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"143 23","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132845401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/SNW.2019.8782967
Yizhou Zhang, Zheng Zhou, Peng Huang, Mengqi Fan, Runze Han, W. Shen, Lifeng Liu, Xiaoyan Liu, Jinfeng Kang
An improved hardware acceleration architecture of RRAM based Binary Neural Networks (BNNs) is proposed and demonstrated. In the architecture, a 1T1R array-based propagation module is introduced and designed to realize the computing acceleration of fully parallel Vector-Matrix Multiplication (VMM) in both forward and backward propagation. By using the propagation module, high acceleration is achieved in both training (50×) and inference (273×) process.
{"title":"An Improved Hardware Accelaration Architecture of Binary Neural Network With 1T1R Array Based Forward/Backward Propagation Module","authors":"Yizhou Zhang, Zheng Zhou, Peng Huang, Mengqi Fan, Runze Han, W. Shen, Lifeng Liu, Xiaoyan Liu, Jinfeng Kang","doi":"10.23919/SNW.2019.8782967","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782967","url":null,"abstract":"An improved hardware acceleration architecture of RRAM based Binary Neural Networks (BNNs) is proposed and demonstrated. In the architecture, a 1T1R array-based propagation module is introduced and designed to realize the computing acceleration of fully parallel Vector-Matrix Multiplication (VMM) in both forward and backward propagation. By using the propagation module, high acceleration is achieved in both training (50×) and inference (273×) process.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133365846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/SNW.2019.8782933
Y. Long, Jun Z. Huang, Zhongming Wei, Jun-Wei Luo, Xiangwei Jiang
The gate-controlled strain induced by piezoelectric layers is used to boost the ON current of InAs $n -$ type piezoelectric tunnel FETs. The advanced NEGF method with strained 8-band ${kcdot p}$ Hamiltonian is employed in transport simulation. Our results suggest that the Piezo-TFETs can achieve about 80% enhancement of ION for the optimal device orientation $[overline{mathbf{1}} mathbf{1} mathbf{0}] /(mathbf{1} mathbf{1} mathbf{0})$.
{"title":"ON Current Enhancement by Gate Controlled Strain in The InAs n-Type Piezoelectric Tunnel FETs","authors":"Y. Long, Jun Z. Huang, Zhongming Wei, Jun-Wei Luo, Xiangwei Jiang","doi":"10.23919/SNW.2019.8782933","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782933","url":null,"abstract":"The gate-controlled strain induced by piezoelectric layers is used to boost the ON current of InAs $n -$ type piezoelectric tunnel FETs. The advanced NEGF method with strained 8-band ${kcdot p}$ Hamiltonian is employed in transport simulation. Our results suggest that the Piezo-TFETs can achieve about 80% enhancement of ION for the optimal device orientation $[overline{mathbf{1}} mathbf{1} mathbf{0}] /(mathbf{1} mathbf{1} mathbf{0})$.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125318749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A capacitive coupled radio frequency double-pipe atmospheric-pressure plasma jet is used for the etching process in fabricating Micro Electro Mechanical Systems. Etchings were carried out on a crystalline silicon substrate. The etching rates can be controlled by the etch gas composition and the plasma conditions.
{"title":"The Prelimniary Investigation of Octrafluorocyclobutane Plasma Jet Etching of Crystalline Silicon","authors":"Chun-Hao Huang, Wei-Ting Liu, Weiliang Li, Li-Ko Huang, Yi-An Chen","doi":"10.23919/SNW.2019.8782945","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782945","url":null,"abstract":"A capacitive coupled radio frequency double-pipe atmospheric-pressure plasma jet is used for the etching process in fabricating Micro Electro Mechanical Systems. Etchings were carried out on a crystalline silicon substrate. The etching rates can be controlled by the etch gas composition and the plasma conditions.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115052818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/SNW.2019.8782952
Dong Keun Lee, Min-Hwi Kim, Suhyun Bang, Tae-Hyeon Kim, Yeon-Joon Choi, Sungjun Kim, Seongjae Cho, Byung-Gook Park
This paper presents switching characteristics of Ni/HfOx/p+-Si with different switching layer thicknesses (5/10 nm) in DC mode. Larger forming voltage and on/off ratio is obtained from the 10 nm HfOx RRAM while step-like reset process is seen from 5 nm HfOx RRAM. From the measurement results, fabricated RRAM device with thicker switching layer is more suitable for nonvolatile memory operation while thinner HfOx layer has potential for application in neuromorphic computing system.
{"title":"Comparison of switching characteristics of HfOx RRAM device with different switching layer thicknesses","authors":"Dong Keun Lee, Min-Hwi Kim, Suhyun Bang, Tae-Hyeon Kim, Yeon-Joon Choi, Sungjun Kim, Seongjae Cho, Byung-Gook Park","doi":"10.23919/SNW.2019.8782952","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782952","url":null,"abstract":"This paper presents switching characteristics of Ni/HfOx/p+-Si with different switching layer thicknesses (5/10 nm) in DC mode. Larger forming voltage and on/off ratio is obtained from the 10 nm HfOx RRAM while step-like reset process is seen from 5 nm HfOx RRAM. From the measurement results, fabricated RRAM device with thicker switching layer is more suitable for nonvolatile memory operation while thinner HfOx layer has potential for application in neuromorphic computing system.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133291974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/SNW.2019.8782926
Jeesoo Chang, M. Oh, Byung-Gook Park
An evolutionary searching method for compact model parameter extraction is proposed. Optimum scale factor (SF) and crossover probability (CP) of the algorithm corresponded with the given task are investigated. The proposed method exhibits stable convergence behavior and superior accuracy compare to conventional methods.
{"title":"A systematic model parameter extraction using differential evolution searching","authors":"Jeesoo Chang, M. Oh, Byung-Gook Park","doi":"10.23919/SNW.2019.8782926","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782926","url":null,"abstract":"An evolutionary searching method for compact model parameter extraction is proposed. Optimum scale factor (SF) and crossover probability (CP) of the algorithm corresponded with the given task are investigated. The proposed method exhibits stable convergence behavior and superior accuracy compare to conventional methods.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132427898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/SNW.2019.8782964
Harshit Kansal, A. Medury
Using TCAD simulations, we have identified the existence of a sub-surface conducting region, below the Si/SiO2 interface, with significant electron concentration, in short channel bulk MOSFETs (p-type silicon substrate), at high accumulation bias. This is symptomatic of weakening gate control. The electron concentration in this sub-surface region is shown to be dependent on oxide thickness, channel length and source-drain junction depth. In the case of short channel nanoscale Double Gate SOI (DGSOI) MOSFETs, studied for different SOI channel thicknesses, despite quantum confinement effects, the electron concentration is found to be considerably reduced at lower SOI channel thicknesses, compared to Bulk MOSFETs.
{"title":"Short-Channel Effects and Sub-Surface Behavior in Bulk MOSFETs and Nanoscale DG-SOI- MOSFETs: A TCAD Investigation","authors":"Harshit Kansal, A. Medury","doi":"10.23919/SNW.2019.8782964","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782964","url":null,"abstract":"Using TCAD simulations, we have identified the existence of a sub-surface conducting region, below the Si/SiO2 interface, with significant electron concentration, in short channel bulk MOSFETs (p-type silicon substrate), at high accumulation bias. This is symptomatic of weakening gate control. The electron concentration in this sub-surface region is shown to be dependent on oxide thickness, channel length and source-drain junction depth. In the case of short channel nanoscale Double Gate SOI (DGSOI) MOSFETs, studied for different SOI channel thicknesses, despite quantum confinement effects, the electron concentration is found to be considerably reduced at lower SOI channel thicknesses, compared to Bulk MOSFETs.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125228273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/SNW.2019.8782949
M. Ueno, T. Oya
In this paper, we proposed a new single-electron (SE) circuit that can learn after being fabricated. We designed it whose result changes with the number of signals arriving at the output. To design it, we designed an SE flip flop circuit and an SE switch circuit to control signal propagation. The circuit can be used as a learning circuit. We performed character recognition as operation test of the proposed circuit. The results show that our SE neural network using a learning circuit can simultaneously learn multiple types of input patterns.
{"title":"Design of learning circuit for single-electron neural networks","authors":"M. Ueno, T. Oya","doi":"10.23919/SNW.2019.8782949","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782949","url":null,"abstract":"In this paper, we proposed a new single-electron (SE) circuit that can learn after being fabricated. We designed it whose result changes with the number of signals arriving at the output. To design it, we designed an SE flip flop circuit and an SE switch circuit to control signal propagation. The circuit can be used as a learning circuit. We performed character recognition as operation test of the proposed circuit. The results show that our SE neural network using a learning circuit can simultaneously learn multiple types of input patterns.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"07 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127284361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/SNW.2019.8782894
Pin-Jui Chen, M. Tsai, F. Hou, Yung-Chun Wu
Negative capacitance (NC) Fin field effect transistors (FinFET) were experimentally demonstrated. These devices had complete dimensions of single channel widths (WCh) from 20 nm to 1000 nm and gate lengths (LG) from 100 nm to 2000 nm. Experimental results show that WCh is smaller than 30 nm and LG > WCh, this proposed 5-nm-HZO Si NC-FinFET guarantees SS < 60 mV/decade.
{"title":"Characterization and Analysis of 5 nm-thick Hf0.5Zr0.5O2 for Negative Capacitance FinFET","authors":"Pin-Jui Chen, M. Tsai, F. Hou, Yung-Chun Wu","doi":"10.23919/SNW.2019.8782894","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782894","url":null,"abstract":"Negative capacitance (NC) Fin field effect transistors (FinFET) were experimentally demonstrated. These devices had complete dimensions of single channel widths (W<inf>Ch</inf>) from 20 nm to 1000 nm and gate lengths (L<inf>G</inf>) from 100 nm to 2000 nm. Experimental results show that W<inf>Ch</inf> is smaller than 30 nm and L<inf>G</inf> > W<inf>Ch</inf>, this proposed 5-nm-HZO Si NC-FinFET guarantees SS < 60 mV/decade.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126414487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/SNW.2019.8782969
H. Asai, W. Chang, N. Okada, K. Fukuda, T. Irisawa
We perform Technology computer-aided (TCAD) simulations for 2D material based Junctionless FET (JLFET) and investigate the effect of the fringe-field interaction between the source/drain (S/D) electrodes and the 2D channel. We find that subthreshold slope (SS) gets worse by the fringe-field interaction, and the degradation of the SS becomes serious when the work function difference becomes large. Interestingly, we also find that high drain voltage recovers the degradation of the SS.
{"title":"Subthreshold Degradation of 2D material Junctionless FETs -Impact of Fringe Field from Source/Drain Electrodes through Insulator-","authors":"H. Asai, W. Chang, N. Okada, K. Fukuda, T. Irisawa","doi":"10.23919/SNW.2019.8782969","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782969","url":null,"abstract":"We perform Technology computer-aided (TCAD) simulations for 2D material based Junctionless FET (JLFET) and investigate the effect of the fringe-field interaction between the source/drain (S/D) electrodes and the 2D channel. We find that subthreshold slope (SS) gets worse by the fringe-field interaction, and the degradation of the SS becomes serious when the work function difference becomes large. Interestingly, we also find that high drain voltage recovers the degradation of the SS.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125036803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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