Pub Date : 2019-06-01DOI: 10.23919/SNW.2019.8782960
H. Numata, N. Banno, K. Okamoto, N. Iguchi, H. Hada, M. Hashimoto, T. Sugibayashi, T. Sakamoto, M. Tada
Sputter deposited GexSe1−x films are characterized, prior to device fabrication for a selector. A Se-rich film has GeSe4/2 tetrahedral structure and higher crystallization temperature than Ge-rich films. Printed Ag-paste electrodes are used for I-V measurement and an amorphous Se-rich GexSe1−x film shows the good switching property for the selector with an on/off ratio of 4.8 × 104.
{"title":"Characterization of Chalcogenide Selectors for Crossbar Switch Used in Nonvolatile FPGA","authors":"H. Numata, N. Banno, K. Okamoto, N. Iguchi, H. Hada, M. Hashimoto, T. Sugibayashi, T. Sakamoto, M. Tada","doi":"10.23919/SNW.2019.8782960","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782960","url":null,"abstract":"Sputter deposited Ge<inf>x</inf>Se<inf>1−x</inf> films are characterized, prior to device fabrication for a selector. A Se-rich film has GeSe<inf>4/2</inf> tetrahedral structure and higher crystallization temperature than Ge-rich films. Printed Ag-paste electrodes are used for I-V measurement and an amorphous Se-rich Ge<inf>x</inf>Se<inf>1−x</inf> film shows the good switching property for the selector with an on/off ratio of 4.8 × 10<sup>4</sup>.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127520257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/SNW.2019.8782946
Y. Omura
This paper theoretically investigates how a nano-scale Si pn-junction wire offers the potential to develop rotating motion. Numerical calculation results strongly suggested that a 1-$mu$m-long Si rod should rotate with the acceleration of $sim 100mathrm{m} /mathrm{s}$2 under the green-light illumination of 1 nW/$mu m^{2}$. It is demonstrated that the rotator suits various medical test chips without any internal battery.
{"title":"Potential of Nano-scale Optical Rotor Based on a pn-Junction Wire","authors":"Y. Omura","doi":"10.23919/SNW.2019.8782946","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782946","url":null,"abstract":"This paper theoretically investigates how a nano-scale Si pn-junction wire offers the potential to develop rotating motion. Numerical calculation results strongly suggested that a 1-$mu$m-long Si rod should rotate with the acceleration of $sim 100mathrm{m} /mathrm{s}$2 under the green-light illumination of 1 nW/$mu m^{2}$. It is demonstrated that the rotator suits various medical test chips without any internal battery.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122502746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/SNW.2019.8782956
M. Tsai, Pin-Jui Chen, Po-Yang Peng, F. Hou, Yung-Chun Wu
We report 2 nm, 3nm, and 5 nm-thick $Hf_{0.5} Zr_{0.5} O_{2}$ (HZO) thin film by atomic-level characterization of negative capacitance Fin field effect transistors (NC-FinFET). GI-XRD by synchrotron radiation results reveal that HZO thin film has a clear orthorhombic(o) crystalline phase even in 2 nm-thick HZO. The proposed NC-FinFETs show sub-60 mV/decade subthreshold slope (SS) and nearly hysteresis-free behaviors, compared to baseline HfO2 FinFET.
{"title":"Atomic-level Analysis by Synchrotron Radiation and Characterization of 2 nm, 3 nm, and 5 nm-thick Hf0.5 Zr0.5 O2 Negative Capacitance FinFET","authors":"M. Tsai, Pin-Jui Chen, Po-Yang Peng, F. Hou, Yung-Chun Wu","doi":"10.23919/SNW.2019.8782956","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782956","url":null,"abstract":"We report 2 nm, 3nm, and 5 nm-thick $Hf_{0.5} Zr_{0.5} O_{2}$ (HZO) thin film by atomic-level characterization of negative capacitance Fin field effect transistors (NC-FinFET). GI-XRD by synchrotron radiation results reveal that HZO thin film has a clear orthorhombic(o) crystalline phase even in 2 nm-thick HZO. The proposed NC-FinFETs show sub-60 mV/decade subthreshold slope (SS) and nearly hysteresis-free behaviors, compared to baseline HfO2 FinFET.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132556660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/SNW.2019.8782971
G. Rzepa, F. Schanovsky, M. Karner
Despite extensive modeling efforts, not all semiconductor fabrication processes are fully understood on a physical level and phenomenological tools are used to analyze process splits. This works well for incremental improvements but has limitations when it comes to more fundamental developments. TCAD simulators, on the other hand, offer physical models and consider non-homogeneous field distributions and the effect of discrete charges. However, they are considerably more complex to use and to parametrize which can make them impractical. Therefore, the efficient gate stack simulator Comphy was presented recently which is used to extract physical defect properties. In this work, a development strategy is presented which employs this extraction methodology followed by an import of the defect parameters in a TCAD simulator. Using the same gate stack on different geometries we study the degradation and time dependent variability which increases from planar MOSFETs to FinFETs and is even worse for nanowires.
{"title":"From Gate Oxide Characterization to TCAD Predictions: Exploring Impact of Defects Across Technologies","authors":"G. Rzepa, F. Schanovsky, M. Karner","doi":"10.23919/SNW.2019.8782971","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782971","url":null,"abstract":"Despite extensive modeling efforts, not all semiconductor fabrication processes are fully understood on a physical level and phenomenological tools are used to analyze process splits. This works well for incremental improvements but has limitations when it comes to more fundamental developments. TCAD simulators, on the other hand, offer physical models and consider non-homogeneous field distributions and the effect of discrete charges. However, they are considerably more complex to use and to parametrize which can make them impractical. Therefore, the efficient gate stack simulator Comphy was presented recently which is used to extract physical defect properties. In this work, a development strategy is presented which employs this extraction methodology followed by an import of the defect parameters in a TCAD simulator. Using the same gate stack on different geometries we study the degradation and time dependent variability which increases from planar MOSFETs to FinFETs and is even worse for nanowires.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133657746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/SNW.2019.8782928
D. Elamaran, Takeo Ueta, H. Satoh, N. Hiromoto, H. Inokawa
Room temperature terahertz bolometers were characterized with various silicon-on-insulator (SOI) CMOS temperature sensors (MOSFET, pn junction diode, resistor and thermocouple) by adopting the 1-THz antenna-coupled structure and assuming 0.6 μm SOI CMOS technology. Performance estimation in terms of responsivity (Rv) showed the largest value of 6.27 kV/W for MOSFET. The smallest response time (τ) of 2.34 μs was obtained for the resistive bolometer whereas the MOSFET showed 13.8 μs. One order of magnitude smaller noise equivalent power (NEP) than that of the resistive bolometer was estimated for the MOSFET. Current results suggest that the n-channel MOSFET bolometer can be a promising terahertz detector integrable with SOI technology.
采用1-THz天线耦合结构，采用0.6 μm SOI CMOS技术，采用多种绝缘体上硅(SOI) CMOS温度传感器(MOSFET、pn结二极管、电阻和热电偶)对室温太赫兹热辐射计进行表征。根据响应度(Rv)的性能估计，MOSFET的最大值为6.27 kV/W。电阻式测热计的响应时间τ最小，为2.34 μs，而MOSFET的响应时间τ最小，为13.8 μs。估计该MOSFET的噪声等效功率(NEP)比电阻式测热计小一个数量级。目前的研究结果表明，n沟道MOSFET热辐射计可以与SOI技术集成，是一种很有前途的太赫兹探测器。
{"title":"Comparative Study on 1-THz Antenna-Coupled Bolometer with Various SOI-CMOS based Temperature Sensors: MOSFET, Diode, Resistor and Thermocouple","authors":"D. Elamaran, Takeo Ueta, H. Satoh, N. Hiromoto, H. Inokawa","doi":"10.23919/SNW.2019.8782928","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782928","url":null,"abstract":"Room temperature terahertz bolometers were characterized with various silicon-on-insulator (SOI) CMOS temperature sensors (MOSFET, pn junction diode, resistor and thermocouple) by adopting the 1-THz antenna-coupled structure and assuming 0.6 μm SOI CMOS technology. Performance estimation in terms of responsivity (Rv) showed the largest value of 6.27 kV/W for MOSFET. The smallest response time (τ) of 2.34 μs was obtained for the resistive bolometer whereas the MOSFET showed 13.8 μs. One order of magnitude smaller noise equivalent power (NEP) than that of the resistive bolometer was estimated for the MOSFET. Current results suggest that the n-channel MOSFET bolometer can be a promising terahertz detector integrable with SOI technology.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122953368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/SNW.2019.8782927
Minsoo Kim, Hyungcheol Shin
In this work, we predicted the characteristics of 3D NAND Flash for lateral and vertical scaling by using simulation tools such as TCAD and SPICE. We fitted our SPICE models to TCAD results, and then we developed a model which predicts the on-current $(mathrm{I}_{on})$, threshold voltage $(mathrm{V}_{mathrm{th}})$, and subthreshold swing (S.S.) with according to lateral scaling. We also analyzed the program efficiency with scaling the thickness of tunneling oxide by using SPICE. Finally, we predicted Ion with increasing number of word-line layers.
{"title":"Prediction of Characteristics of Future Scaled 3D NAND Flash Memory by Using TCAD and SPICE","authors":"Minsoo Kim, Hyungcheol Shin","doi":"10.23919/SNW.2019.8782927","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782927","url":null,"abstract":"In this work, we predicted the characteristics of 3D NAND Flash for lateral and vertical scaling by using simulation tools such as TCAD and SPICE. We fitted our SPICE models to TCAD results, and then we developed a model which predicts the on-current $(mathrm{I}_{on})$, threshold voltage $(mathrm{V}_{mathrm{th}})$, and subthreshold swing (S.S.) with according to lateral scaling. We also analyzed the program efficiency with scaling the thickness of tunneling oxide by using SPICE. Finally, we predicted Ion with increasing number of word-line layers.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123821550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/SNW.2019.8782961
Risa Kaide, T. Oya
In this study, we designed a thermal-noise-harnessing single-electron memory (SEM) pair circuit. The SEM consists of a capacitor and two tunnel junctions in series. Originally, the SEM shows hysteresis operation, i.e., it can be assumed to have two stable states. The SEM pair circuit has two SEMs and they are connected with a coupling capacitor, we designed. We found that this pair circuit shows four stable states under the condition of T=0[K]. Moreover, it changes the stable states from four to two under the thermal noise condition. Surprisingly, this new two state can be used for binary information processing. As one of its application, we here designed the full adder. Our full adder can be constructed only one SEM pair circuit. By computer simulations, we confirmed they showed correct operation. These results mean the pair circuit can operate under the thermal noise condition, and be used as useful and functional nanodevice with simple structure.
{"title":"Thermal-Noise-Harnessing Single-Electron Memory Pair Circuit and its Application to Full Adder Circuit With Simple Structure","authors":"Risa Kaide, T. Oya","doi":"10.23919/SNW.2019.8782961","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782961","url":null,"abstract":"In this study, we designed a thermal-noise-harnessing single-electron memory (SEM) pair circuit. The SEM consists of a capacitor and two tunnel junctions in series. Originally, the SEM shows hysteresis operation, i.e., it can be assumed to have two stable states. The SEM pair circuit has two SEMs and they are connected with a coupling capacitor, we designed. We found that this pair circuit shows four stable states under the condition of T=0[K]. Moreover, it changes the stable states from four to two under the thermal noise condition. Surprisingly, this new two state can be used for binary information processing. As one of its application, we here designed the full adder. Our full adder can be constructed only one SEM pair circuit. By computer simulations, we confirmed they showed correct operation. These results mean the pair circuit can operate under the thermal noise condition, and be used as useful and functional nanodevice with simple structure.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":" 62","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120829649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/SNW.2019.8782944
Fabio Ansaloni, C. Volk, A. Chatterjee, F. Kuemmeth
Spins in gate-defined silicon quantum dots are at the forefront of solid-state qubit research. We characterize top-gated devices fabricated from Si/SiGe heterostructures, demonstrating the formation of stable double and triple quantum dots with proximal charge-sensing dots. We also demonstrate fabrication of linear dot arrays with overlapping gate technology, thereby significantly increasing the density of control electrodes relative to our single-gate-layer devices.
{"title":"Characterization of top-gated Si/SiGe devices for spin qubit applications","authors":"Fabio Ansaloni, C. Volk, A. Chatterjee, F. Kuemmeth","doi":"10.23919/SNW.2019.8782944","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782944","url":null,"abstract":"Spins in gate-defined silicon quantum dots are at the forefront of solid-state qubit research. We characterize top-gated devices fabricated from Si/SiGe heterostructures, demonstrating the formation of stable double and triple quantum dots with proximal charge-sensing dots. We also demonstrate fabrication of linear dot arrays with overlapping gate technology, thereby significantly increasing the density of control electrodes relative to our single-gate-layer devices.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127539837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/snw.2019.8782931
Yuanlin Li, A. Tsurumaki‐Fukuchi, M. Arita, T. Morie, Yasuo Takahashi
Multilevel switching (MS) behaviors in Ta2O5-based resistive random-access-memory (ReRAM) have been drawing attentions as hardware artificial synapse. However, operating resistances, which decide the power consumption of whole system, are relatively low for future integration. In this work, we investigated the characteristics of two kinds of ReRAMs operating with different mechanisms; Cu-top-electrode and Ta-top-electrode Ta2O5-based ReRAMs. By taking account of resistance of high resistive state (HRS), we clarify the difference of MS characteristics between the two kinds of ReRAM devices.
{"title":"Switching Current of Ta2O5-Based Resistive Analog Memories","authors":"Yuanlin Li, A. Tsurumaki‐Fukuchi, M. Arita, T. Morie, Yasuo Takahashi","doi":"10.23919/snw.2019.8782931","DOIUrl":"https://doi.org/10.23919/snw.2019.8782931","url":null,"abstract":"Multilevel switching (MS) behaviors in Ta2O5-based resistive random-access-memory (ReRAM) have been drawing attentions as hardware artificial synapse. However, operating resistances, which decide the power consumption of whole system, are relatively low for future integration. In this work, we investigated the characteristics of two kinds of ReRAMs operating with different mechanisms; Cu-top-electrode and Ta-top-electrode Ta2O5-based ReRAMs. By taking account of resistance of high resistive state (HRS), we clarify the difference of MS characteristics between the two kinds of ReRAM devices.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116888758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, TiN/TiOx/HfO2/Pt resistive random access memory (RRAM) devices with different TiOx film thickness were fabricated. The distributions of cycle-to-cycle and device-to-device showed that the RRAM devices with thick TiOx film performed high ratio and small switching voltage. Besides, the RRAM device with thick TiOx film under pulse measurement shows as fast as 20ns pulse width and can be cycled for 1e6 cy.
{"title":"Effect of TiOx Film Thickness on Resistive Switching Behavior of TiN/TiOx/HfO2/Pt RRAM Device","authors":"Xiangxiang Ding, Lifeng Liu, Yulin Feng, Peng Huang","doi":"10.23919/SNW.2019.8782976","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782976","url":null,"abstract":"In this work, TiN/TiO<inf>x</inf>/HfO<inf>2</inf>/Pt resistive random access memory (RRAM) devices with different TiO<inf>x</inf> film thickness were fabricated. The distributions of cycle-to-cycle and device-to-device showed that the RRAM devices with thick TiO<inf>x</inf> film performed high ratio and small switching voltage. Besides, the RRAM device with thick TiO<inf>x</inf> film under pulse measurement shows as fast as 20ns pulse width and can be cycled for 1e6 cy.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128189784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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