Pub Date : 2019-06-01DOI: 10.23919/SNW.2019.8782974
You-Tai Chang, Pei-Wen Li, Horng-Chih Lin
Four-level random-telegraph-noise (RTN) characteristics of a gate-all-around (GAA) poly-Si junctionless (JL) nanowire (NW) transistor induced by two discrete traps are studied in this work. By carefully analyzing the RTN, depths of the two traps in the gate oxide can be identified separately. Consistent information is obtained by assessing the probability of transitions between different levels.
{"title":"Characterization of Four-Level Random Telegraph Noise in a Gate-All-Around Poly-Si Nanowire Transistor","authors":"You-Tai Chang, Pei-Wen Li, Horng-Chih Lin","doi":"10.23919/SNW.2019.8782974","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782974","url":null,"abstract":"Four-level random-telegraph-noise (RTN) characteristics of a gate-all-around (GAA) poly-Si junctionless (JL) nanowire (NW) transistor induced by two discrete traps are studied in this work. By carefully analyzing the RTN, depths of the two traps in the gate oxide can be identified separately. Consistent information is obtained by assessing the probability of transitions between different levels.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127812306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/SNW.2019.8782948
T. Fukai, Toshitake Asabuki
The brain identifies potentially salient features within continuous information streams, but the underlying mechanisms are poorly understood. I will show two biologically inspired neural network models that perform such analyses. The seemingly different models suggest a common principle, which we term self-consistent mismatch detection, for temporal feature analyses. A network of two-compartment neuron model implementing this principle conducts a surprisingly wide variety of temporal feature analysis. The model is also potentially useful in neural engineering.
{"title":"Temporal feature analysis in brain-inspired neural systems","authors":"T. Fukai, Toshitake Asabuki","doi":"10.23919/SNW.2019.8782948","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782948","url":null,"abstract":"The brain identifies potentially salient features within continuous information streams, but the underlying mechanisms are poorly understood. I will show two biologically inspired neural network models that perform such analyses. The seemingly different models suggest a common principle, which we term self-consistent mismatch detection, for temporal feature analyses. A network of two-compartment neuron model implementing this principle conducts a surprisingly wide variety of temporal feature analysis. The model is also potentially useful in neural engineering.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133014784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/SNW.2019.8782947
Changbeom Woo, Shinkeun Kim, Jaeyeol Park, Hyungcheol Shin
In this paper, we analyzed lateral migration (LM) mechanism of V-NAND occurring during retention operation depending on scaling of geometric parameters using TCAD simulation. Modeling for LM was performed and the behavior of time-constant (τ) parameter used for modeling was analyzed. In addition, we analyzed retention characteristics according to the states of neighbor word line (WLNei.). Comparing the extracted τ for different patterns, checker-board pattern (C/P) has the smallest τ, followed by NPN and solid pattern (S/P).
{"title":"Effect of Device Scaling on Lateral Migration Mechanism of Electrons in V-NAND","authors":"Changbeom Woo, Shinkeun Kim, Jaeyeol Park, Hyungcheol Shin","doi":"10.23919/SNW.2019.8782947","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782947","url":null,"abstract":"In this paper, we analyzed lateral migration (LM) mechanism of V-NAND occurring during retention operation depending on scaling of geometric parameters using TCAD simulation. Modeling for LM was performed and the behavior of time-constant (τ) parameter used for modeling was analyzed. In addition, we analyzed retention characteristics according to the states of neighbor word line (WLNei.). Comparing the extracted τ for different patterns, checker-board pattern (C/P) has the smallest τ, followed by NPN and solid pattern (S/P).","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132134805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/SNW.2019.8782954
Hideto Yamashita, T. Oya
In this study, we propose new single-electron circuits mimicking the behavior of a fish shoal for aiming to design the single-electron information-processing circuit to which the information processing method of multi-agent systems is applied. We here use single-electron oscillator circuits as main components. The outputs from the two-dimensional arrayed single-electron oscillators shows fish-swimming-like behavior, we confirmed by computer simulation. As a next step, we designed an additional circuit that can express how fishes swim while avoiding collisions. This function is a very important factor to mimic the behavior. Then, we confirmed its operation.
{"title":"Single-Electron Information-Processing Circuit Mimicking Behavior of Fish Shoals","authors":"Hideto Yamashita, T. Oya","doi":"10.23919/SNW.2019.8782954","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782954","url":null,"abstract":"In this study, we propose new single-electron circuits mimicking the behavior of a fish shoal for aiming to design the single-electron information-processing circuit to which the information processing method of multi-agent systems is applied. We here use single-electron oscillator circuits as main components. The outputs from the two-dimensional arrayed single-electron oscillators shows fish-swimming-like behavior, we confirmed by computer simulation. As a next step, we designed an additional circuit that can express how fishes swim while avoiding collisions. This function is a very important factor to mimic the behavior. Then, we confirmed its operation.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116642456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/SNW.2019.8782937
F. Fedele, A. Chatterjee, F. Kuemmeth
We use fast gate-voltage pulses and multiplexed RF-reflectometry charge sensing to coherently manipulate and read out multiple singlet-triplet spin qubits, within a 2D array of 12 gate-defined quantum dots in GaAs. By measuring the qubits’ responses to precise timing changes of control pulses generated at room temperature, we characterize in situ the synchronization of control pulses with sub-ns resolution. These techniques are useful for calibrating the effective delay in cryogenic transmission lines for silicon quantum processors.
{"title":"Simultaneous operation of singlet-triplet qubits","authors":"F. Fedele, A. Chatterjee, F. Kuemmeth","doi":"10.23919/SNW.2019.8782937","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782937","url":null,"abstract":"We use fast gate-voltage pulses and multiplexed RF-reflectometry charge sensing to coherently manipulate and read out multiple singlet-triplet spin qubits, within a 2D array of 12 gate-defined quantum dots in GaAs. By measuring the qubits’ responses to precise timing changes of control pulses generated at room temperature, we characterize in situ the synchronization of control pulses with sub-ns resolution. These techniques are useful for calibrating the effective delay in cryogenic transmission lines for silicon quantum processors.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125959721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/SNW.2019.8782935
Min-Hwi Kim, Suhyun Bang, Tae-Hyeon Kim, Dong Keun Lee, Sungjun Kim, Seongjae Cho, Byung-Gook Park
In this work, we have confirmed that dependent reset switching phenomenon of SiNx/SiO2 RRAM is dependent on stop voltage (VSTOP) in both DC and pulse operation. In addition, it was confirmed that improved gradual resistance change can be obtained by adjusting the amplitude of the applied reset pulse. By process simulation and empirical modeling of resistance change of the device, it is confirmed that the voltage distribution can be controlled only in the reset operation, resulting in more linear and gradual resistance change phenomenon even though same reset pulse is used.
{"title":"Improved Gradual Reset Phenomenon in SiNx-based RRAM by Diode-Connected Structure","authors":"Min-Hwi Kim, Suhyun Bang, Tae-Hyeon Kim, Dong Keun Lee, Sungjun Kim, Seongjae Cho, Byung-Gook Park","doi":"10.23919/SNW.2019.8782935","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782935","url":null,"abstract":"In this work, we have confirmed that dependent reset switching phenomenon of SiNx/SiO2 RRAM is dependent on stop voltage (VSTOP) in both DC and pulse operation. In addition, it was confirmed that improved gradual resistance change can be obtained by adjusting the amplitude of the applied reset pulse. By process simulation and empirical modeling of resistance change of the device, it is confirmed that the voltage distribution can be controlled only in the reset operation, resulting in more linear and gradual resistance change phenomenon even though same reset pulse is used.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123991265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/SNW.2019.8782899
Xianle Zhang, P. Chang, G. Du, Xiaoyan Liu
In this work, impacts of remote Coulomb scattering on hole mobility in Si p-MOSFETs devices at cryogenic temperatures are investigated. The physical models including phonon, surface roughness (SR) and remote Coulomb scatterings (RCS) are verified by reproducing fairly well the experimental results for temperature ranging from 300 to 30K, which are reliably employed to predict the hole mobility down to liquid helium temperatures (4.2K). Simulation results reveal that as temperature decreases, the RCS due to Si/SiO2 interfacial trap charges plays an important role in determining hole mobility. Dependence of hole mobility on interfacial trap density is further explored at 4.2K.
{"title":"Impacts of Remote Coulomb Scattering on Hole Mobility in Si p-MOSFFETs at Cryogenic Temperatures","authors":"Xianle Zhang, P. Chang, G. Du, Xiaoyan Liu","doi":"10.23919/SNW.2019.8782899","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782899","url":null,"abstract":"In this work, impacts of remote Coulomb scattering on hole mobility in Si p-MOSFETs devices at cryogenic temperatures are investigated. The physical models including phonon, surface roughness (SR) and remote Coulomb scatterings (RCS) are verified by reproducing fairly well the experimental results for temperature ranging from 300 to 30K, which are reliably employed to predict the hole mobility down to liquid helium temperatures (4.2K). Simulation results reveal that as temperature decreases, the RCS due to Si/SiO2 interfacial trap charges plays an important role in determining hole mobility. Dependence of hole mobility on interfacial trap density is further explored at 4.2K.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134047128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/SNW.2019.8782896
Liqiao Liu, Xiaoyan Liu, G. Du
This paper provided a photosensitive performance evaluation of UTBB MOSFET with different structures. The UTBB MOSFET can achieve photosensitive function by integrating a doping well or photodiode under the BOX. With doping well under the BOX, the UTBB MOSFET is more sensitive to light. On the other hand, the saturation exposure time of UTBB with photodiode is longer.
{"title":"Evaluation of Photosensitive Performance of Different Structured UTBB MOSFET","authors":"Liqiao Liu, Xiaoyan Liu, G. Du","doi":"10.23919/SNW.2019.8782896","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782896","url":null,"abstract":"This paper provided a photosensitive performance evaluation of UTBB MOSFET with different structures. The UTBB MOSFET can achieve photosensitive function by integrating a doping well or photodiode under the BOX. With doping well under the BOX, the UTBB MOSFET is more sensitive to light. On the other hand, the saturation exposure time of UTBB with photodiode is longer.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132438305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/SNW.2019.8782936
An Chen
Unique nanoscale material and device properties provide opportunities to achieve improved performance and efficiency, and to enable new functionalities. The focus of nanoelectronics research has shifted from low-power switches for Boolean logic to emerging materials and devices for novel computing paradigms. This paper will discuss new directions of energy-efficient nanoelectronics based on a brief review of the new research funded by the Semiconductor Research Corporation (SRC).
{"title":"Energy Efficient Nanoelectronics","authors":"An Chen","doi":"10.23919/SNW.2019.8782936","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782936","url":null,"abstract":"Unique nanoscale material and device properties provide opportunities to achieve improved performance and efficiency, and to enable new functionalities. The focus of nanoelectronics research has shifted from low-power switches for Boolean logic to emerging materials and devices for novel computing paradigms. This paper will discuss new directions of energy-efficient nanoelectronics based on a brief review of the new research funded by the Semiconductor Research Corporation (SRC).","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132580567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/SNW.2019.8782930
Kyosuke Maeda, Kyoji Mizoguchi, K. Takeuchi
This paper proposes Less Reliable Page Error Reduction (LRPER) to achieve both high reliability and small data overhead of 3D-TLC NAND flash memories. LRPER suppresses both lateral charge migration and vertical charge de-trap without redundant reading of memory cells, thus achieving fast write. In addition, data overhead is small by adding flag bits to the highly reliable page. As a result, the data-retention lifetime increases by 5.0-times. The proposal can be implemented in the SSD controller for highly reliable 3D-NAND flash.
{"title":"Less Reliable Page Error Reduction for 3D-TLC NAND Flash Memories with Data Overhead Reduction by 40% and Data-retention Time Increase by 5.0x","authors":"Kyosuke Maeda, Kyoji Mizoguchi, K. Takeuchi","doi":"10.23919/SNW.2019.8782930","DOIUrl":"https://doi.org/10.23919/SNW.2019.8782930","url":null,"abstract":"This paper proposes Less Reliable Page Error Reduction (LRPER) to achieve both high reliability and small data overhead of 3D-TLC NAND flash memories. LRPER suppresses both lateral charge migration and vertical charge de-trap without redundant reading of memory cells, thus achieving fast write. In addition, data overhead is small by adding flag bits to the highly reliable page. As a result, the data-retention lifetime increases by 5.0-times. The proposal can be implemented in the SSD controller for highly reliable 3D-NAND flash.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"68 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116375026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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