Pub Date : 2023-06-30DOI: 10.5573/jsts.2023.23.3.176
Min-seong Kang, K. Yoon
{"title":"A Resolution Reconfigurable Hybrid ADC with Register-switching Method for Bio-signal Processing","authors":"Min-seong Kang, K. Yoon","doi":"10.5573/jsts.2023.23.3.176","DOIUrl":"https://doi.org/10.5573/jsts.2023.23.3.176","url":null,"abstract":"","PeriodicalId":17067,"journal":{"name":"Journal of Semiconductor Technology and Science","volume":"2 1","pages":""},"PeriodicalIF":0.4,"publicationDate":"2023-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79423337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-30DOI: 10.5573/jsts.2023.23.2.118
Jae-Hyuk Lee, Seunghoon Lee, Jun-Ho Boo, Jun-Sang Park, Tai-Ji An, Hee-Wook Shin, Young-Jae Cho, Michael Choi, J. Burm, G. Ahn
—This work proposes a single-channel 11-bit successive-approximation register (SAR) analog-to-digital converter (ADC) with an operating speed of 160-MS/s based on a non-binary digital-to-analog converter (DAC) for settling error correction. In the proposed DAC, a non-binary-weighted structure with redundancy is employed for the upper 8-bit capacitor array to reduce the residual voltage settling time requirement, facilitating high-speed operation. The remaining 3-bit capacitor array is composed of three unit capacitors, which are attached to the fractional reference voltages generated from a resistor string (R-string). The proposed partially monotonic switching scheme reduces the switching power consumption and the common-mode voltage variations of the DAC output voltage. The proposed 3D-encapsulated capacitor layout reduces the interference of adjacent signals while securing the high linearity of capacitors. Implemented in a 28 nm CMOS, the proposed ADC consumes 1.67 mW of power with a 1.0 V supply voltage and occupies an active area of 0.026 mm 2
本研究提出了一种基于非二进制数模转换器(DAC)的单通道11位连续逼近寄存器(SAR)模数转换器(ADC)，其工作速度为160 ms /s，用于解决纠错。在该DAC中，采用非二值加权冗余结构对上8位电容阵列进行冗余处理，减少了剩余电压的稳定时间，便于高速运行。剩余的3位电容器阵列由三个单位电容器组成，它们连接到由电阻串(r -串)产生的分数参考电压上。所提出的部分单调开关方案降低了开关功耗和DAC输出电压的共模电压变化。所提出的3d封装电容器布局减少了相邻信号的干扰，同时确保了电容器的高线性度。该ADC采用28 nm CMOS实现，在1.0 V电源电压下功耗为1.67 mW，有效面积为0.026 mm2
{"title":"An 11-bit 160-MS/s Non-binary C-based SAR ADC with a Partially Monotonic Switching Scheme","authors":"Jae-Hyuk Lee, Seunghoon Lee, Jun-Ho Boo, Jun-Sang Park, Tai-Ji An, Hee-Wook Shin, Young-Jae Cho, Michael Choi, J. Burm, G. Ahn","doi":"10.5573/jsts.2023.23.2.118","DOIUrl":"https://doi.org/10.5573/jsts.2023.23.2.118","url":null,"abstract":"—This work proposes a single-channel 11-bit successive-approximation register (SAR) analog-to-digital converter (ADC) with an operating speed of 160-MS/s based on a non-binary digital-to-analog converter (DAC) for settling error correction. In the proposed DAC, a non-binary-weighted structure with redundancy is employed for the upper 8-bit capacitor array to reduce the residual voltage settling time requirement, facilitating high-speed operation. The remaining 3-bit capacitor array is composed of three unit capacitors, which are attached to the fractional reference voltages generated from a resistor string (R-string). The proposed partially monotonic switching scheme reduces the switching power consumption and the common-mode voltage variations of the DAC output voltage. The proposed 3D-encapsulated capacitor layout reduces the interference of adjacent signals while securing the high linearity of capacitors. Implemented in a 28 nm CMOS, the proposed ADC consumes 1.67 mW of power with a 1.0 V supply voltage and occupies an active area of 0.026 mm 2","PeriodicalId":17067,"journal":{"name":"Journal of Semiconductor Technology and Science","volume":"30 1","pages":""},"PeriodicalIF":0.4,"publicationDate":"2023-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83317392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-30DOI: 10.5573/jsts.2023.23.2.138
Hyoju Seo, Hyelin Seok, Jungwon Lee, Youngsun Han, Yongtae Kim
{"title":"Design of an Approximate Adder based on Modified Full Adder and Nonzero Truncation for Machine Learning","authors":"Hyoju Seo, Hyelin Seok, Jungwon Lee, Youngsun Han, Yongtae Kim","doi":"10.5573/jsts.2023.23.2.138","DOIUrl":"https://doi.org/10.5573/jsts.2023.23.2.138","url":null,"abstract":"","PeriodicalId":17067,"journal":{"name":"Journal of Semiconductor Technology and Science","volume":"423 1","pages":""},"PeriodicalIF":0.4,"publicationDate":"2023-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78765654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-30DOI: 10.5573/jsts.2023.23.2.112
In-Young Lee, D. Im
{"title":"Low Power RF Interface of the Near-field Communications Tag IC for Sensors","authors":"In-Young Lee, D. Im","doi":"10.5573/jsts.2023.23.2.112","DOIUrl":"https://doi.org/10.5573/jsts.2023.23.2.112","url":null,"abstract":"","PeriodicalId":17067,"journal":{"name":"Journal of Semiconductor Technology and Science","volume":"1 1","pages":""},"PeriodicalIF":0.4,"publicationDate":"2023-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90988594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-30DOI: 10.5573/jsts.2023.23.2.128
Seungjik Lee, O. Lee, I. Nam
{"title":"Review of Short-circuit Protection Circuits for SiC MOSFETs","authors":"Seungjik Lee, O. Lee, I. Nam","doi":"10.5573/jsts.2023.23.2.128","DOIUrl":"https://doi.org/10.5573/jsts.2023.23.2.128","url":null,"abstract":"","PeriodicalId":17067,"journal":{"name":"Journal of Semiconductor Technology and Science","volume":"45 1","pages":""},"PeriodicalIF":0.4,"publicationDate":"2023-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75269423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-30DOI: 10.5573/jsts.2023.23.2.89
Ji-Hun Lim, Sang-Gyu Park
{"title":"A Simple Timing-skew Calibration using Flip-flops for Time-interleaved ADCs","authors":"Ji-Hun Lim, Sang-Gyu Park","doi":"10.5573/jsts.2023.23.2.89","DOIUrl":"https://doi.org/10.5573/jsts.2023.23.2.89","url":null,"abstract":"","PeriodicalId":17067,"journal":{"name":"Journal of Semiconductor Technology and Science","volume":"1 1","pages":""},"PeriodicalIF":0.4,"publicationDate":"2023-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73415785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-30DOI: 10.5573/jsts.2023.23.2.98
Won-Cheol Lee, Ho-Jun Kim, Hong-June Park
—A low-power DRAM controller ASIC is proposed for point-to-point interconnects such as deep learning applications. The termination resistance of the DRAM controller is increased to 160 Ω and infinity during the write and read modes, respectively, to reduce power consumption with no transmission errors. Short-reach interconnects of 25 mm DQ/DQS lines are used to avoid signal integrity issues. The proposed DRAM controller is implemented in a 65 nm process with an active area of 1.64 mm 2 , 16 DQ 8 Gb configuration, and a data rate of 800 Mbps per DQ pin. The DRAM interface using the proposed controller and a commercial DDR3 DRAM chip consumes 379 mW on average; this is 64% of the power with the default termination of the JEDEC standard. Derived equations for the TX and RX current of the DRAM interface reveals that the TX current of a clock signal is minimized when the time of flight of the PCB channel is integer multiples of the half period of the clock signal with large TX and RX terminations.
{"title":"A Low-power DRAM Controller ASIC with a 36% Reduction in Average Active Power by Increasing On-die Termination Resistance","authors":"Won-Cheol Lee, Ho-Jun Kim, Hong-June Park","doi":"10.5573/jsts.2023.23.2.98","DOIUrl":"https://doi.org/10.5573/jsts.2023.23.2.98","url":null,"abstract":"—A low-power DRAM controller ASIC is proposed for point-to-point interconnects such as deep learning applications. The termination resistance of the DRAM controller is increased to 160 Ω and infinity during the write and read modes, respectively, to reduce power consumption with no transmission errors. Short-reach interconnects of 25 mm DQ/DQS lines are used to avoid signal integrity issues. The proposed DRAM controller is implemented in a 65 nm process with an active area of 1.64 mm 2 , 16 DQ 8 Gb configuration, and a data rate of 800 Mbps per DQ pin. The DRAM interface using the proposed controller and a commercial DDR3 DRAM chip consumes 379 mW on average; this is 64% of the power with the default termination of the JEDEC standard. Derived equations for the TX and RX current of the DRAM interface reveals that the TX current of a clock signal is minimized when the time of flight of the PCB channel is integer multiples of the half period of the clock signal with large TX and RX terminations.","PeriodicalId":17067,"journal":{"name":"Journal of Semiconductor Technology and Science","volume":"159 1","pages":""},"PeriodicalIF":0.4,"publicationDate":"2023-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74085555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-02-28DOI: 10.5573/jsts.2023.23.1.8
G. Kang, I. Kang, Sang-Ho Lee, Jin Park, S. Min, G. Kim, J. Heo, Jaewon Jang, J. Bae, Sin‐Hyung Lee
{"title":"Electrical Performance Depending on the Grain Boundary-location in the Multiple Nanosheet Tunneling Field-effect Transistor based on the Poly-Si","authors":"G. Kang, I. Kang, Sang-Ho Lee, Jin Park, S. Min, G. Kim, J. Heo, Jaewon Jang, J. Bae, Sin‐Hyung Lee","doi":"10.5573/jsts.2023.23.1.8","DOIUrl":"https://doi.org/10.5573/jsts.2023.23.1.8","url":null,"abstract":"","PeriodicalId":17067,"journal":{"name":"Journal of Semiconductor Technology and Science","volume":"6 1","pages":""},"PeriodicalIF":0.4,"publicationDate":"2023-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85868611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-02-28DOI: 10.5573/jsts.2023.23.1.56
B. Seo, Gu Jung, Sunghun Jung, Dong-Min Seol, Sungmoon Chung, Y. Eo
{"title":"A 0.9 - 1.5 GHz CMOS UWB Radar IC for Through the Wall Human Detection","authors":"B. Seo, Gu Jung, Sunghun Jung, Dong-Min Seol, Sungmoon Chung, Y. Eo","doi":"10.5573/jsts.2023.23.1.56","DOIUrl":"https://doi.org/10.5573/jsts.2023.23.1.56","url":null,"abstract":"","PeriodicalId":17067,"journal":{"name":"Journal of Semiconductor Technology and Science","volume":"27 1","pages":""},"PeriodicalIF":0.4,"publicationDate":"2023-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85518549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-02-28DOI: 10.5573/jsts.2023.23.1.1
K. Kim, Sookyeong Kim, Ah-Hyun Hong, Yoojeong Ko, Hyowon Jang, Hyeok-Don Kim, Dong-Wook Park
{"title":"Development of Organic Thin-film Transistors on a Biocompatible Parylene-C Substrate","authors":"K. Kim, Sookyeong Kim, Ah-Hyun Hong, Yoojeong Ko, Hyowon Jang, Hyeok-Don Kim, Dong-Wook Park","doi":"10.5573/jsts.2023.23.1.1","DOIUrl":"https://doi.org/10.5573/jsts.2023.23.1.1","url":null,"abstract":"","PeriodicalId":17067,"journal":{"name":"Journal of Semiconductor Technology and Science","volume":"196 1","pages":""},"PeriodicalIF":0.4,"publicationDate":"2023-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76030346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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