Pub Date : 2000-06-24DOI: 10.1109/HKEDM.2000.904223
Jinshu Zhang, P. Tsien, Pei-yi Chen, L. Nanver, J. Slotboom
Although the performance of SiGe heterojunction bipolar transistor has been improved much with the development of epitaxy technology, the reliability is a concern for practical application due to its large mismatch. We have carried out accelerated life test on the SiGe microwave power heterojunction bipolar transistor, and found that the performance of the SiGe microwave power HBT does not change after the HBT is addressed at peak junction temperature of 200/spl deg/C for 168 hrs by forward DC bias. This clearly indicates that the SiGe HBT has the same reliability as Si bipolar transistor.
{"title":"On the reliability of SiGe microwave power heterojunction bipolar transistor","authors":"Jinshu Zhang, P. Tsien, Pei-yi Chen, L. Nanver, J. Slotboom","doi":"10.1109/HKEDM.2000.904223","DOIUrl":"https://doi.org/10.1109/HKEDM.2000.904223","url":null,"abstract":"Although the performance of SiGe heterojunction bipolar transistor has been improved much with the development of epitaxy technology, the reliability is a concern for practical application due to its large mismatch. We have carried out accelerated life test on the SiGe microwave power heterojunction bipolar transistor, and found that the performance of the SiGe microwave power HBT does not change after the HBT is addressed at peak junction temperature of 200/spl deg/C for 168 hrs by forward DC bias. This clearly indicates that the SiGe HBT has the same reliability as Si bipolar transistor.","PeriodicalId":178667,"journal":{"name":"Proceedings 2000 IEEE Hong Kong Electron Devices Meeting (Cat. No.00TH8503)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123732708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-24DOI: 10.1109/HKEDM.2000.904234
Hongxia Ren, H. Yue
Based on the hydrodynamic energy transport model, using the 2-dimensional device simulator MEDICI, the port electrical characteristics for grooved-gate PMOSFETs are studied at first, and compared with that of counterpart conventional planar PMOSFETs. Then the characteristics are explained in terms of interior physical parameters distribution.
{"title":"Study on the characteristics for deep-sub-micron grooved-gate PMOSFET","authors":"Hongxia Ren, H. Yue","doi":"10.1109/HKEDM.2000.904234","DOIUrl":"https://doi.org/10.1109/HKEDM.2000.904234","url":null,"abstract":"Based on the hydrodynamic energy transport model, using the 2-dimensional device simulator MEDICI, the port electrical characteristics for grooved-gate PMOSFETs are studied at first, and compared with that of counterpart conventional planar PMOSFETs. Then the characteristics are explained in terms of interior physical parameters distribution.","PeriodicalId":178667,"journal":{"name":"Proceedings 2000 IEEE Hong Kong Electron Devices Meeting (Cat. No.00TH8503)","volume":"153 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123091214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-24DOI: 10.1109/HKEDM.2000.904222
B. Yan, E. Yang
A self-aligned fabrication process for AlGaAs/GaAs heterojunction bipolar transistors (HBT's) is presented. The advantage of this process is that selfaligned structure and device passivation can be realized simultaneously using silicon nitride sidewall technique. The silicon nitride sidewall functions both as an isolation layer to prevent shorting between the base metal and the emitter mesa and as an etching mask to prevent AlGaAs passivation layer to be removed. A current gain cutoff frequency f/sub T/ of 30 GHz and a maximum oscillation frequency f/sub max/ of 50 GHz have been obtained from the device with 3 /spl mu/m/spl times/15 /spl mu/m emitter size.
{"title":"A self-aligned structure AlGaAs/GaAs HBT's using silicon nitride sidewall technique","authors":"B. Yan, E. Yang","doi":"10.1109/HKEDM.2000.904222","DOIUrl":"https://doi.org/10.1109/HKEDM.2000.904222","url":null,"abstract":"A self-aligned fabrication process for AlGaAs/GaAs heterojunction bipolar transistors (HBT's) is presented. The advantage of this process is that selfaligned structure and device passivation can be realized simultaneously using silicon nitride sidewall technique. The silicon nitride sidewall functions both as an isolation layer to prevent shorting between the base metal and the emitter mesa and as an etching mask to prevent AlGaAs passivation layer to be removed. A current gain cutoff frequency f/sub T/ of 30 GHz and a maximum oscillation frequency f/sub max/ of 50 GHz have been obtained from the device with 3 /spl mu/m/spl times/15 /spl mu/m emitter size.","PeriodicalId":178667,"journal":{"name":"Proceedings 2000 IEEE Hong Kong Electron Devices Meeting (Cat. No.00TH8503)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131875846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-24DOI: 10.1109/HKEDM.2000.904212
C. Chen, C. Chang, J. Chou, C. Huang, K. Lin, Yao-Chin Cheng, Chih-Yung Lin
Excellent PMOS short channel effect is achieved by using high energy, large tilt angle arsenic implant as P-Halo. For the first time, it was found that the tail profile of P-Halo implant through the polysilicon gate, therefore, the channel concentration is modulated not only laterally from gate edge but also vertically from top of the polysilicon gate and it resulted in very flat short channel behavior. The effect of arsenic P-Halo implant was comprehensively studied and well characterized to explain this specific phenomenon. The gate oxide integrity was examined by Q/sub BD/ and it passed the lifetime of 10 years at different conditions of P-Halo implants. Excellent performance of 0.12 um PMOSFET is also demonstrated in this work.
利用高能、大倾角砷植入物作为P-Halo，获得了优异的PMOS短通道效应。首次发现了P-Halo植入体通过多晶硅栅极的尾部轮廓，因此，沟道浓度不仅从栅极边缘横向调制，而且从多晶硅栅极顶部垂直调制，导致了非常平坦的短沟道行为。对砷磷晕种植体的作用进行了全面的研究和表征，以解释这一特殊现象。采用Q/sub - BD/测试方法对栅氧化物的完整性进行了测试，结果表明，在不同的P-Halo植入物条件下，栅氧化物的寿命均超过了10年。本研究也证明了0.12 um PMOSFET的优异性能。
{"title":"Optimization of short channel effect by arsenic P-Halo implant through polysilicon gate for 0.12 um P-MOSFET","authors":"C. Chen, C. Chang, J. Chou, C. Huang, K. Lin, Yao-Chin Cheng, Chih-Yung Lin","doi":"10.1109/HKEDM.2000.904212","DOIUrl":"https://doi.org/10.1109/HKEDM.2000.904212","url":null,"abstract":"Excellent PMOS short channel effect is achieved by using high energy, large tilt angle arsenic implant as P-Halo. For the first time, it was found that the tail profile of P-Halo implant through the polysilicon gate, therefore, the channel concentration is modulated not only laterally from gate edge but also vertically from top of the polysilicon gate and it resulted in very flat short channel behavior. The effect of arsenic P-Halo implant was comprehensively studied and well characterized to explain this specific phenomenon. The gate oxide integrity was examined by Q/sub BD/ and it passed the lifetime of 10 years at different conditions of P-Halo implants. Excellent performance of 0.12 um PMOSFET is also demonstrated in this work.","PeriodicalId":178667,"journal":{"name":"Proceedings 2000 IEEE Hong Kong Electron Devices Meeting (Cat. No.00TH8503)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128088281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-24DOI: 10.1109/HKEDM.2000.904203
J. Kuo
This paper presents PD-SOI SPICE, which is based on compact BiCMOS charge-control models and includes second-order effects, electron and lattice temperatures, for circuit simulation of low-voltage CMOS circuits using deep-submicron partially-depleted (PD) SOI CMOS devices. This PD-SOI SPICE performs transient simulation of the write-access critical path in an SRAM composed of 42 PD SOI CMOS devices without convergence problems, which are commonly encountered while modeling PD devices due to kink effects.
PD-SOI SPICE基于紧凑的BiCMOS电荷控制模型，包含二阶效应、电子和晶格温度，可用于深亚微米部分耗尽(PD) SOI CMOS器件的低压CMOS电路仿真。该PD-SOI SPICE在由42个PD SOI CMOS器件组成的SRAM中执行写访问关键路径的瞬态仿真，而不会出现由于扭结效应而在建模PD器件时经常遇到的收敛问题。
{"title":"SPICE compact modeling of PD-SOI CMOS devices","authors":"J. Kuo","doi":"10.1109/HKEDM.2000.904203","DOIUrl":"https://doi.org/10.1109/HKEDM.2000.904203","url":null,"abstract":"This paper presents PD-SOI SPICE, which is based on compact BiCMOS charge-control models and includes second-order effects, electron and lattice temperatures, for circuit simulation of low-voltage CMOS circuits using deep-submicron partially-depleted (PD) SOI CMOS devices. This PD-SOI SPICE performs transient simulation of the write-access critical path in an SRAM composed of 42 PD SOI CMOS devices without convergence problems, which are commonly encountered while modeling PD devices due to kink effects.","PeriodicalId":178667,"journal":{"name":"Proceedings 2000 IEEE Hong Kong Electron Devices Meeting (Cat. No.00TH8503)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129112577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-24DOI: 10.1109/HKEDM.2000.904224
C. Chakraborty, P. Lai, S. Chakraborty
The electric field induced shift of ground-state and higher energy levels of two interacting electrons in a GaAs quantum dot with parabolic confinement is presented. A perturbation method is used to calculate the shift in the electronic energy levels. The results indicate a negative energy level shift for ground and a few higher levels, while the shift is positive for other level. A periodicity of positive and negative energy level shifts occurs for higher energy levels. The lowering of energy levels is also found to be more pronounced for larger dots.
{"title":"Effect of electric field on the energy levels of two interacting electrons in a quantum dot","authors":"C. Chakraborty, P. Lai, S. Chakraborty","doi":"10.1109/HKEDM.2000.904224","DOIUrl":"https://doi.org/10.1109/HKEDM.2000.904224","url":null,"abstract":"The electric field induced shift of ground-state and higher energy levels of two interacting electrons in a GaAs quantum dot with parabolic confinement is presented. A perturbation method is used to calculate the shift in the electronic energy levels. The results indicate a negative energy level shift for ground and a few higher levels, while the shift is positive for other level. A periodicity of positive and negative energy level shifts occurs for higher energy levels. The lowering of energy levels is also found to be more pronounced for larger dots.","PeriodicalId":178667,"journal":{"name":"Proceedings 2000 IEEE Hong Kong Electron Devices Meeting (Cat. No.00TH8503)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123661726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-24DOI: 10.1109/HKEDM.2000.904231
Yutao Ma, Litian Liu, L. Tian, Zhijian Li
The degree of degeneracy of a quantized inversion layer in an MOS structure is investigated by a fully quantum mechanical approach via self-consistent solution of Schrodinger and Poisson equations. The relative error of carrier sheet density induced by Boltzmann statistics is used as a measurement of the degeneracy. It is shown that the degree of degeneracy of the inversion layer is much weaker due to the quantization of carrier energy compared with the semi-classical case.
{"title":"Statistical analysis of quantized inversion layer in MOS devices with ultra-thin gate oxide and high substrate doping levels","authors":"Yutao Ma, Litian Liu, L. Tian, Zhijian Li","doi":"10.1109/HKEDM.2000.904231","DOIUrl":"https://doi.org/10.1109/HKEDM.2000.904231","url":null,"abstract":"The degree of degeneracy of a quantized inversion layer in an MOS structure is investigated by a fully quantum mechanical approach via self-consistent solution of Schrodinger and Poisson equations. The relative error of carrier sheet density induced by Boltzmann statistics is used as a measurement of the degeneracy. It is shown that the degree of degeneracy of the inversion layer is much weaker due to the quantization of carrier energy compared with the semi-classical case.","PeriodicalId":178667,"journal":{"name":"Proceedings 2000 IEEE Hong Kong Electron Devices Meeting (Cat. No.00TH8503)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114813555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-24DOI: 10.1109/HKEDM.2000.904218
Zhikuan Zhang, Hongmei Wang, M. Chan, S. Jagar, M. Poon, M. Qin, Yangyuan Wang
The effects of grain boundaries on the performance of super TFTs formed by MILC are studied. The existence of grain boundaries in the channel region will cause subthreshold hump, early punchthrough or device degradation, depending on the direction of the grain boundaries. The probability for the channel region of a TFT to cover multiple grains decrease significantly when the device is scaled down, thus resulting in better device performance and higher uniformity. A novel method to measure the grain dimension by using boundaries oxide as a etching mask has also been developed.
{"title":"Effects of grain boundaries on TFTs formed by high-temperature MILC","authors":"Zhikuan Zhang, Hongmei Wang, M. Chan, S. Jagar, M. Poon, M. Qin, Yangyuan Wang","doi":"10.1109/HKEDM.2000.904218","DOIUrl":"https://doi.org/10.1109/HKEDM.2000.904218","url":null,"abstract":"The effects of grain boundaries on the performance of super TFTs formed by MILC are studied. The existence of grain boundaries in the channel region will cause subthreshold hump, early punchthrough or device degradation, depending on the direction of the grain boundaries. The probability for the channel region of a TFT to cover multiple grains decrease significantly when the device is scaled down, thus resulting in better device performance and higher uniformity. A novel method to measure the grain dimension by using boundaries oxide as a etching mask has also been developed.","PeriodicalId":178667,"journal":{"name":"Proceedings 2000 IEEE Hong Kong Electron Devices Meeting (Cat. No.00TH8503)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128319718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-24DOI: 10.1109/HKEDM.2000.904216
Chang-Soon Choi, Kyung-Whan Kim, W. Choi
A new Self-Aligned Asymmetric Structure (SAAS) which has asymmetric halo at the highly doped source extension is proposed and optimized for sub-0.1 /spl mu/m MOSFET technology. The fabrication process for the asymmetric structure requires no additional masks. The hydrodynamic device simulation coupled with process simulation shows that the highly doped asymmetric halo enhances the velocity overshoot at the source side and suppresses the short channel effects. The degradation of device performance caused by increased resistance in the highly doped halo is reduced by the asymmetric drain structure with low parasitic resistance.
{"title":"A new Self-Aligned Asymmetric Structure (SAAS) for 0.1 /spl mu/m MOSFET technology","authors":"Chang-Soon Choi, Kyung-Whan Kim, W. Choi","doi":"10.1109/HKEDM.2000.904216","DOIUrl":"https://doi.org/10.1109/HKEDM.2000.904216","url":null,"abstract":"A new Self-Aligned Asymmetric Structure (SAAS) which has asymmetric halo at the highly doped source extension is proposed and optimized for sub-0.1 /spl mu/m MOSFET technology. The fabrication process for the asymmetric structure requires no additional masks. The hydrodynamic device simulation coupled with process simulation shows that the highly doped asymmetric halo enhances the velocity overshoot at the source side and suppresses the short channel effects. The degradation of device performance caused by increased resistance in the highly doped halo is reduced by the asymmetric drain structure with low parasitic resistance.","PeriodicalId":178667,"journal":{"name":"Proceedings 2000 IEEE Hong Kong Electron Devices Meeting (Cat. No.00TH8503)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130685790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-24DOI: 10.1109/HKEDM.2000.904227
S. Chakraborty, P. Lai, C. Chan, Y. Cheng
The electrical properties of dry-oxidized, N/sub 2/O-annealed n-type 6H-SiC metal-oxide-semiconductor (MOS) capacitors are investigated at room temperature. As compared to conventional dry-oxidized device, although the N/sub 2/O-annealed device has higher oxide-charge density, it shows smaller increase in interface-state density under high-field stress. On the other hand, the stress measurements indicate that dry-oxidized device has fewer pre-existing acceptor-type interface states and oxide traps. In summary, N/sub 2/O nitridation improves the hardness of SiO/sub 2//n-type SiC interface and the oxide quality under high-field stress.
{"title":"Interface properties of N/sub 2/O-annealed SiO/sub 2//SiC system","authors":"S. Chakraborty, P. Lai, C. Chan, Y. Cheng","doi":"10.1109/HKEDM.2000.904227","DOIUrl":"https://doi.org/10.1109/HKEDM.2000.904227","url":null,"abstract":"The electrical properties of dry-oxidized, N/sub 2/O-annealed n-type 6H-SiC metal-oxide-semiconductor (MOS) capacitors are investigated at room temperature. As compared to conventional dry-oxidized device, although the N/sub 2/O-annealed device has higher oxide-charge density, it shows smaller increase in interface-state density under high-field stress. On the other hand, the stress measurements indicate that dry-oxidized device has fewer pre-existing acceptor-type interface states and oxide traps. In summary, N/sub 2/O nitridation improves the hardness of SiO/sub 2//n-type SiC interface and the oxide quality under high-field stress.","PeriodicalId":178667,"journal":{"name":"Proceedings 2000 IEEE Hong Kong Electron Devices Meeting (Cat. No.00TH8503)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122404859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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