Pub Date : 2000-06-24DOI: 10.1109/HKEDM.2000.904205
Xinnan Lin, M. Chan, Hongmei Wang
An opposite side floating gate SOI FLASH memory cell has been proposed for advanced device scaling. The new structure has the read gate and floating gate on the opposite sides of the active silicon film. It allows the use of a thick tunneling oxide to prevent charge leakage and a thin gate oxide for device scaling. The functionality of the device is demonstrated through the analysis of threshold voltage shift before and after programming. The effects of various parameters such as front and back gate oxide thickness, silicon film thickness and channel doping on device performance have been studied and a possible way to fabricate the device is proposed.
{"title":"Opposite side floating gate SOI FLASH memory cell","authors":"Xinnan Lin, M. Chan, Hongmei Wang","doi":"10.1109/HKEDM.2000.904205","DOIUrl":"https://doi.org/10.1109/HKEDM.2000.904205","url":null,"abstract":"An opposite side floating gate SOI FLASH memory cell has been proposed for advanced device scaling. The new structure has the read gate and floating gate on the opposite sides of the active silicon film. It allows the use of a thick tunneling oxide to prevent charge leakage and a thin gate oxide for device scaling. The functionality of the device is demonstrated through the analysis of threshold voltage shift before and after programming. The effects of various parameters such as front and back gate oxide thickness, silicon film thickness and channel doping on device performance have been studied and a possible way to fabricate the device is proposed.","PeriodicalId":178667,"journal":{"name":"Proceedings 2000 IEEE Hong Kong Electron Devices Meeting (Cat. No.00TH8503)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126733771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-24DOI: 10.1109/HKEDM.2000.904210
Kyung-Whan Kim, Chang-Soon Choi, W. Choi
A new self-aligned ESD (Elevated Source Drain) MOSFET structure which can effectively reduce the GIDL (Gate-Induced Drain Leakage) current is proposed and analyzed. Proposed ESD structure is characterized by sidewall spacer width (W/sub S/) and recessed-channel depth (X/sub R/) which are determined by dry-etching process. Elevation of the Source/Drain extension region is realized so that the low-activation effect caused by low-energy ion implantation can be avoided. The GIDL current in the proposed ESD structure is reduced as the region with the peak electric field is shifted toward the drain side.
{"title":"Analysis of a novel Elevated Source Drain MOSFET with reduced Gate-Induced Drain-Leakage current","authors":"Kyung-Whan Kim, Chang-Soon Choi, W. Choi","doi":"10.1109/HKEDM.2000.904210","DOIUrl":"https://doi.org/10.1109/HKEDM.2000.904210","url":null,"abstract":"A new self-aligned ESD (Elevated Source Drain) MOSFET structure which can effectively reduce the GIDL (Gate-Induced Drain Leakage) current is proposed and analyzed. Proposed ESD structure is characterized by sidewall spacer width (W/sub S/) and recessed-channel depth (X/sub R/) which are determined by dry-etching process. Elevation of the Source/Drain extension region is realized so that the low-activation effect caused by low-energy ion implantation can be avoided. The GIDL current in the proposed ESD structure is reduced as the region with the peak electric field is shifted toward the drain side.","PeriodicalId":178667,"journal":{"name":"Proceedings 2000 IEEE Hong Kong Electron Devices Meeting (Cat. No.00TH8503)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132272166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-24DOI: 10.1109/HKEDM.2000.904228
J. Wen, J. Evans-Freeman, A. Peaker, J.P. Zhang, P. Hemment, C. Marsh, G. Booker
The role of oxygen concentration on the formation/evolution of residual defects in implanted and rapid thermal annealed silicon was studied in samples with various oxygen concentrations. Photoluminescence (PL) study showed a strong correlation between the D-line intensity and the oxygen concentration. Transmission electron microscopy (TEM) measurements also suggested the extended defects were more favored in the high oxygen sample. High frequency capacitance-voltage (C-V) measurements revealed excess acceptors that were further investigated by deep level transient spectroscopy (DLTS). A hole trap with activation energy of 450 meV was detected and was suggested to relate to agglomerations of point defects associated with more than one type of 3D-metal related deep levels.
{"title":"Role of oxygen on the implantation related residual defects in silicon","authors":"J. Wen, J. Evans-Freeman, A. Peaker, J.P. Zhang, P. Hemment, C. Marsh, G. Booker","doi":"10.1109/HKEDM.2000.904228","DOIUrl":"https://doi.org/10.1109/HKEDM.2000.904228","url":null,"abstract":"The role of oxygen concentration on the formation/evolution of residual defects in implanted and rapid thermal annealed silicon was studied in samples with various oxygen concentrations. Photoluminescence (PL) study showed a strong correlation between the D-line intensity and the oxygen concentration. Transmission electron microscopy (TEM) measurements also suggested the extended defects were more favored in the high oxygen sample. High frequency capacitance-voltage (C-V) measurements revealed excess acceptors that were further investigated by deep level transient spectroscopy (DLTS). A hole trap with activation energy of 450 meV was detected and was suggested to relate to agglomerations of point defects associated with more than one type of 3D-metal related deep levels.","PeriodicalId":178667,"journal":{"name":"Proceedings 2000 IEEE Hong Kong Electron Devices Meeting (Cat. No.00TH8503)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122048666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-24DOI: 10.1109/HKEDM.2000.904221
C. Chakraborty, P. Lai
An attempt is made to investigate theoretically the effect of electric and magnetic fields on an n-GaAs semiconductor quantum box. The magnitude of energy shift due to the electric or magnetic field increases with the field strength. The shift is also more pronounced for larger box dimensions.
{"title":"Effects of electric and magnetic fields on electrons in a GaAs quantum box","authors":"C. Chakraborty, P. Lai","doi":"10.1109/HKEDM.2000.904221","DOIUrl":"https://doi.org/10.1109/HKEDM.2000.904221","url":null,"abstract":"An attempt is made to investigate theoretically the effect of electric and magnetic fields on an n-GaAs semiconductor quantum box. The magnitude of energy shift due to the electric or magnetic field increases with the field strength. The shift is also more pronounced for larger box dimensions.","PeriodicalId":178667,"journal":{"name":"Proceedings 2000 IEEE Hong Kong Electron Devices Meeting (Cat. No.00TH8503)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117123868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-24DOI: 10.1109/HKEDM.2000.904211
Jionguang Su, S. Wong, C. Chang, K. Chiu, T. Huang, C.-T. Ou, Chi-Hung Kao, Chuan-Jane Chao
The stability issues of CMOS devices for RF applications were studied. The stability factor of MOS devices based on the small-signal model (SSM) parameters was derived, for the first time. The results reveal some new insights on the effects of biasing, and scaling parameters on the stability; and were subsequently confirmed by our experimental results. Our results also show that unconditional stability of RF CMOS devices can be obtained with proper biasing and device geometries. Finally, the effects of temperature on stability were also investigated. Our results suggest that careful attention needs to be paid for stable low temperature operation.
{"title":"New insights on RF CMOS stability related to bias, scaling, and temperature","authors":"Jionguang Su, S. Wong, C. Chang, K. Chiu, T. Huang, C.-T. Ou, Chi-Hung Kao, Chuan-Jane Chao","doi":"10.1109/HKEDM.2000.904211","DOIUrl":"https://doi.org/10.1109/HKEDM.2000.904211","url":null,"abstract":"The stability issues of CMOS devices for RF applications were studied. The stability factor of MOS devices based on the small-signal model (SSM) parameters was derived, for the first time. The results reveal some new insights on the effects of biasing, and scaling parameters on the stability; and were subsequently confirmed by our experimental results. Our results also show that unconditional stability of RF CMOS devices can be obtained with proper biasing and device geometries. Finally, the effects of temperature on stability were also investigated. Our results suggest that careful attention needs to be paid for stable low temperature operation.","PeriodicalId":178667,"journal":{"name":"Proceedings 2000 IEEE Hong Kong Electron Devices Meeting (Cat. No.00TH8503)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128453804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-24DOI: 10.1109/HKEDM.2000.904235
Min Zhang, A. Courtay, Zhi-lian Yang
In this paper an improvement made to the behavioral IGBT model available in the Saber simulator is described. The saturation characteristics have been improved and a characterization tool in order to increase the model ease of use is developed. Using this tool, a 1200 V/600 A commercial IGBT (MITSUBISHI CM 600 HA-24 H) has been fully characterized. The model shows good agreement with measured results.
本文描述了对军刀模拟器中可用的行为IGBT模型的改进。为了提高模型的易用性，我们改进了饱和特性，并开发了表征工具。使用该工具，对1200 V/600 a商用IGBT (MITSUBISHI CM 600 HA-24 H)进行了全面表征。该模型与实测结果吻合较好。
{"title":"An improved behavioral IGBT model and its characterization tool","authors":"Min Zhang, A. Courtay, Zhi-lian Yang","doi":"10.1109/HKEDM.2000.904235","DOIUrl":"https://doi.org/10.1109/HKEDM.2000.904235","url":null,"abstract":"In this paper an improvement made to the behavioral IGBT model available in the Saber simulator is described. The saturation characteristics have been improved and a characterization tool in order to increase the model ease of use is developed. Using this tool, a 1200 V/600 A commercial IGBT (MITSUBISHI CM 600 HA-24 H) has been fully characterized. The model shows good agreement with measured results.","PeriodicalId":178667,"journal":{"name":"Proceedings 2000 IEEE Hong Kong Electron Devices Meeting (Cat. No.00TH8503)","volume":"22 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127565782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-24DOI: 10.1109/HKEDM.2000.904226
A. Khoueir, Z. Lu, W. Ng, S. Tay, P. Lait
The continuous scale down of devices to smaller feature sizes in order to maximize integration density demands a decrease in the thickness of the gate dielectric in advanced complementary metal-oxide-semiconductor (CMOS) devices. Once the thickness of the SiO/sub 2/ is reduced below about 3 nm, the regime of direct tunneling becomes predominant resulting in large leakage current. When the thickness of SiO/sub 2/ is reduced below 2 nm, the reliability of the gate oxide becomes a major problem where alternative gate dielectrics must be considered. In this work, using a novel method via direct nitridation in N/sub 2/, two different processing approaches were undergone to produce rapid thermal processing (RTP) nitrided oxides or oxynitrides. One approach is the direct nitridation of the Si surface with N/sub 2/ gas at an elevated temperature (>1150/spl deg/C) to form Si/sub 3/N/sub 4/ followed by O/sub 2/ oxidation, while the second method simply involves O/sub 2/ oxidation of the Si wafer to form SiO/sub 2/ followed by N/sub 2/ nitridation. The aim of this work is to electrically characterise the ultrathin films and prove its viability as a SiO/sub 2/ substitute for future CMOS device generations.
{"title":"RTP formed oxynitride via direct nitridation in N/sub 2/","authors":"A. Khoueir, Z. Lu, W. Ng, S. Tay, P. Lait","doi":"10.1109/HKEDM.2000.904226","DOIUrl":"https://doi.org/10.1109/HKEDM.2000.904226","url":null,"abstract":"The continuous scale down of devices to smaller feature sizes in order to maximize integration density demands a decrease in the thickness of the gate dielectric in advanced complementary metal-oxide-semiconductor (CMOS) devices. Once the thickness of the SiO/sub 2/ is reduced below about 3 nm, the regime of direct tunneling becomes predominant resulting in large leakage current. When the thickness of SiO/sub 2/ is reduced below 2 nm, the reliability of the gate oxide becomes a major problem where alternative gate dielectrics must be considered. In this work, using a novel method via direct nitridation in N/sub 2/, two different processing approaches were undergone to produce rapid thermal processing (RTP) nitrided oxides or oxynitrides. One approach is the direct nitridation of the Si surface with N/sub 2/ gas at an elevated temperature (>1150/spl deg/C) to form Si/sub 3/N/sub 4/ followed by O/sub 2/ oxidation, while the second method simply involves O/sub 2/ oxidation of the Si wafer to form SiO/sub 2/ followed by N/sub 2/ nitridation. The aim of this work is to electrically characterise the ultrathin films and prove its viability as a SiO/sub 2/ substitute for future CMOS device generations.","PeriodicalId":178667,"journal":{"name":"Proceedings 2000 IEEE Hong Kong Electron Devices Meeting (Cat. No.00TH8503)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124616913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-24DOI: 10.1109/HKEDM.2000.904232
Yutao Ma, Litian Liu, L. Tian, Zhiping Yu, Zhijian Li
Quantized inversion and accumulation layers are characterized through an approximate method by solving the Schrodinger equation analytically under a triangle potential well approximation. Results are compared with a fully numerical method by self-consistent solution of Schrodinger and Poisson equations. It is shown that both carrier sheet density and surface potential can be determined by analytical solution with sufficiently high accuracy. However, the carrier distribution profile and centroid of mobile charge layer have a large deviation from the numerical results.
{"title":"Characterization of MOS structure inversion and accumulation layer by approximate solution of Schrodinger equation","authors":"Yutao Ma, Litian Liu, L. Tian, Zhiping Yu, Zhijian Li","doi":"10.1109/HKEDM.2000.904232","DOIUrl":"https://doi.org/10.1109/HKEDM.2000.904232","url":null,"abstract":"Quantized inversion and accumulation layers are characterized through an approximate method by solving the Schrodinger equation analytically under a triangle potential well approximation. Results are compared with a fully numerical method by self-consistent solution of Schrodinger and Poisson equations. It is shown that both carrier sheet density and surface potential can be determined by analytical solution with sufficiently high accuracy. However, the carrier distribution profile and centroid of mobile charge layer have a large deviation from the numerical results.","PeriodicalId":178667,"journal":{"name":"Proceedings 2000 IEEE Hong Kong Electron Devices Meeting (Cat. No.00TH8503)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127311466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-24DOI: 10.1109/HKEDM.2000.904207
Bin Li, P. Lai, C. Chan, J. Sin
The resistance-temperature (R-T) characteristics of silicon Spreading-Resistance Temperature (SRT) sensor have been investigated. Experiment results show that dimensions of the device structure, substrate doping strongly affect the maximum operating temperature, while processing conditions only have a slight effect. With appropriately small circular n/sup +/ region and high substrate doping, the SRT sensor can function at temperatures up to 400/spl deg/C at a low current of 2 mA.
{"title":"Optimization of silicon Spreading-Resistance Temperature sensor","authors":"Bin Li, P. Lai, C. Chan, J. Sin","doi":"10.1109/HKEDM.2000.904207","DOIUrl":"https://doi.org/10.1109/HKEDM.2000.904207","url":null,"abstract":"The resistance-temperature (R-T) characteristics of silicon Spreading-Resistance Temperature (SRT) sensor have been investigated. Experiment results show that dimensions of the device structure, substrate doping strongly affect the maximum operating temperature, while processing conditions only have a slight effect. With appropriately small circular n/sup +/ region and high substrate doping, the SRT sensor can function at temperatures up to 400/spl deg/C at a low current of 2 mA.","PeriodicalId":178667,"journal":{"name":"Proceedings 2000 IEEE Hong Kong Electron Devices Meeting (Cat. No.00TH8503)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131853646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-24DOI: 10.1109/HKEDM.2000.904204
J. Vinson, J. Liou
Electrostatic discharges (ESD) are prevalent. These events damage sensitive electronic components causing system failures. Designers are not helpless against this event. There are ways to provide protection for these electronic devices. This paper provides an overview of the additional elements placed on the circuit to divert charge and clamp voltages. Both the protection architectures and clamps used are reviewed.
{"title":"Electrostatic discharge in semiconductor devices: overview of circuit protection techniques","authors":"J. Vinson, J. Liou","doi":"10.1109/HKEDM.2000.904204","DOIUrl":"https://doi.org/10.1109/HKEDM.2000.904204","url":null,"abstract":"Electrostatic discharges (ESD) are prevalent. These events damage sensitive electronic components causing system failures. Designers are not helpless against this event. There are ways to provide protection for these electronic devices. This paper provides an overview of the additional elements placed on the circuit to divert charge and clamp voltages. Both the protection architectures and clamps used are reviewed.","PeriodicalId":178667,"journal":{"name":"Proceedings 2000 IEEE Hong Kong Electron Devices Meeting (Cat. No.00TH8503)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123638916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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