Pub Date : 2009-03-14DOI: 10.1109/MSPCT.2009.5164211
S. K. Chatterjee, I. Chakrabarti
This paper proposes a parallel architecture for Fast Two-Step Search algorithm, which is used in sub-pixel motion estimation with reduced complexity. As frequent data access is necessary to execute the algorithm which involves interpolation, an architecture efficient in terms of the memory bandwidth is suitable for implementing the algorithm. In the present paper, an architecture based on an intelligent memory configuration has been proposed for the implementation of Fast Two-Step Search algorithm for half-pixel motion estimation. The proposed architecture is based upon nine processing elements (PEs) accompanied with the use of intelligent data arrangement and memory configuration. The proposed architecture is designed to be used as part of H.264 video coding. The architecture, which has been synthesized under Synopsys Design Vision environment, can work at a frequency up to 90 MHz while consuming a power of approximately 459 mW. The proposed architecture provides the solution for realtime low bit rate video applications.
{"title":"A high performance VLSI architecture for Fast Two-Step Search algorithm for sub-pixel motion estimation","authors":"S. K. Chatterjee, I. Chakrabarti","doi":"10.1109/MSPCT.2009.5164211","DOIUrl":"https://doi.org/10.1109/MSPCT.2009.5164211","url":null,"abstract":"This paper proposes a parallel architecture for Fast Two-Step Search algorithm, which is used in sub-pixel motion estimation with reduced complexity. As frequent data access is necessary to execute the algorithm which involves interpolation, an architecture efficient in terms of the memory bandwidth is suitable for implementing the algorithm. In the present paper, an architecture based on an intelligent memory configuration has been proposed for the implementation of Fast Two-Step Search algorithm for half-pixel motion estimation. The proposed architecture is based upon nine processing elements (PEs) accompanied with the use of intelligent data arrangement and memory configuration. The proposed architecture is designed to be used as part of H.264 video coding. The architecture, which has been synthesized under Synopsys Design Vision environment, can work at a frequency up to 90 MHz while consuming a power of approximately 459 mW. The proposed architecture provides the solution for realtime low bit rate video applications.","PeriodicalId":179541,"journal":{"name":"2009 International Multimedia, Signal Processing and Communication Technologies","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132659826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-14DOI: 10.1109/MSPCT.2009.5164202
N. Alam, A. K. Kureshi, M. Hasan, T. Arslan
Bundles of carbon nanotubes (CNT) have potential to replace on-chip copper (Cu) interconnects due to their large conductivity and current carrying capabilities. Analysis of the impact of process variations on CNT bundles relative to standard copper interconnects is important for predicting the reliability of CNT based interconnects. This paper investigates the impact of process variations on the resistance and capacitance of CNT bundle and compare it with the Cu interconnects at the 32nm technology node (year 2013). HSPICE simulation results show that CNT bundle consumes 1.5 to 2 folds smaller power and are 1.4 to 3 times faster than Cu for Intermediate and Global interconnects. However, for local interconnect Cu wire outperforms the CNT bundle. It was observed that process variation has comparable effects for CNT bundle and Cu wire except for Local interconnects.
{"title":"Performance comparison and variability analysis of CNT bundle and Cu interconnects","authors":"N. Alam, A. K. Kureshi, M. Hasan, T. Arslan","doi":"10.1109/MSPCT.2009.5164202","DOIUrl":"https://doi.org/10.1109/MSPCT.2009.5164202","url":null,"abstract":"Bundles of carbon nanotubes (CNT) have potential to replace on-chip copper (Cu) interconnects due to their large conductivity and current carrying capabilities. Analysis of the impact of process variations on CNT bundles relative to standard copper interconnects is important for predicting the reliability of CNT based interconnects. This paper investigates the impact of process variations on the resistance and capacitance of CNT bundle and compare it with the Cu interconnects at the 32nm technology node (year 2013). HSPICE simulation results show that CNT bundle consumes 1.5 to 2 folds smaller power and are 1.4 to 3 times faster than Cu for Intermediate and Global interconnects. However, for local interconnect Cu wire outperforms the CNT bundle. It was observed that process variation has comparable effects for CNT bundle and Cu wire except for Local interconnects.","PeriodicalId":179541,"journal":{"name":"2009 International Multimedia, Signal Processing and Communication Technologies","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133154336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-14DOI: 10.1109/MSPCT.2009.5164200
Abhijit R. Asati, Chandrashekhar
Array multipliers are preferred for smaller operand sizes due to their simpler VLSI implementation, in-spite of their linear time complexity. The tree multipliers have time complexity of O (log n) but are less suitable for VLSI implementation since, being less regular, they require larger total routing length, which may degrade their performance. Some hybrid architectures called ‘array of array’ multipliers have intermediate performance. These multipliers have a time complexity better than array multipliers, and therefore becomes an obvious choice for higher performance multiplier designs of moderate operand sizes. In this paper a 16×16 unsigned ‘array of array’ multiplier circuit is designed with hierarchical structure and implemented using conventional CMOS logic in 0.6µm, N-well CMOS process (SCN_SUBM, lambda=0.3) of MOSIS. The proposed multiplier implementation shows large reduction in propagation delay and the average power consumption (at 20MHz) as compared to 16-bit Booth encoded Wallace tree multiplier by F Jalil [3]. The total transistor count, maximum instantaneous power, leakage power, core area, total routing length and number of vias are also presented.
{"title":"A high-speed, hierarchical 16×16 array of array multiplier design","authors":"Abhijit R. Asati, Chandrashekhar","doi":"10.1109/MSPCT.2009.5164200","DOIUrl":"https://doi.org/10.1109/MSPCT.2009.5164200","url":null,"abstract":"Array multipliers are preferred for smaller operand sizes due to their simpler VLSI implementation, in-spite of their linear time complexity. The tree multipliers have time complexity of O (log n) but are less suitable for VLSI implementation since, being less regular, they require larger total routing length, which may degrade their performance. Some hybrid architectures called ‘array of array’ multipliers have intermediate performance. These multipliers have a time complexity better than array multipliers, and therefore becomes an obvious choice for higher performance multiplier designs of moderate operand sizes. In this paper a 16×16 unsigned ‘array of array’ multiplier circuit is designed with hierarchical structure and implemented using conventional CMOS logic in 0.6µm, N-well CMOS process (SCN_SUBM, lambda=0.3) of MOSIS. The proposed multiplier implementation shows large reduction in propagation delay and the average power consumption (at 20MHz) as compared to 16-bit Booth encoded Wallace tree multiplier by F Jalil [3]. The total transistor count, maximum instantaneous power, leakage power, core area, total routing length and number of vias are also presented.","PeriodicalId":179541,"journal":{"name":"2009 International Multimedia, Signal Processing and Communication Technologies","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116375189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-14DOI: 10.1109/MSPCT.2009.5164190
N. Alam, A. K. Kureshi, M. Hasan, T. Arslan
The carbon nanotube (CNT) bundles have potential to provide an attractive solution for the resistivity and electromigration problems faced by traditional copper interconnects in very deep submicron (VDSM) technology. This paper presents a comprehensive analysis of mixed bundles of CNTs and compares various transmission line model interconnect parameters (R, L, & C) with that of the Cu interconnects at 32nm technology node. Results show that the mixed bundles of CNTs have smaller value of R & C for Intermediate and Global level interconnects. However, for Local interconnects Cu wire has smaller value of R and the value of C is comparable to that of the bundle of CNTs.
{"title":"Analysis of carbon nanotube interconnects and their comparison with Cu interconnects","authors":"N. Alam, A. K. Kureshi, M. Hasan, T. Arslan","doi":"10.1109/MSPCT.2009.5164190","DOIUrl":"https://doi.org/10.1109/MSPCT.2009.5164190","url":null,"abstract":"The carbon nanotube (CNT) bundles have potential to provide an attractive solution for the resistivity and electromigration problems faced by traditional copper interconnects in very deep submicron (VDSM) technology. This paper presents a comprehensive analysis of mixed bundles of CNTs and compares various transmission line model interconnect parameters (R, L, & C) with that of the Cu interconnects at 32nm technology node. Results show that the mixed bundles of CNTs have smaller value of R & C for Intermediate and Global level interconnects. However, for Local interconnects Cu wire has smaller value of R and the value of C is comparable to that of the bundle of CNTs.","PeriodicalId":179541,"journal":{"name":"2009 International Multimedia, Signal Processing and Communication Technologies","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114481424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-14DOI: 10.1109/MSPCT.2009.5164185
Maneesha Gupta, Madhu Jain, B. Kumar
A novel recursive wideband digital integrator is presented. The integrator is obtained by interpolating two popular digital integration techniques, the SKG (Schneider-Kaneshige-Groutage) rule and the trapezoidal rule. The proposed integrator accurately approximates the ideal integrator reasonably well over the entire Nyquist frequency range with absolute magnitude error ≤ 0.02 and compares favourably with the existing integrators. The proposed integrator is of third order and is highly accurate.
{"title":"Wideband digital integrator","authors":"Maneesha Gupta, Madhu Jain, B. Kumar","doi":"10.1109/MSPCT.2009.5164185","DOIUrl":"https://doi.org/10.1109/MSPCT.2009.5164185","url":null,"abstract":"A novel recursive wideband digital integrator is presented. The integrator is obtained by interpolating two popular digital integration techniques, the SKG (Schneider-Kaneshige-Groutage) rule and the trapezoidal rule. The proposed integrator accurately approximates the ideal integrator reasonably well over the entire Nyquist frequency range with absolute magnitude error ≤ 0.02 and compares favourably with the existing integrators. The proposed integrator is of third order and is highly accurate.","PeriodicalId":179541,"journal":{"name":"2009 International Multimedia, Signal Processing and Communication Technologies","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121942971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-14DOI: 10.1109/MSPCT.2009.5164204
A. Taherinia, M. Jamzad
In this paper, we propose a new method for damaging and destroying robust invisible watermarks using an image resizing technique which is named seam carving. By using this method we are able to resize watermarked images in a content-aware manner so that the synchronization of the embedder and extractor of watermarking system is broken and the watermark detection becomes impossible. In contrast to the available benchmarks like Stirmark, proposed attack does not severely reduce the quality of the watermarked image. Therefore it maintains the commercial value of the watermarked image. We have tested the proposed method to attack 3 recent and robust watermarking methods and the results sound impressive. The NC for all extracted watermarks after applying this attack is lowers than predefined threshold 0.4, so they are not detectable. The proposed method is a generic attack which does not consider any knowledge about the underlying watermarking algorithm.
{"title":"A new watermarking attack based on content-aware image resizing","authors":"A. Taherinia, M. Jamzad","doi":"10.1109/MSPCT.2009.5164204","DOIUrl":"https://doi.org/10.1109/MSPCT.2009.5164204","url":null,"abstract":"In this paper, we propose a new method for damaging and destroying robust invisible watermarks using an image resizing technique which is named seam carving. By using this method we are able to resize watermarked images in a content-aware manner so that the synchronization of the embedder and extractor of watermarking system is broken and the watermark detection becomes impossible. In contrast to the available benchmarks like Stirmark, proposed attack does not severely reduce the quality of the watermarked image. Therefore it maintains the commercial value of the watermarked image. We have tested the proposed method to attack 3 recent and robust watermarking methods and the results sound impressive. The NC for all extracted watermarks after applying this attack is lowers than predefined threshold 0.4, so they are not detectable. The proposed method is a generic attack which does not consider any knowledge about the underlying watermarking algorithm.","PeriodicalId":179541,"journal":{"name":"2009 International Multimedia, Signal Processing and Communication Technologies","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130951338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-14DOI: 10.1109/MSPCT.2009.5164230
Farooq Hussain, E. Khan, Omar Farooq
In this paper, a novel scheme to extract the watermark data embedded in FRFT domain is presented. The watermark data (FRFT coefficients of the watermark image) is embedded by adding in FRFT coefficients of a host image at pre-determined locations. A non-blind extraction scheme is the main contribution of this paper. To the best of our knowledge, most of the existing work deals with the watermark detection in FRFT domain and only limited efforts are made for extraction of image watermarking in FRFT domain. But, in this paper, extraction of the watermark was performed in images using original host image. The watermark is extracted by subtracting the FRFT coefficients of the watermarked image from the FRFT coefficients of the original host image. Then the watermark is obtained by performing inverse FRFT of difference FRFT coefficients. Simulations results show that the extracted watermark image is very close to the original watermark image.
{"title":"Embedding and non-blind extraction of watermark data in images in FRFT domain","authors":"Farooq Hussain, E. Khan, Omar Farooq","doi":"10.1109/MSPCT.2009.5164230","DOIUrl":"https://doi.org/10.1109/MSPCT.2009.5164230","url":null,"abstract":"In this paper, a novel scheme to extract the watermark data embedded in FRFT domain is presented. The watermark data (FRFT coefficients of the watermark image) is embedded by adding in FRFT coefficients of a host image at pre-determined locations. A non-blind extraction scheme is the main contribution of this paper. To the best of our knowledge, most of the existing work deals with the watermark detection in FRFT domain and only limited efforts are made for extraction of image watermarking in FRFT domain. But, in this paper, extraction of the watermark was performed in images using original host image. The watermark is extracted by subtracting the FRFT coefficients of the watermarked image from the FRFT coefficients of the original host image. Then the watermark is obtained by performing inverse FRFT of difference FRFT coefficients. Simulations results show that the extracted watermark image is very close to the original watermark image.","PeriodicalId":179541,"journal":{"name":"2009 International Multimedia, Signal Processing and Communication Technologies","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116946566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-14DOI: 10.1109/MSPCT.2009.5164177
S. Bedi, Hemant Yadav, P. Yadav
Clustering techniques have been used by many intelligent software agents in order to retrieve, filter, and categorize documents available on the World Wide Web. Clustering is also useful in extracting salient features of related web documents to automatically formulate queries and search for other similar documents on the Web. Traditional clustering algorithms either use a priori knowledge of document structures to define a distance or similarity among these documents, or use probabilistic techniques such as Bayesian classification. Many of these traditional algorithms, however, falter when the dimensionality of the feature space becomes high relative to the size of the document space. In this paper, we introduce two new clustering algorithms that can effectively cluster documents, even in the presence of a very high dimensional feature space. These clustering techniques which are based on generalizations of graph partitioning, do not require pre-specified ad hoc distance functions, and are capable of automatically discovering document similarities or associations. We conduct several experiments on real Web data using various feature selection heuristics, and compare our clustering schemes to standard distance-based techniques, such as hierarchical agglomeration clustering, and Bayesian classification methods, AutoClass.
{"title":"Categorization, clustering and association rule mining on WWW","authors":"S. Bedi, Hemant Yadav, P. Yadav","doi":"10.1109/MSPCT.2009.5164177","DOIUrl":"https://doi.org/10.1109/MSPCT.2009.5164177","url":null,"abstract":"Clustering techniques have been used by many intelligent software agents in order to retrieve, filter, and categorize documents available on the World Wide Web. Clustering is also useful in extracting salient features of related web documents to automatically formulate queries and search for other similar documents on the Web. Traditional clustering algorithms either use a priori knowledge of document structures to define a distance or similarity among these documents, or use probabilistic techniques such as Bayesian classification. Many of these traditional algorithms, however, falter when the dimensionality of the feature space becomes high relative to the size of the document space. In this paper, we introduce two new clustering algorithms that can effectively cluster documents, even in the presence of a very high dimensional feature space. These clustering techniques which are based on generalizations of graph partitioning, do not require pre-specified ad hoc distance functions, and are capable of automatically discovering document similarities or associations. We conduct several experiments on real Web data using various feature selection heuristics, and compare our clustering schemes to standard distance-based techniques, such as hierarchical agglomeration clustering, and Bayesian classification methods, AutoClass.","PeriodicalId":179541,"journal":{"name":"2009 International Multimedia, Signal Processing and Communication Technologies","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124058423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-14DOI: 10.1109/MSPCT.2009.5164227
Farah Maqsood, Omar Farooq, Wasim Ahmad
In this paper a programmable long PN sequence generator using Linear Feedback Shift Register is presented that uses different taps randomly or in a predefined manner. Various statistical tests were also performed which show random nature of the sequence generated. Further, the sequence generated was applied to encrypt an image. The encrypted image shows white noise characteristics and is successfully decrypted.
{"title":"LFSR and PLA based complex code generator for stream cipher","authors":"Farah Maqsood, Omar Farooq, Wasim Ahmad","doi":"10.1109/MSPCT.2009.5164227","DOIUrl":"https://doi.org/10.1109/MSPCT.2009.5164227","url":null,"abstract":"In this paper a programmable long PN sequence generator using Linear Feedback Shift Register is presented that uses different taps randomly or in a predefined manner. Various statistical tests were also performed which show random nature of the sequence generated. Further, the sequence generated was applied to encrypt an image. The encrypted image shows white noise characteristics and is successfully decrypted.","PeriodicalId":179541,"journal":{"name":"2009 International Multimedia, Signal Processing and Communication Technologies","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115564134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-14DOI: 10.1109/MSPCT.2009.5164199
M. S. Ansari, S. Maheshwari
A new mixed-mode quadrature oscillator circuit using two multi-output current controlled conveyors (MOCCCIIs) and two grounded capacitors is presented. In the proposed circuit, four quadrature current-mode signals are available at high impedance nodes. The oscillation conditions and oscillation frequencies are orthogonally (or independently) controllable. Further, two voltage-mode signals in phase quadrature can also be simultaneously obtained from the circuit. The use of only grounded capacitors makes the proposed circuit ideal for integrated circuit implementation. Results of PSPICE simulation confirm the proposed theory.
{"title":"Electronically tunable MOSFET-C mixed-mode quadrature oscillator","authors":"M. S. Ansari, S. Maheshwari","doi":"10.1109/MSPCT.2009.5164199","DOIUrl":"https://doi.org/10.1109/MSPCT.2009.5164199","url":null,"abstract":"A new mixed-mode quadrature oscillator circuit using two multi-output current controlled conveyors (MOCCCIIs) and two grounded capacitors is presented. In the proposed circuit, four quadrature current-mode signals are available at high impedance nodes. The oscillation conditions and oscillation frequencies are orthogonally (or independently) controllable. Further, two voltage-mode signals in phase quadrature can also be simultaneously obtained from the circuit. The use of only grounded capacitors makes the proposed circuit ideal for integrated circuit implementation. Results of PSPICE simulation confirm the proposed theory.","PeriodicalId":179541,"journal":{"name":"2009 International Multimedia, Signal Processing and Communication Technologies","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130084794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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