Pub Date : 1900-01-01DOI: 10.1109/IEDM.1980.189918
H. Becke, R. P. Misra
R & D was carried out on gate turn-off devices, 1. An optimized, high speed epi-base GTO was developed. Fall times of <200ns and rise times 50A/cm2@ Tj=125°C. The fast trand tfresponse was obtained through a controlled gold distribution in the active device volume. A voltage source with series inductance at the gate will establish safe turn-off conditions; a 1.6KW switching capability @ 50kHz is calculated for a chip of 0.15cm2. 2. The introduction of anode shorts improves turn-off, however, turn-on sensitivity is substantially reduced. Replacing these shorts with Schottky barrier diodes fully restores the turn-on sensitivity. Devices with identical VT and similar turn-off capability, ≃ 30A @ 125°c, show about an order of magnitude improvement in turn-on sensitivity @ -40°C if Schottky barriers are added. 3. A dynamic ballasting concept was introduced. Through resistive, edge metalized cathodes the operational range for GTO's was extended from-60°C for turn-on (Igt=300µA) to +150°C for turn-off (J>55A/cm2) The formation of high current density filaments is countered.
{"title":"Investigations of gate turn-off structures","authors":"H. Becke, R. P. Misra","doi":"10.1109/IEDM.1980.189918","DOIUrl":"https://doi.org/10.1109/IEDM.1980.189918","url":null,"abstract":"R & D was carried out on gate turn-off devices, 1. An optimized, high speed epi-base GTO was developed. Fall times of <200ns and rise times 50A/cm2@ Tj=125°C. The fast trand tfresponse was obtained through a controlled gold distribution in the active device volume. A voltage source with series inductance at the gate will establish safe turn-off conditions; a 1.6KW switching capability @ 50kHz is calculated for a chip of 0.15cm2. 2. The introduction of anode shorts improves turn-off, however, turn-on sensitivity is substantially reduced. Replacing these shorts with Schottky barrier diodes fully restores the turn-on sensitivity. Devices with identical VT and similar turn-off capability, ≃ 30A @ 125°c, show about an order of magnitude improvement in turn-on sensitivity @ -40°C if Schottky barriers are added. 3. A dynamic ballasting concept was introduced. Through resistive, edge metalized cathodes the operational range for GTO's was extended from-60°C for turn-on (Igt=300µA) to +150°C for turn-off (J>55A/cm2) The formation of high current density filaments is countered.","PeriodicalId":180541,"journal":{"name":"1980 International Electron Devices Meeting","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114483487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1980.189956
S. Malhi, C. Salama, W. Donnison, H. D. Barber
A novel, bipolar compatible junction field effect transistor structure is described in this paper. The device is fabricated using a single high energy boron implant which results in a p-type channel embedded in an n-epitaxial background material. The channel is buffered from the Si/SiO2interface by a thin n-type layer which improves device reproducibility. The resulting devices exhibit controllable pinchoff voltages in the subvolt range.
{"title":"Subsurface junction field effect transistor (SJFET)","authors":"S. Malhi, C. Salama, W. Donnison, H. D. Barber","doi":"10.1109/IEDM.1980.189956","DOIUrl":"https://doi.org/10.1109/IEDM.1980.189956","url":null,"abstract":"A novel, bipolar compatible junction field effect transistor structure is described in this paper. The device is fabricated using a single high energy boron implant which results in a p-type channel embedded in an n-epitaxial background material. The channel is buffered from the Si/SiO2interface by a thin n-type layer which improves device reproducibility. The resulting devices exhibit controllable pinchoff voltages in the subvolt range.","PeriodicalId":180541,"journal":{"name":"1980 International Electron Devices Meeting","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117081455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1980.189814
J. Fossum, M. A. Shibib
A physical, analytic model for heavily doped polysilicon contacts to silicon bipolar devices is developed. The model defines an effective surface recombination velocity Sefffor minority carriers at the polysilicon-silicon interface in terms of the physical properties of the polysilicon. It thus allows the carrier transport problem in the adjacent silicon region, e.g., the emitter, to be solved and the efficacy of the device, e.g., a transistor or a solar cell, to be characterized, and hence can be an effective design aid. The model is shown to compare well with published experimental data indicating the benefits of polysilicon contacts to bipolar transistors. Such benefits, which result because of the relatively low values of Seff, might also occur when polysilicon contacts are used on silicon solar cells.
{"title":"A minority-carrier transport model for polysilicon contacts to silicon bipolar devices, including solar cells","authors":"J. Fossum, M. A. Shibib","doi":"10.1109/IEDM.1980.189814","DOIUrl":"https://doi.org/10.1109/IEDM.1980.189814","url":null,"abstract":"A physical, analytic model for heavily doped polysilicon contacts to silicon bipolar devices is developed. The model defines an effective surface recombination velocity Sefffor minority carriers at the polysilicon-silicon interface in terms of the physical properties of the polysilicon. It thus allows the carrier transport problem in the adjacent silicon region, e.g., the emitter, to be solved and the efficacy of the device, e.g., a transistor or a solar cell, to be characterized, and hence can be an effective design aid. The model is shown to compare well with published experimental data indicating the benefits of polysilicon contacts to bipolar transistors. Such benefits, which result because of the relatively low values of Seff, might also occur when polysilicon contacts are used on silicon solar cells.","PeriodicalId":180541,"journal":{"name":"1980 International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124485067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1980.189976
D. Yaney, T. Fogarty, R. Porter, D. Fraser, S. Murarka
Long polysilicon runners used for gates and interconnections in large devices limit performance due to RC delays encountered in propagating signals. As devices are scaled down for VLSI, thinner gates and field oxides as well as narrower runner widths tend to accentuate this problem. An order of magnitude decrease in sheet resistance with the corresponding improvement in RC delay is possible through the use of refractory metal silicides for these levels. In this work we describe the fabrication of a fully functional 64K NMOS dynamic RAM where TaSi2was substituted for polysilicon on the second poly level. We discuss the co-sputtering of the silicide on a poly "buffer" layer, annealing and subsequent plasma pattern definition. Final sheet resistance of the silicide level was under 3 ohms per square. In a related study, we have examined device I-V and MOS C-V characteristics and find no degradation due to these process changes. Together with the results of the physical fabrication, this work demonstrates the feasibility of this technology for extensive present and future application.
{"title":"Fabrication of a 64K dynamic MOS RAM with tantalum silicide replacing polysilicon","authors":"D. Yaney, T. Fogarty, R. Porter, D. Fraser, S. Murarka","doi":"10.1109/IEDM.1980.189976","DOIUrl":"https://doi.org/10.1109/IEDM.1980.189976","url":null,"abstract":"Long polysilicon runners used for gates and interconnections in large devices limit performance due to RC delays encountered in propagating signals. As devices are scaled down for VLSI, thinner gates and field oxides as well as narrower runner widths tend to accentuate this problem. An order of magnitude decrease in sheet resistance with the corresponding improvement in RC delay is possible through the use of refractory metal silicides for these levels. In this work we describe the fabrication of a fully functional 64K NMOS dynamic RAM where TaSi2was substituted for polysilicon on the second poly level. We discuss the co-sputtering of the silicide on a poly \"buffer\" layer, annealing and subsequent plasma pattern definition. Final sheet resistance of the silicide level was under 3 ohms per square. In a related study, we have examined device I-V and MOS C-V characteristics and find no degradation due to these process changes. Together with the results of the physical fabrication, this work demonstrates the feasibility of this technology for extensive present and future application.","PeriodicalId":180541,"journal":{"name":"1980 International Electron Devices Meeting","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124774873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1980.189932
L. Tannas
The most critical problem in flat-panel displays reduces to that of addressing the large array of picture elements (pixels). Numerous technologies have evolved for creating an image, including gas discharge, vacuum fluorescence, light-emitting diodes, electroluminescence, liquid crystallinity, and electrochromism. The problem of addressing the array for an eight-character display with 64 pixels is critical and becomes awesome for a 2000-character display or a TV video display with approximately 200,000 pixels. This paper reviews the status of technology for addressing a flat-panel display, presents new techniques for the analysis of large arrays, and describes the state of the art of display drive electronics.
{"title":"Matrix addressing flat-panel displays","authors":"L. Tannas","doi":"10.1109/IEDM.1980.189932","DOIUrl":"https://doi.org/10.1109/IEDM.1980.189932","url":null,"abstract":"The most critical problem in flat-panel displays reduces to that of addressing the large array of picture elements (pixels). Numerous technologies have evolved for creating an image, including gas discharge, vacuum fluorescence, light-emitting diodes, electroluminescence, liquid crystallinity, and electrochromism. The problem of addressing the array for an eight-character display with 64 pixels is critical and becomes awesome for a 2000-character display or a TV video display with approximately 200,000 pixels. This paper reviews the status of technology for addressing a flat-panel display, presents new techniques for the analysis of large arrays, and describes the state of the art of display drive electronics.","PeriodicalId":180541,"journal":{"name":"1980 International Electron Devices Meeting","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113956627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1980.189929
C. Fung, P. Cheung, W. Ko
A model adapting the surface ionization and complexation of the surface hydroxyl groups on the gate insulator surface in conjunction with the IGFET theory is proposed to arrive at the terminal behavior of the electrolyte-insulator-semiconductor field-effect transistor (EISFET) in response to the variation of electrolyte parameters. Experimental results of EISFET employing thermally grown silicon dioxide in simple electrolytes containing Na+, K+and Li+ions titrated in a pH range from 2 to 9 were found to be in good agreement with the theory. The model successfully explains the pH sensitivity as well as the ion interference effect of the EISFET as a pH sensor. From this model, it is concluded that the surface site density, NS, and the separation of surface ionization constants, in terms of ΔpK, are the main controlling factors for the EISFET as a pH sensor. For high sensitivity and good selectivity, large NS and small ΔpK values are required.
{"title":"Electrolyte-insulator-semiconductor field-effect transistor","authors":"C. Fung, P. Cheung, W. Ko","doi":"10.1109/IEDM.1980.189929","DOIUrl":"https://doi.org/10.1109/IEDM.1980.189929","url":null,"abstract":"A model adapting the surface ionization and complexation of the surface hydroxyl groups on the gate insulator surface in conjunction with the IGFET theory is proposed to arrive at the terminal behavior of the electrolyte-insulator-semiconductor field-effect transistor (EISFET) in response to the variation of electrolyte parameters. Experimental results of EISFET employing thermally grown silicon dioxide in simple electrolytes containing Na+, K+and Li+ions titrated in a pH range from 2 to 9 were found to be in good agreement with the theory. The model successfully explains the pH sensitivity as well as the ion interference effect of the EISFET as a pH sensor. From this model, it is concluded that the surface site density, NS, and the separation of surface ionization constants, in terms of ΔpK, are the main controlling factors for the EISFET as a pH sensor. For high sensitivity and good selectivity, large NS and small ΔpK values are required.","PeriodicalId":180541,"journal":{"name":"1980 International Electron Devices Meeting","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124880063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1980.189980
P. Chen, R. Jolly, G. Halac, R. Muller, R. White, A. Andrews, M. E. Motamedi
Excel lent experimental performance has been observed on in tegra ted acce lerometer s t ruc tures t h a t were fab r i ca t ed us ing capac i t i ve PI-FET t r a n s d u c e r s ( l ) t o d e t e c t s t r a i n s i n m i n i a t u r e c a n t i l e v e r beams. The beams are composite struct u r e s c o n s i s t i n g of s i l i c o n , s i l i c o n d i o x i d e , z i n c oxide, metal and pass iva t ing oxide (F igure 1). They a r e formed by a n i s o t r o p i c a l l y e t c h i n g t h e s i l i con f rom undernea th the l aye red s t ruc tu res using EDP e t c h a n t i n t h e manner desc r ibed by P e t e r s e n , ( Z ) o r e l s e by a combination of backside and f r o n t s i d e e t c h i n g of t he wafe r w i th EDP so lu t i on . The p i e z o e l e c t r i c s t r a i n s e n s i n g l a y e r s are direct ly coupled to deplet ion-type, p-channel MOS t r a n s i s t o r s . Dependent on the fabrication procedures employed, the total beam t h i c k n e s s e s a r e e i t h e r below 5 pm ( f o r t o p s u r f a c e e t c h i n g ) , o r else range to about 50 pm ( for e tch ing f rom both s i d e s of t he wafe r ) . S ix sets of beam wid th l l eng th rat ios have been designed: 701235, 2001225, 2751510, 4101505, 5001570, and 950/1240 pm i n o r d e r t o a c h i e v e s e n s i t i v i t i e s t o a wide range of g values and to de te rmine process ing cons t ra in ts . The a c c e l e r o m e t e r s t r u c t u r e s a r e p a r t i a l l y t e m p e r a ture compensated by t h e a d d i t i o n o f a n u n s t r a i n e d z inc -ox ide capac i to r t o ba l ance ou t t he vo l t age produced by t h e p y r o e l e c t r i c i t y o f t h e ZnO. An i n v e s t i g a t i o n of t e m p e r a t u r e s e n s i t i v i t y i s prese n t l y underway.
{"title":"A planar-processed PI-FET accelerometer","authors":"P. Chen, R. Jolly, G. Halac, R. Muller, R. White, A. Andrews, M. E. Motamedi","doi":"10.1109/IEDM.1980.189980","DOIUrl":"https://doi.org/10.1109/IEDM.1980.189980","url":null,"abstract":"Excel lent experimental performance has been observed on in tegra ted acce lerometer s t ruc tures t h a t were fab r i ca t ed us ing capac i t i ve PI-FET t r a n s d u c e r s ( l ) t o d e t e c t s t r a i n s i n m i n i a t u r e c a n t i l e v e r beams. The beams are composite struct u r e s c o n s i s t i n g of s i l i c o n , s i l i c o n d i o x i d e , z i n c oxide, metal and pass iva t ing oxide (F igure 1). They a r e formed by a n i s o t r o p i c a l l y e t c h i n g t h e s i l i con f rom undernea th the l aye red s t ruc tu res using EDP e t c h a n t i n t h e manner desc r ibed by P e t e r s e n , ( Z ) o r e l s e by a combination of backside and f r o n t s i d e e t c h i n g of t he wafe r w i th EDP so lu t i on . The p i e z o e l e c t r i c s t r a i n s e n s i n g l a y e r s are direct ly coupled to deplet ion-type, p-channel MOS t r a n s i s t o r s . Dependent on the fabrication procedures employed, the total beam t h i c k n e s s e s a r e e i t h e r below 5 pm ( f o r t o p s u r f a c e e t c h i n g ) , o r else range to about 50 pm ( for e tch ing f rom both s i d e s of t he wafe r ) . S ix sets of beam wid th l l eng th rat ios have been designed: 701235, 2001225, 2751510, 4101505, 5001570, and 950/1240 pm i n o r d e r t o a c h i e v e s e n s i t i v i t i e s t o a wide range of g values and to de te rmine process ing cons t ra in ts . The a c c e l e r o m e t e r s t r u c t u r e s a r e p a r t i a l l y t e m p e r a ture compensated by t h e a d d i t i o n o f a n u n s t r a i n e d z inc -ox ide capac i to r t o ba l ance ou t t he vo l t age produced by t h e p y r o e l e c t r i c i t y o f t h e ZnO. An i n v e s t i g a t i o n of t e m p e r a t u r e s e n s i t i v i t y i s prese n t l y underway.","PeriodicalId":180541,"journal":{"name":"1980 International Electron Devices Meeting","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125680660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1980.189886
J. Fan, C. Bozler, R. Gale, R. McClelland, R. L. Chapman, G. Turner, H. J. Zeiger
By using an n+/p/p+structure, we have previously succeeded in fabricating GaAs solar cells on single-crystal GaAs and Ge substrates, with conversion efficiency of 21% at AM1. Three approaches are being used to lower the cost of such cells, preparation of large-grained Ge sheets on low-cost substrates, preparation of heteroepitaxial Ge films on inexpensive Si sheets, and preparation of thin single-crystal GaAs layers on reusable GaAs substrates. Important advances have been achieved in all three areas. Crystallites 2 µm × 100 µm have been obtained on fused silica substrates by heating amorphous Ge films with a scanned Nd:YAG laser. Heteroepitaxial Ge films have also been obtained on Si substrates by transient heating, and epitaxial GaAs layers have been grown on such films. Single-crystal GaAs layers as thin as 5 µm have been separated from reusable GaAs substrates by a new process named CLEFT. A 15% (AMI) GaAs solar cell, only 8 µm thick and bonded to a glass substrate, has been fabricated. With these developments, low-cost high-efficiency, GaAs cells may well become a reality.
{"title":"Recent advances in high efficiency, low-cost GaAs solar cells","authors":"J. Fan, C. Bozler, R. Gale, R. McClelland, R. L. Chapman, G. Turner, H. J. Zeiger","doi":"10.1109/IEDM.1980.189886","DOIUrl":"https://doi.org/10.1109/IEDM.1980.189886","url":null,"abstract":"By using an n+/p/p+structure, we have previously succeeded in fabricating GaAs solar cells on single-crystal GaAs and Ge substrates, with conversion efficiency of 21% at AM1. Three approaches are being used to lower the cost of such cells, preparation of large-grained Ge sheets on low-cost substrates, preparation of heteroepitaxial Ge films on inexpensive Si sheets, and preparation of thin single-crystal GaAs layers on reusable GaAs substrates. Important advances have been achieved in all three areas. Crystallites 2 µm × 100 µm have been obtained on fused silica substrates by heating amorphous Ge films with a scanned Nd:YAG laser. Heteroepitaxial Ge films have also been obtained on Si substrates by transient heating, and epitaxial GaAs layers have been grown on such films. Single-crystal GaAs layers as thin as 5 µm have been separated from reusable GaAs substrates by a new process named CLEFT. A 15% (AMI) GaAs solar cell, only 8 µm thick and bonded to a glass substrate, has been fabricated. With these developments, low-cost high-efficiency, GaAs cells may well become a reality.","PeriodicalId":180541,"journal":{"name":"1980 International Electron Devices Meeting","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125916417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1980.189801
A. Goodman
The constant-magnitude steady-state surface photovoltage (SPV) method for determining the minority carrier diffusion length L is in principle an excellent technique. It has, however, recevied relatively limited use because of practical difficulties in carrying out the required measurements. This paper describes an improved measurement system that virtually eliminates these difficulties and allows a rapid straightforward determination of L. These measurements in silicon monitor wafers have enabled a routine quality control check on many factory processing steps, particularly those that are carried out at high temperature and have the potential for significantly degrading L.
{"title":"Improvements in method and apparatus for determining minority carrier diffusion length","authors":"A. Goodman","doi":"10.1109/IEDM.1980.189801","DOIUrl":"https://doi.org/10.1109/IEDM.1980.189801","url":null,"abstract":"The constant-magnitude steady-state surface photovoltage (SPV) method for determining the minority carrier diffusion length L is in principle an excellent technique. It has, however, recevied relatively limited use because of practical difficulties in carrying out the required measurements. This paper describes an improved measurement system that virtually eliminates these difficulties and allows a rapid straightforward determination of L. These measurements in silicon monitor wafers have enabled a routine quality control check on many factory processing steps, particularly those that are carried out at high temperature and have the potential for significantly degrading L.","PeriodicalId":180541,"journal":{"name":"1980 International Electron Devices Meeting","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125524649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1980.189746
M. Wada, S. Mimura, H. Nihira, H. Iizuka
In order to realize high density EPROM's it is necessary to reduce the dimensions of EPROM cells. In this paper the programming characteristics of the floating gate EPROM's are discussed in relation to the limiting factors for device parameters and the programming conditions. Some problems which arise from the arrayed cell configuration are clarified. The programming speed of an EPROM is remarkably lowered by the voltage drop in a bit line due to an excess current flow through deselected cells which is induced by pulling up of the floating gate potential due to capacitance coupling between the bit line and the floating gate. A punch-through current in memory cells has the same effect on the programming characteristics. The feasibility of higher density EPROM's are also discussed by taking these problems into account.
{"title":"Limiting factors for programming EPROM of reduced dimensions","authors":"M. Wada, S. Mimura, H. Nihira, H. Iizuka","doi":"10.1109/IEDM.1980.189746","DOIUrl":"https://doi.org/10.1109/IEDM.1980.189746","url":null,"abstract":"In order to realize high density EPROM's it is necessary to reduce the dimensions of EPROM cells. In this paper the programming characteristics of the floating gate EPROM's are discussed in relation to the limiting factors for device parameters and the programming conditions. Some problems which arise from the arrayed cell configuration are clarified. The programming speed of an EPROM is remarkably lowered by the voltage drop in a bit line due to an excess current flow through deselected cells which is induced by pulling up of the floating gate potential due to capacitance coupling between the bit line and the floating gate. A punch-through current in memory cells has the same effect on the programming characteristics. The feasibility of higher density EPROM's are also discussed by taking these problems into account.","PeriodicalId":180541,"journal":{"name":"1980 International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121545330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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