Pub Date : 1900-01-01DOI: 10.1109/IEDM.1980.189859
H. Ohno, J. Barnard, C. Wood, L. Rathbun, L. Eastman
MESFETs with Ga0.47In0.53As active channel grown by MBE on InP substrates were successfully fabricated Thin layers of MBE grown Al0.48In0.52As separated both the single crystal aluminum gate from the active channel and the active channel from the semi-insulating InP substrate so raising the Schottky barrier height and confining the electrons to the channel. The MESFETs with 0.6 µm long gates and gate-to-source separations of 0.8 µm exhibited an average gmof 135 mS mm-1of gate width for Vds= 2V and Vg= 0V. An integrated photoreceiver comprising a dual gate DH GaInAs MESFET and two notch-type photoconductive detectors in series has been fabricated and shows potential for high speed operation.
MBE生长的薄层Al0.48In0.52As使单晶铝栅与有源沟道分离，也使有源沟道与半绝缘的InP衬底分离，从而提高了肖特基势垒高度，将电子限制在沟道内。在Vds= 2V和Vg= 0V条件下，栅极长度为0.6µm、栅极源间距为0.8µm的mesfet的栅极宽度平均为135 mS mm-1。一种集成光接收器由双栅DH GaInAs MESFET和两个槽型光导探测器串联组成，并显示出高速运行的潜力。
{"title":"Double heterojunction GaInAs devices by MBE","authors":"H. Ohno, J. Barnard, C. Wood, L. Rathbun, L. Eastman","doi":"10.1109/IEDM.1980.189859","DOIUrl":"https://doi.org/10.1109/IEDM.1980.189859","url":null,"abstract":"MESFETs with Ga<inf>0.47</inf>In<inf>0.53</inf>As active channel grown by MBE on InP substrates were successfully fabricated Thin layers of MBE grown Al<inf>0.48</inf>In<inf>0.52</inf>As separated both the single crystal aluminum gate from the active channel and the active channel from the semi-insulating InP substrate so raising the Schottky barrier height and confining the electrons to the channel. The MESFETs with 0.6 µm long gates and gate-to-source separations of 0.8 µm exhibited an average g<inf>m</inf>of 135 mS mm<sup>-1</sup>of gate width for V<inf>ds</inf>= 2V and V<inf>g</inf>= 0V. An integrated photoreceiver comprising a dual gate DH GaInAs MESFET and two notch-type photoconductive detectors in series has been fabricated and shows potential for high speed operation.","PeriodicalId":180541,"journal":{"name":"1980 International Electron Devices Meeting","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131254551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1980.189752
D. Tang, V. Silvestri, H.N. Yu, A. Reisman
This paper presents symmetrical bipolar-transistor structures suitable for bilateral operation. Such structures were fabricated using a technique of simultaneous-growth of epitaxial and polycrystalline Si on a stack structure. Vertical symmetrical transistors have been built and showed an emitter-base diode breakdown voltage of 7V, a current gain of 17.
{"title":"A symmetrical bipolar structure","authors":"D. Tang, V. Silvestri, H.N. Yu, A. Reisman","doi":"10.1109/IEDM.1980.189752","DOIUrl":"https://doi.org/10.1109/IEDM.1980.189752","url":null,"abstract":"This paper presents symmetrical bipolar-transistor structures suitable for bilateral operation. Such structures were fabricated using a technique of simultaneous-growth of epitaxial and polycrystalline Si on a stack structure. Vertical symmetrical transistors have been built and showed an emitter-base diode breakdown voltage of 7V, a current gain of 17.","PeriodicalId":180541,"journal":{"name":"1980 International Electron Devices Meeting","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131043560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1980.189885
G. Olsen, F. Hawrylo, D. Channin, D. Botez, M. Ettenberg
Both vapor phase epitaxy (VPE) and liquid phase epitaxy (LPE) have been used to fabricate 1.3 µm InGaAsP/InP double heterojunction edge-emitting LEDs. Narrow contact stripes (12 µm), thin active regions (300-1200 Å) and modified device geometries were used to improve the coupling efficiency of these LEDs to optical fibers. Over 130 µW of optical power has been coupled into 50 µm core 0.2 N.A. graded index fiber. Coupling efficiencies over 10% were measured with both VPE and LPE devices. Modulation rates over 200 MHz (3 dB point) and rise times ∼2 ns have also been measured. The increased coupling efficiency together with high speed operation is attributed to the use of the edge-emitting device structure with thin active regions. Operating lifetimes of over 14,000 hours at 70°C and 3000 hours at 120°C have also been observed.
{"title":"High performance 1.3 µm InGaAsP edge-emitting LEDs","authors":"G. Olsen, F. Hawrylo, D. Channin, D. Botez, M. Ettenberg","doi":"10.1109/IEDM.1980.189885","DOIUrl":"https://doi.org/10.1109/IEDM.1980.189885","url":null,"abstract":"Both vapor phase epitaxy (VPE) and liquid phase epitaxy (LPE) have been used to fabricate 1.3 µm InGaAsP/InP double heterojunction edge-emitting LEDs. Narrow contact stripes (12 µm), thin active regions (300-1200 Å) and modified device geometries were used to improve the coupling efficiency of these LEDs to optical fibers. Over 130 µW of optical power has been coupled into 50 µm core 0.2 N.A. graded index fiber. Coupling efficiencies over 10% were measured with both VPE and LPE devices. Modulation rates over 200 MHz (3 dB point) and rise times ∼2 ns have also been measured. The increased coupling efficiency together with high speed operation is attributed to the use of the edge-emitting device structure with thin active regions. Operating lifetimes of over 14,000 hours at 70°C and 3000 hours at 120°C have also been observed.","PeriodicalId":180541,"journal":{"name":"1980 International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131127252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1980.189949
W. Hunter, T. Holloway, P. Chatterjee, A. Tasch
This paper describes a new, convenient "undercut and backfill" technique for forming edge-defined submicrometer elements based only on standard optical lithography and vertical (anisotropic) dry etching. MOSFETs having physical channel lengths from0.3 microm tosimeq 1.0 microm can be fabricated using this approach, This method is compared with an alternative vertical etch, edge-defined technique which is capable of fabricating physical gate lengths oF0.1-0.4 microm. In particular, MOSFETs havingL simeq 0.1 microm, believed to be the smallest reported to date, have been made. A vertical etching technique which forms a passivating sidewall oxide is also described. Modifications of this technique to fabricate self-aligned shallow/deep n+/n++ junctions having reduced series resistance and short-channel effects (in particular punchthrough) are illustrated.
{"title":"New edge-defined vertical-etch approaches for submicrometer MOSFET fabrication","authors":"W. Hunter, T. Holloway, P. Chatterjee, A. Tasch","doi":"10.1109/IEDM.1980.189949","DOIUrl":"https://doi.org/10.1109/IEDM.1980.189949","url":null,"abstract":"This paper describes a new, convenient \"undercut and backfill\" technique for forming edge-defined submicrometer elements based only on standard optical lithography and vertical (anisotropic) dry etching. MOSFETs having physical channel lengths from0.3 microm tosimeq 1.0 microm can be fabricated using this approach, This method is compared with an alternative vertical etch, edge-defined technique which is capable of fabricating physical gate lengths oF0.1-0.4 microm. In particular, MOSFETs havingL simeq 0.1 microm, believed to be the smallest reported to date, have been made. A vertical etching technique which forms a passivating sidewall oxide is also described. Modifications of this technique to fabricate self-aligned shallow/deep n+/n++ junctions having reduced series resistance and short-channel effects (in particular punchthrough) are illustrated.","PeriodicalId":180541,"journal":{"name":"1980 International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131198853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1980.189958
J. Ruzyllo, J. Stach
The Lateral MIS Tunnel Transistor (LMISTT) is a transistor structure which exploits the combined properties of lateral MIS tunnel structures and non-equilibrium MIS tunnel diodes. Due to its features the LMISTT offers possibilities in a variety of applications including very large scale integrated high speed IC's. In this work the various aspects of design and processing of this device are discussed in relation to its basic properties and performance.
{"title":"Basic properties of lateral MIS tunnel transistor","authors":"J. Ruzyllo, J. Stach","doi":"10.1109/IEDM.1980.189958","DOIUrl":"https://doi.org/10.1109/IEDM.1980.189958","url":null,"abstract":"The Lateral MIS Tunnel Transistor (LMISTT) is a transistor structure which exploits the combined properties of lateral MIS tunnel structures and non-equilibrium MIS tunnel diodes. Due to its features the LMISTT offers possibilities in a variety of applications including very large scale integrated high speed IC's. In this work the various aspects of design and processing of this device are discussed in relation to its basic properties and performance.","PeriodicalId":180541,"journal":{"name":"1980 International Electron Devices Meeting","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132707213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1980.189770
S. Nanbu, M. Hagio, A. Nagashima, K. Goda, G. Kanô, I. Teramoto
This paper demonstrates a new dual-gate GaAs MESFET specially designed for a UHF TV tuner that meets the coming FCC regulation of NF reduction to the same level as the present VHF TV tuner. The device has been designed under the philosophy as follows. (i) To reduce |S11| at the smallest expense of the low noise feature interent in GaAs MESFETs. (ii) To obtain AGC and cross-modulation performances compatible with those of a conventional Si MOS tetrode. The optimized pattern geometry satisfying the above philosophy was obtained through extensive theoretical and experimental studies. The FET was molded in a plastic package. The new FET, of which minimum NF value is as low as 0.9dB. was compatible with a Si MOS tetrode in a conventional tuner circuit owing to the large K value. The AGC and CM performances were also satisfactorily excellent.
{"title":"A dual-gate MESFET for a high performance UHF TV tuner","authors":"S. Nanbu, M. Hagio, A. Nagashima, K. Goda, G. Kanô, I. Teramoto","doi":"10.1109/IEDM.1980.189770","DOIUrl":"https://doi.org/10.1109/IEDM.1980.189770","url":null,"abstract":"This paper demonstrates a new dual-gate GaAs MESFET specially designed for a UHF TV tuner that meets the coming FCC regulation of NF reduction to the same level as the present VHF TV tuner. The device has been designed under the philosophy as follows. (i) To reduce |S11| at the smallest expense of the low noise feature interent in GaAs MESFETs. (ii) To obtain AGC and cross-modulation performances compatible with those of a conventional Si MOS tetrode. The optimized pattern geometry satisfying the above philosophy was obtained through extensive theoretical and experimental studies. The FET was molded in a plastic package. The new FET, of which minimum NF value is as low as 0.9dB. was compatible with a Si MOS tetrode in a conventional tuner circuit owing to the large K value. The AGC and CM performances were also satisfactorily excellent.","PeriodicalId":180541,"journal":{"name":"1980 International Electron Devices Meeting","volume":"71 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127840467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1980.189936
S. Miura, S. Sato
Conventional ZnS:Mn electroluminescence (EL) device has a good level of brightness but needs a high operating voltage. The best way to lower the operating voltage seemed to be by reducing the band gap of the host material and to achieve this, ZnSe had been proposed before. However, our experiments showed that when the ZnSe:Mn EL was operated at low voltages the brightness level and contrast ratio decreased, due to the yellowish coloration of the ZnSe film. The authors have developed a host material which combines both advantages; the high brightness level of ZnS, and the low operating voltage of ZnSe. A material with a band gap between those of ZnS (3.7 eV) and ZnSe (2.7 eV) was tested. By coevaporation of ZnS and ZnSe, a solid solution ZnSxSe1-xwas found in an evaporated film. By measuring the absorption edge and using X-ray techniques, we found that the band gap varied in proportion to the concentration of selenium. A thin film of ZnS0.4Se0.6EL sandwiched between Y2O3insulating layers can operate at a low voltage (120 V) with a high level of brightness (>100 fL at 1 KHz), with a very small upward voltage shift (10 V) during aging.
{"title":"Thin film AC ZnSxSe1-x:Mn EL","authors":"S. Miura, S. Sato","doi":"10.1109/IEDM.1980.189936","DOIUrl":"https://doi.org/10.1109/IEDM.1980.189936","url":null,"abstract":"Conventional ZnS:Mn electroluminescence (EL) device has a good level of brightness but needs a high operating voltage. The best way to lower the operating voltage seemed to be by reducing the band gap of the host material and to achieve this, ZnSe had been proposed before. However, our experiments showed that when the ZnSe:Mn EL was operated at low voltages the brightness level and contrast ratio decreased, due to the yellowish coloration of the ZnSe film. The authors have developed a host material which combines both advantages; the high brightness level of ZnS, and the low operating voltage of ZnSe. A material with a band gap between those of ZnS (3.7 eV) and ZnSe (2.7 eV) was tested. By coevaporation of ZnS and ZnSe, a solid solution ZnSxSe1-xwas found in an evaporated film. By measuring the absorption edge and using X-ray techniques, we found that the band gap varied in proportion to the concentration of selenium. A thin film of ZnS0.4Se0.6EL sandwiched between Y2O3insulating layers can operate at a low voltage (120 V) with a high level of brightness (>100 fL at 1 KHz), with a very small upward voltage shift (10 V) during aging.","PeriodicalId":180541,"journal":{"name":"1980 International Electron Devices Meeting","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134475293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1980.189815
B. Zetterlund, A. Steckl
The recombination lifetime, τr, has been measured at low temperature in Si p-MOSFET's using charge pumping. Measurements were performed over the 40-300°K range. A monotonically increasing lifetime with decreasing temperature was measured. τrwas found to be proportional to exp(Ar/kT), where Aris a constant determined from the slope of lnτ vs. l/T. For a typical MOSFET the lifetime ranged from 0.08 µs at 300°K to 0.37 ms at 100°K. The value of Arin this case was determined to be 106 meV.
{"title":"Low temperature recombination lifetime in Si MOSFET's","authors":"B. Zetterlund, A. Steckl","doi":"10.1109/IEDM.1980.189815","DOIUrl":"https://doi.org/10.1109/IEDM.1980.189815","url":null,"abstract":"The recombination lifetime, τ<inf>r</inf>, has been measured at low temperature in Si p-MOSFET's using charge pumping. Measurements were performed over the 40-300°K range. A monotonically increasing lifetime with decreasing temperature was measured. τ<inf>r</inf>was found to be proportional to exp(A<inf>r</inf>/kT), where A<inf>r</inf>is a constant determined from the slope of lnτ vs. l/T. For a typical MOSFET the lifetime ranged from 0.08 µs at 300°K to 0.37 ms at 100°K. The value of A<inf>r</inf>in this case was determined to be 106 meV.","PeriodicalId":180541,"journal":{"name":"1980 International Electron Devices Meeting","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115470021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1980.189740
R.N. Thomas
The status of melt growth techniques for preparing large-area Si and GaAs bulk substrates for microelectronic devices is reviewed. The Czochralski crystal growth process, which yields large diameter, doped single crystals by pulling from a hot crucible-contained melt, has gained widespread acceptance by silicon IC manufacturers. In a modified form, this process has also been applied to several compound semiconductors and commercial liquid encapsulated Czochralski crystal pullers are currently available for producing large diameter GaAs crystals. Innovative approaches aimed at improving compositional purity, structural perfection and uniformity in these important electronic materials are discussed. New device opportunities afforded by improvements in basic materials parameters are illustrated by (i) the role of residual impurities in infrared focal plane arrays based on extrinsically-doped silicon, (ii) the importance of oxygen and oxygen-related defects in LSI silicon processing, and (iii) the current progress in monolithic microwave GaAs IC processing technology.
{"title":"Advances in bulk silicon and gallium arsenide materials technology","authors":"R.N. Thomas","doi":"10.1109/IEDM.1980.189740","DOIUrl":"https://doi.org/10.1109/IEDM.1980.189740","url":null,"abstract":"The status of melt growth techniques for preparing large-area Si and GaAs bulk substrates for microelectronic devices is reviewed. The Czochralski crystal growth process, which yields large diameter, doped single crystals by pulling from a hot crucible-contained melt, has gained widespread acceptance by silicon IC manufacturers. In a modified form, this process has also been applied to several compound semiconductors and commercial liquid encapsulated Czochralski crystal pullers are currently available for producing large diameter GaAs crystals. Innovative approaches aimed at improving compositional purity, structural perfection and uniformity in these important electronic materials are discussed. New device opportunities afforded by improvements in basic materials parameters are illustrated by (i) the role of residual impurities in infrared focal plane arrays based on extrinsically-doped silicon, (ii) the importance of oxygen and oxygen-related defects in LSI silicon processing, and (iii) the current progress in monolithic microwave GaAs IC processing technology.","PeriodicalId":180541,"journal":{"name":"1980 International Electron Devices Meeting","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114730515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1980.189837
D. Botez, J. Connolly
Constricted double-heterojunction (CDH) diode lasers of relatively low cw thresholds (28-40 mA) are obtained by growing structures that maximize the amount of current flow into the lasing spot. This is achieved while using "standard" 10-µm-wide oxide-defined stripe contacts. The temperature dependence of threshold currents in CDH lasers with strong lateral mode confinement is found to be significantly milder than for other types of lasers. The threshold-current relative variations with ambient temperature are two to three times less than for any other devices of cw-operation capability. Over the interval 10-70°c the threshold currents fit the empirical exponential law exp (frac{T_{2}-T_{1}}{T_{0})with T0values in the 240°-375° range To in pulsed operation, and in the 200-310° range in cw operation. The external differential quantum efficiency and the mode far-field pattern near threshold are virtually invariant with temperature. The possible causes of high-To behavior are analyzed, and a new phenomenon--temperature-dependent current focusing--is presented to explain the results.
{"title":"Low-threshold high-T0constricted double heterojunction AlGaAs lasers","authors":"D. Botez, J. Connolly","doi":"10.1109/IEDM.1980.189837","DOIUrl":"https://doi.org/10.1109/IEDM.1980.189837","url":null,"abstract":"Constricted double-heterojunction (CDH) diode lasers of relatively low cw thresholds (28-40 mA) are obtained by growing structures that maximize the amount of current flow into the lasing spot. This is achieved while using \"standard\" 10-µm-wide oxide-defined stripe contacts. The temperature dependence of threshold currents in CDH lasers with strong lateral mode confinement is found to be significantly milder than for other types of lasers. The threshold-current relative variations with ambient temperature are two to three times less than for any other devices of cw-operation capability. Over the interval 10-70°c the threshold currents fit the empirical exponential law exp (frac{T_{2}-T_{1}}{T_{0})with T0values in the 240°-375° range To in pulsed operation, and in the 200-310° range in cw operation. The external differential quantum efficiency and the mode far-field pattern near threshold are virtually invariant with temperature. The possible causes of high-To behavior are analyzed, and a new phenomenon--temperature-dependent current focusing--is presented to explain the results.","PeriodicalId":180541,"journal":{"name":"1980 International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128447405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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