In this paper we present the design methodology and implementation of a wide frequency range (30 MHz-1 GHz) low-power, Integrated CMOS mixer. The mixer has a high conversion gain (12 dB), and a low noise figure (9.2 dB) and operates at 3.3 V. The mixer is designed for low power mobile transceiver (user sets), where power consumption is a key issue. The wide frequency band and dynamic range of the mixer makes it suitable for both homodyne (zero-IF) and heterodyne mobile transceivers.
{"title":"Wide frequency range (30 M-1 GHz) low noise figure, low power, active CMOS mixer","authors":"E.W. El-Shewekh, M. El-Saba","doi":"10.1109/ICM.2003.238503","DOIUrl":"https://doi.org/10.1109/ICM.2003.238503","url":null,"abstract":"In this paper we present the design methodology and implementation of a wide frequency range (30 MHz-1 GHz) low-power, Integrated CMOS mixer. The mixer has a high conversion gain (12 dB), and a low noise figure (9.2 dB) and operates at 3.3 V. The mixer is designed for low power mobile transceiver (user sets), where power consumption is a key issue. The wide frequency band and dynamic range of the mixer makes it suitable for both homodyne (zero-IF) and heterodyne mobile transceivers.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127486616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a new approach to on-line fault tolerance via reconfiguration for the systems mapped onto field programmable gate arrays (FPGAs). The fault detection, based on self-checking technique, is introduced at application level, therefore our approach can detect the faults in the FPGAs concurrently with the normal system work. A grid of tiles is projected on the FPGA structure and a certain number of spare configurable logic blocks (CLBs) is reserved inside every tile. Unlike fixed structure fault-tolerance techniques for ASICs and microprocessors. this approach allows a single physical component to provide redundant backup for several types of components. The reliability gain of the proposed solution was evaluated using basic reliability parameter, whose values were computed for different alternatives of the solution.
{"title":"Embedding fault tolerance via reconfiguration in configurable systems","authors":"K. Elshafey","doi":"10.1109/ICM.2003.237968","DOIUrl":"https://doi.org/10.1109/ICM.2003.237968","url":null,"abstract":"This paper presents a new approach to on-line fault tolerance via reconfiguration for the systems mapped onto field programmable gate arrays (FPGAs). The fault detection, based on self-checking technique, is introduced at application level, therefore our approach can detect the faults in the FPGAs concurrently with the normal system work. A grid of tiles is projected on the FPGA structure and a certain number of spare configurable logic blocks (CLBs) is reserved inside every tile. Unlike fixed structure fault-tolerance techniques for ASICs and microprocessors. this approach allows a single physical component to provide redundant backup for several types of components. The reliability gain of the proposed solution was evaluated using basic reliability parameter, whose values were computed for different alternatives of the solution.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128364143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we propose a novel Viterbi decoder core. This core is optimized to minimize the decoding latency, which is an important factor for real time multimedia applications. The new core has the same complexity as the conventional cores and it achieves the same performance.
{"title":"A Viterbi decoder core with no trace-back unit","authors":"A. Shebaita, M. Khairy, A. Salama, M. Ashour","doi":"10.1109/ICM.2003.237969","DOIUrl":"https://doi.org/10.1109/ICM.2003.237969","url":null,"abstract":"In this paper, we propose a novel Viterbi decoder core. This core is optimized to minimize the decoding latency, which is an important factor for real time multimedia applications. The new core has the same complexity as the conventional cores and it achieves the same performance.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131932162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a processor that efficiently executes Verilog code written at Register Transfer Level (RTL). It is a RISC type processor that performs the parallel execution of multiple procedural blocks of Verilog HDL. This results in a very significant saving of simulation time. The simulation time taken by the software based simulation in terms of clock cycles on a normal Pentium Processor is Million times more than taken by this processor built on an FPGA.
{"title":"An RTL Verilog processor","authors":"H. Jamal, S. Khan, F. Hameed, S. Saeed, M. Pasha","doi":"10.1109/ICM.2003.238298","DOIUrl":"https://doi.org/10.1109/ICM.2003.238298","url":null,"abstract":"This paper presents a processor that efficiently executes Verilog code written at Register Transfer Level (RTL). It is a RISC type processor that performs the parallel execution of multiple procedural blocks of Verilog HDL. This results in a very significant saving of simulation time. The simulation time taken by the software based simulation in terms of clock cycles on a normal Pentium Processor is Million times more than taken by this processor built on an FPGA.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133344240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The behavior of the Four-Phase Twisted-Ring Counter (4P-TRC) circuit is analyzed. The circuit produces four individual phased clock signals that exercise a phase difference equal to the half period of the clock. A tree-like structure is built by applying the phased outputs of the circuit to the clock inputs of four replicas of the circuit in order to extend its behavior. The EXOR4 gate is used to define a mirroring structure attached to the 4P-TRC structure such that a primitive/expanded counter configuration is formed. A fundamental concept being described by the transposition mechanism of the EXOR operator is incorporated to the above configuration such that the phase association of interconnecting signals is preserved.
{"title":"The Four-Phase Twisted-Ring Counter circuit","authors":"S. Poriazis","doi":"10.1109/ICM.2003.238497","DOIUrl":"https://doi.org/10.1109/ICM.2003.238497","url":null,"abstract":"The behavior of the Four-Phase Twisted-Ring Counter (4P-TRC) circuit is analyzed. The circuit produces four individual phased clock signals that exercise a phase difference equal to the half period of the clock. A tree-like structure is built by applying the phased outputs of the circuit to the clock inputs of four replicas of the circuit in order to extend its behavior. The EXOR4 gate is used to define a mirroring structure attached to the 4P-TRC structure such that a primitive/expanded counter configuration is formed. A fundamental concept being described by the transposition mechanism of the EXOR operator is incorporated to the above configuration such that the phase association of interconnecting signals is preserved.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116416965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The sub-micron regime has caused the interconnect delay to become a critical determiner of circuit performance. As a result, circuit placement is starting to play an important role in today's high performance chip designs. In addition to wirelength optimization, the issue of reducing excessive congestion in local regions such that the router can finish the routing successfully is becoming another important problem. In this paper, a post-processing congestion reduction technique is implemented and incorporated into the flat and hierarchical placement. Results obtained show that the congestion-driven placement approach reduces the congestion by about 51% for flat designs and 37% for hierarchical designs with a slight increase in wirelength.
{"title":"Congestion driven placement for VLSI standard cell design","authors":"S. Areibi, Zhen Yang","doi":"10.1109/ICM.2003.237880","DOIUrl":"https://doi.org/10.1109/ICM.2003.237880","url":null,"abstract":"The sub-micron regime has caused the interconnect delay to become a critical determiner of circuit performance. As a result, circuit placement is starting to play an important role in today's high performance chip designs. In addition to wirelength optimization, the issue of reducing excessive congestion in local regions such that the router can finish the routing successfully is becoming another important problem. In this paper, a post-processing congestion reduction technique is implemented and incorporated into the flat and hierarchical placement. Results obtained show that the congestion-driven placement approach reduces the congestion by about 51% for flat designs and 37% for hierarchical designs with a slight increase in wirelength.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116705428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Frequency Synthesizers (FS) are used in a wide range of RF applications. The narrow-band FM transceivers are usually used in mobile communication network e.g. (AMPS) and public safety applications, which employ a huge number of channels in a limited bandwidth. In such applications, it is required to have a stable local oscillator (LO) signal with minimum phase noise, in order to avoid the channel interference. In this paper we present a design of a low-power low-noise integrated FS, which can be used for such applications. The circuit is capable of digitally selecting one out of 400 channels, which are closely spaced by narrow windows (25 kHz). The FS circuit is based on the charge pump phase-locked-loop (PLL) architecture. In order to cope with switching phase noise problems, we employ a programmable dual modulus divider (DMD) with a differential input prescaler and a low phase-noise LC tunable voltage controlled oscillator (VCO). We also make use of a dead-zone free phase frequency detector (PFD) with output charge pump (CP) and a third order passive loop filter. The FS is fully integrated using 0.8-micron CMOS technology on a single chip operating at 3.3 V. Being designed for narrow-band FM transceivers (operating at about 100 MHz), the single coil used in the VCO and the loop filter are placed off chip, for high-Q considerations. The integrated FS occupies 1 mm/sup 2/ areas and consumes only 6 mW. The phase noise is about -95 dBc/Hz at 25 kHz, and -122 dBc/Hz at 100 kHz.
{"title":"Design and implementation of a low-phase-noise integrated CMOS Frequency Synthesizer for high-sensitivity narrow-band FM transceivers","authors":"M. Kamal, E.W. El-Shewekh, M. El-Saba","doi":"10.1109/ICM.2003.238559","DOIUrl":"https://doi.org/10.1109/ICM.2003.238559","url":null,"abstract":"Frequency Synthesizers (FS) are used in a wide range of RF applications. The narrow-band FM transceivers are usually used in mobile communication network e.g. (AMPS) and public safety applications, which employ a huge number of channels in a limited bandwidth. In such applications, it is required to have a stable local oscillator (LO) signal with minimum phase noise, in order to avoid the channel interference. In this paper we present a design of a low-power low-noise integrated FS, which can be used for such applications. The circuit is capable of digitally selecting one out of 400 channels, which are closely spaced by narrow windows (25 kHz). The FS circuit is based on the charge pump phase-locked-loop (PLL) architecture. In order to cope with switching phase noise problems, we employ a programmable dual modulus divider (DMD) with a differential input prescaler and a low phase-noise LC tunable voltage controlled oscillator (VCO). We also make use of a dead-zone free phase frequency detector (PFD) with output charge pump (CP) and a third order passive loop filter. The FS is fully integrated using 0.8-micron CMOS technology on a single chip operating at 3.3 V. Being designed for narrow-band FM transceivers (operating at about 100 MHz), the single coil used in the VCO and the loop filter are placed off chip, for high-Q considerations. The integrated FS occupies 1 mm/sup 2/ areas and consumes only 6 mW. The phase noise is about -95 dBc/Hz at 25 kHz, and -122 dBc/Hz at 100 kHz.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126607196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The object-oriented design methodology has been manipulated to model the standard CMOS fabrication technology. Detecting and characterizing the objects and classes within the basic object-oriented features of encapsulation, inheritance and polymorphism, as well as discussing the model framework and model characterization has been the main pursuits of this works. This modeling approach puts forth the chance of a fully automated fabrication system, with well-characterized hardware and reusable software. This model is also a promising candidate for enhancing the system performance to the minimum level required for fully integrated agent-oriented entities, which can reconfigure themselves for future technology generations.
{"title":"An object-oriented design paradigm for standard CMOS fabrication technology","authors":"B. Hekmatshoar, C. Lucas","doi":"10.1109/ICM.2003.237931","DOIUrl":"https://doi.org/10.1109/ICM.2003.237931","url":null,"abstract":"The object-oriented design methodology has been manipulated to model the standard CMOS fabrication technology. Detecting and characterizing the objects and classes within the basic object-oriented features of encapsulation, inheritance and polymorphism, as well as discussing the model framework and model characterization has been the main pursuits of this works. This modeling approach puts forth the chance of a fully automated fabrication system, with well-characterized hardware and reusable software. This model is also a promising candidate for enhancing the system performance to the minimum level required for fully integrated agent-oriented entities, which can reconfigure themselves for future technology generations.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124303127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this article, we discussed a digital compensation technique to improve the transient response of the comb drive actuator. Linear comb actuator are very important MEMS structures that are widely used in many applications.
{"title":"Characterization of digitally compensated, large displacement comb drive","authors":"M. S. Mahmoud, D. Khalil, M. El-Hagry, M. Badr","doi":"10.1109/ICM.2003.237833","DOIUrl":"https://doi.org/10.1109/ICM.2003.237833","url":null,"abstract":"In this article, we discussed a digital compensation technique to improve the transient response of the comb drive actuator. Linear comb actuator are very important MEMS structures that are widely used in many applications.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123453867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A digitally controlled balanced output transconductor (DCBOTA) is proposed and analyzed. The proposed DCBOTA is based on the BOTA given and MOS switches. The DCBOTA transconductance is tunable in a range of 2/sup n-1/ times using n bits control word. A wide band digitally controlled variable gain amplifier (DCVGA) and a six order lowpass filter based on the DCBOTA are presented. The proposed filter has the advantage of independent control of gain and cutoff frequency. Simulations results are included to verify the analysis.
{"title":"Digitally controlled balanced output transconductor: CMOS realization and applications","authors":"S. Mahmoud, I. A. Awad","doi":"10.1109/ICM.2003.238615","DOIUrl":"https://doi.org/10.1109/ICM.2003.238615","url":null,"abstract":"A digitally controlled balanced output transconductor (DCBOTA) is proposed and analyzed. The proposed DCBOTA is based on the BOTA given and MOS switches. The DCBOTA transconductance is tunable in a range of 2/sup n-1/ times using n bits control word. A wide band digitally controlled variable gain amplifier (DCVGA) and a six order lowpass filter based on the DCBOTA are presented. The proposed filter has the advantage of independent control of gain and cutoff frequency. Simulations results are included to verify the analysis.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122738155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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