A test structure to characterize CMOS APS image sensor is presented. Individual photodiodes and pixels as well as an image sensor array of 64/spl times/64 active pixels with selectable linear or logarithmic operation modes are designed. A test chip includes these features in addition to on-chip timing and control digital circuits as well as correlated double sampling have been built on a 0.6 /spl mu/m CMOS process. The test methodology and preliminary simulation results are presented.
提出了一种CMOS APS图像传感器的测试结构。设计了单独的光电二极管和像素以及64/spl倍/64个有源像素的图像传感器阵列，具有可选的线性或对数操作模式。除了片上时序和控制数字电路以及相关双采样外，测试芯片还包括这些功能，这些功能已建立在0.6 /spl μ m CMOS工艺上。给出了试验方法和初步仿真结果。
{"title":"A test structure for characterization of CMOS APS","authors":"T. Elkhatib, S. Moussa, H. Ragaie, H. Haddara","doi":"10.1109/ICM.2003.238501","DOIUrl":"https://doi.org/10.1109/ICM.2003.238501","url":null,"abstract":"A test structure to characterize CMOS APS image sensor is presented. Individual photodiodes and pixels as well as an image sensor array of 64/spl times/64 active pixels with selectable linear or logarithmic operation modes are designed. A test chip includes these features in addition to on-chip timing and control digital circuits as well as correlated double sampling have been built on a 0.6 /spl mu/m CMOS process. The test methodology and preliminary simulation results are presented.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128363475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A 5 mW 4th order SC bandpass sigma-delta modulator is designed in 0.8-/spl mu/m CMOS process. An SNDR of 64.8 dB over 200 kHz, and image-rejection better than 80 dB are achieved by adapting double-sampling technique in circulating-delay-type resonator. The resonator is built using a high performance gain-boosted folded-cascode opamp. An improved SC-CMFB circuit is proposed to support double-sampling requirements. The opamp achieves 106 dB of DC gain, 180 MHz GBW with 750 mA at 3 V supply.
{"title":"5 mW, 64 dB SNDR, 4/sup th/ order bandpass /spl Sigma//spl Delta/ modulator for 10.7 MHz digital IF","authors":"A. Noman, K. Sharaf, H. Ragai","doi":"10.1109/ICM.2003.238425","DOIUrl":"https://doi.org/10.1109/ICM.2003.238425","url":null,"abstract":"A 5 mW 4th order SC bandpass sigma-delta modulator is designed in 0.8-/spl mu/m CMOS process. An SNDR of 64.8 dB over 200 kHz, and image-rejection better than 80 dB are achieved by adapting double-sampling technique in circulating-delay-type resonator. The resonator is built using a high performance gain-boosted folded-cascode opamp. An improved SC-CMFB circuit is proposed to support double-sampling requirements. The opamp achieves 106 dB of DC gain, 180 MHz GBW with 750 mA at 3 V supply.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131053167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The boundary scan (BS) technique offers a convenient alternative to physical probing. This paper presents new boundary scan architecture for Built-In Self-Test (BIST). The Boundary Scan Register (BSR) input cells have been configured to operate as a Test Pattern Generator (TPG) in the BIST mode. The BSR output cells have been configured to operate as a Multi-Input Shift Register (MISR) In the BIST mode. The Test Access Port Controller (TAPC) controls the BIST process. Instructions for BIST process are proposed. This configuration supports the BIST for both the Built-In Logic Block Observer (BILBO) register and the register transfer level. This design Implemented on the Field Programmable Gate Array (FPGA) Spartan X2C200 family.
{"title":"Design and implementation of an new Built-In Self-Test boundary scan architecture","authors":"M. El-Mahlawy, E.A. El-Sehely, A. Ragab, S. Anas","doi":"10.1109/ICM.2003.238299","DOIUrl":"https://doi.org/10.1109/ICM.2003.238299","url":null,"abstract":"The boundary scan (BS) technique offers a convenient alternative to physical probing. This paper presents new boundary scan architecture for Built-In Self-Test (BIST). The Boundary Scan Register (BSR) input cells have been configured to operate as a Test Pattern Generator (TPG) in the BIST mode. The BSR output cells have been configured to operate as a Multi-Input Shift Register (MISR) In the BIST mode. The Test Access Port Controller (TAPC) controls the BIST process. Instructions for BIST process are proposed. This configuration supports the BIST for both the Built-In Logic Block Observer (BILBO) register and the register transfer level. This design Implemented on the Field Programmable Gate Array (FPGA) Spartan X2C200 family.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123182771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. R. Rahman Khan, M. M. Shahidul Hassan, T. Rahman
A new and compact formula for the base transit time, /spl tau//sub b/, of a modern high speed npn bipolar transistor with exponential base doping profile is derived. The present treatment includes doping dependence of mobility, bandgap narrowing effect, high injection effect and carrier velocity saturation at the base edge of the collector-base junction The derivation is not based on the charge control concept, but shows how current and charge depend on minority carrier concentration, which in turn are function of junction voltage. The expression is applicable for arbitrary injection before the onset of Kirk effect and it is simple and straight forward to give insight into device operation. The base transit time calculated analytically is compared with numerical results in order to demonstrate the validity of the assumptions made in deriving the expression.
{"title":"New expression for base transit time in an exponentially doped base bipolar transistor for all levels of injection","authors":"M. R. Rahman Khan, M. M. Shahidul Hassan, T. Rahman","doi":"10.1109/ICM.2003.237928","DOIUrl":"https://doi.org/10.1109/ICM.2003.237928","url":null,"abstract":"A new and compact formula for the base transit time, /spl tau//sub b/, of a modern high speed npn bipolar transistor with exponential base doping profile is derived. The present treatment includes doping dependence of mobility, bandgap narrowing effect, high injection effect and carrier velocity saturation at the base edge of the collector-base junction The derivation is not based on the charge control concept, but shows how current and charge depend on minority carrier concentration, which in turn are function of junction voltage. The expression is applicable for arbitrary injection before the onset of Kirk effect and it is simple and straight forward to give insight into device operation. The base transit time calculated analytically is compared with numerical results in order to demonstrate the validity of the assumptions made in deriving the expression.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122304987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a floating-point multiplier with high speed and area efficient is presented. The multiplier is designed, optimized, and implemented on an FPGA based system. A comparison between the results of the proposed design and a previously reported one is provided. The effect of rounding on the area, speed, and accuracy for three different configurations is examined.
{"title":"High-speed, area-efficient FPGA-based floating-point multiplier","authors":"G. Aty, A. Hussein, I. Ashour, M. Mones","doi":"10.1109/ICM.2003.237828","DOIUrl":"https://doi.org/10.1109/ICM.2003.237828","url":null,"abstract":"In this paper, a floating-point multiplier with high speed and area efficient is presented. The multiplier is designed, optimized, and implemented on an FPGA based system. A comparison between the results of the proposed design and a previously reported one is provided. The effect of rounding on the area, speed, and accuracy for three different configurations is examined.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115971394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Quoc-Hoang Duong, Trung‐Kien Nguyen, H. Duong, Sang-Gug Lee
A new CMOS exponential V-I converter (EVIC), based on Taylor's concept and using NMOS transistor, is presented in this paper. The proposed-modified Taylor series expansion is used to extend the dB-linear output current range. In a 0.25 /spl mu/m CMOS process, the simulations show more than 22 dB output current range and 17 dB linear range with the linearity error less than /spl plusmn/0.5 dB. The power dissipation is less than 0.3 mW with /spl plusmn/1.5 V supply voltage. The proposed EVIC can be used for the design of an extremely low-voltage and low-power variable gain amplifier (VGA) and automatic gain control (AGC).
{"title":"dB-linear V-I converter using composite NMOS transistor","authors":"Quoc-Hoang Duong, Trung‐Kien Nguyen, H. Duong, Sang-Gug Lee","doi":"10.1109/ICM.2003.238249","DOIUrl":"https://doi.org/10.1109/ICM.2003.238249","url":null,"abstract":"A new CMOS exponential V-I converter (EVIC), based on Taylor's concept and using NMOS transistor, is presented in this paper. The proposed-modified Taylor series expansion is used to extend the dB-linear output current range. In a 0.25 /spl mu/m CMOS process, the simulations show more than 22 dB output current range and 17 dB linear range with the linearity error less than /spl plusmn/0.5 dB. The power dissipation is less than 0.3 mW with /spl plusmn/1.5 V supply voltage. The proposed EVIC can be used for the design of an extremely low-voltage and low-power variable gain amplifier (VGA) and automatic gain control (AGC).","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"11 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116780205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents hardware development and implementation of an algorithm for object tracking. The presented parallel hardware implementation is necessary for real time tracking. The parallelism has been accomplished by implementing the computational-intensive Block Matching Algorithm (BMA) via a semisystolic array of non-programmable Processor Elements (PEs). This paper also, describes an efficient architecture for maximum repetition module for calculating the moving object centroid and its motion vector. The design is described using Synthesizable VHDL code under Xilinx foundation series 2.1, CAD environment.
{"title":"Hardware development and implementation of an object tracking algorithm","authors":"I. Mahmoud, H.A. Abd El-Halym, S. Habib","doi":"10.1109/ICM.2003.237926","DOIUrl":"https://doi.org/10.1109/ICM.2003.237926","url":null,"abstract":"This paper presents hardware development and implementation of an algorithm for object tracking. The presented parallel hardware implementation is necessary for real time tracking. The parallelism has been accomplished by implementing the computational-intensive Block Matching Algorithm (BMA) via a semisystolic array of non-programmable Processor Elements (PEs). This paper also, describes an efficient architecture for maximum repetition module for calculating the moving object centroid and its motion vector. The design is described using Synthesizable VHDL code under Xilinx foundation series 2.1, CAD environment.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131917687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The flexibility of field programmable gate arrays (FPGAs) can provide arithmetic intensive applications with the benefites of custom hardware but without the high cost of custom silicon implementations. In this paper present the adaptation of radix 2 division algorithm for lookup table based FPGAs implementation. This division algorithm is well suited for IEEE 754 standard operands belonging to the range. The implementation has been done with xilinx technology and FPGA-Advantage CAD tools.
{"title":"FPGA implementation of radix 2 division with over-redundant quotient selection","authors":"A. A. Ibrahem, H. Elsimary, A. Salama","doi":"10.1109/ICM.2003.237827","DOIUrl":"https://doi.org/10.1109/ICM.2003.237827","url":null,"abstract":"The flexibility of field programmable gate arrays (FPGAs) can provide arithmetic intensive applications with the benefites of custom hardware but without the high cost of custom silicon implementations. In this paper present the adaptation of radix 2 division algorithm for lookup table based FPGAs implementation. This division algorithm is well suited for IEEE 754 standard operands belonging to the range. The implementation has been done with xilinx technology and FPGA-Advantage CAD tools.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"70 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124841702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we propose a novel Viterbi decoder core. This core is optimized to minimize the decoding latency, which is an important factor for real time multimedia applications. The new core has the same complexity as the conventional cores and it achieves the same performance.
{"title":"A Viterbi decoder core with no trace-back unit","authors":"A. Shebaita, M. Khairy, A. Salama, M. Ashour","doi":"10.1109/ICM.2003.237969","DOIUrl":"https://doi.org/10.1109/ICM.2003.237969","url":null,"abstract":"In this paper, we propose a novel Viterbi decoder core. This core is optimized to minimize the decoding latency, which is an important factor for real time multimedia applications. The new core has the same complexity as the conventional cores and it achieves the same performance.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131932162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a new approach to on-line fault tolerance via reconfiguration for the systems mapped onto field programmable gate arrays (FPGAs). The fault detection, based on self-checking technique, is introduced at application level, therefore our approach can detect the faults in the FPGAs concurrently with the normal system work. A grid of tiles is projected on the FPGA structure and a certain number of spare configurable logic blocks (CLBs) is reserved inside every tile. Unlike fixed structure fault-tolerance techniques for ASICs and microprocessors. this approach allows a single physical component to provide redundant backup for several types of components. The reliability gain of the proposed solution was evaluated using basic reliability parameter, whose values were computed for different alternatives of the solution.
{"title":"Embedding fault tolerance via reconfiguration in configurable systems","authors":"K. Elshafey","doi":"10.1109/ICM.2003.237968","DOIUrl":"https://doi.org/10.1109/ICM.2003.237968","url":null,"abstract":"This paper presents a new approach to on-line fault tolerance via reconfiguration for the systems mapped onto field programmable gate arrays (FPGAs). The fault detection, based on self-checking technique, is introduced at application level, therefore our approach can detect the faults in the FPGAs concurrently with the normal system work. A grid of tiles is projected on the FPGA structure and a certain number of spare configurable logic blocks (CLBs) is reserved inside every tile. Unlike fixed structure fault-tolerance techniques for ASICs and microprocessors. this approach allows a single physical component to provide redundant backup for several types of components. The reliability gain of the proposed solution was evaluated using basic reliability parameter, whose values were computed for different alternatives of the solution.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128364143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：