D. Shahrjerdi, B. Hekmatshoar, M. Talaie, O. Shoaei
A fast settling, low power, high dynamic range OPAMP with a DC gain of 96 dB has been designed. Simulations have been performed in 0.35 /spl mu/m CMOS technology for slow, nominal and fast models. High DC gain has been achieved by adding gain boosting active blocks to the main OPAMP. In this design, a telescopic OTA has been chosen as the main opamp due to its fast settling and low power advantages, as well as the gain boosting OPAMPs. Transient simulation indicates a settling time of 17ns for a global feedback with /spl beta/= 1/2 . Although telescopic OPAMPs suffer from inherent low output voltage swing, a dynamic range of 83 dB has been achieved in this design. A power consumption of 4.1 mW is obtained for the total circuit including the main OPAMP, gain boosters and the bias circuitry.
{"title":"A fast settling, high DC gain, low power OPAMP design for high resolution, high speed A/D converters","authors":"D. Shahrjerdi, B. Hekmatshoar, M. Talaie, O. Shoaei","doi":"10.1109/ICM.2003.238614","DOIUrl":"https://doi.org/10.1109/ICM.2003.238614","url":null,"abstract":"A fast settling, low power, high dynamic range OPAMP with a DC gain of 96 dB has been designed. Simulations have been performed in 0.35 /spl mu/m CMOS technology for slow, nominal and fast models. High DC gain has been achieved by adding gain boosting active blocks to the main OPAMP. In this design, a telescopic OTA has been chosen as the main opamp due to its fast settling and low power advantages, as well as the gain boosting OPAMPs. Transient simulation indicates a settling time of 17ns for a global feedback with /spl beta/= 1/2 . Although telescopic OPAMPs suffer from inherent low output voltage swing, a dynamic range of 83 dB has been achieved in this design. A power consumption of 4.1 mW is obtained for the total circuit including the main OPAMP, gain boosters and the bias circuitry.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"106 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120874105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A single-poly floating gate non volatile memory cell is presented. In this device the second poly layer is removed to make the device compatible with standard logic CMOS process. An array of cells with high storage density has been fabricated on a standard 0.25 /spl mu/m CMOS process with a special architecture. All memory cells tolerate 60000 cycles of endurance test and show 10 years of data retention. Using this cell, a small to medium size (typically 64 K*8b) Flash EEPROM array would be integrated in standard logic CMOS process.
提出了一种单聚浮栅非易失性存储单元。在该器件中，为了使器件与标准逻辑CMOS工艺兼容，将第二多晶硅层去除。采用标准的0.25 /spl μ m CMOS工艺，采用特殊的结构，制备了具有高存储密度的电池阵列。所有的记忆单元都能承受60000次的耐久性测试，并能保持10年的数据。使用该单元，一个小到中等尺寸(通常为64k *8b)的闪存EEPROM阵列将集成在标准逻辑CMOS工艺中。
{"title":"A logic CMOS compatible Flash EEPROM for small scale integration","authors":"M. Shalchian, S. M. Atarodi","doi":"10.1109/ICM.2003.237930","DOIUrl":"https://doi.org/10.1109/ICM.2003.237930","url":null,"abstract":"A single-poly floating gate non volatile memory cell is presented. In this device the second poly layer is removed to make the device compatible with standard logic CMOS process. An array of cells with high storage density has been fabricated on a standard 0.25 /spl mu/m CMOS process with a special architecture. All memory cells tolerate 60000 cycles of endurance test and show 10 years of data retention. Using this cell, a small to medium size (typically 64 K*8b) Flash EEPROM array would be integrated in standard logic CMOS process.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"2019 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133007925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a new CMOS output buffer with low switching noise and load adaptability is presented. Instead of using current source, the current limiter is proposed to reduce switching noise and the static power dissipation. The output ringing is lowered by automatically turning off one driving stage near the end of the output transition. Compared with the previous designs, the proposed buffer has less switching noise and optimized output ringing and speed. Without the feedback control circuit, the proposed method is simple and easy to be implemented.
{"title":"Design of a new CMOS output buffer with low switching noise","authors":"L. Yang, J. Yuan","doi":"10.1109/ICM.2003.238496","DOIUrl":"https://doi.org/10.1109/ICM.2003.238496","url":null,"abstract":"In this paper, a new CMOS output buffer with low switching noise and load adaptability is presented. Instead of using current source, the current limiter is proposed to reduce switching noise and the static power dissipation. The output ringing is lowered by automatically turning off one driving stage near the end of the output transition. Compared with the previous designs, the proposed buffer has less switching noise and optimized output ringing and speed. Without the feedback control circuit, the proposed method is simple and easy to be implemented.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132051809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
There exist a number of algorithms for minimization of MVL functions. The main objective is to produce near minimal expressions for MVL functions at an affordable cost (measured in terms of CPU time). Among the proposed heuristic-based techniques, direct cover-based techniques have received the most attention. In this paper, we analyze two of the existing direct cover techniques in terms of the number of implicants needed to synthesize a given function. We introduce five modified techniques and analyze them as well. An overall comparison is conducted among the existing and the proposed techniques. The analysis is based on performance measures of these techniques for 50,000 2-variable 4-valued and 21,000 2-variable 5-valued randomly selected functions. The analysis shows that algorithm DM/spl I.bar/MIN-2 outperforms all other considered algorithms. The algorithm introduced by Besslich is outperformed by all considered algorithms.
{"title":"Analysis of direct cover algorithms for minimization of MVL functions","authors":"M. Abd-El-Barr, L. Al-Awami","doi":"10.1109/ICM.2003.237881","DOIUrl":"https://doi.org/10.1109/ICM.2003.237881","url":null,"abstract":"There exist a number of algorithms for minimization of MVL functions. The main objective is to produce near minimal expressions for MVL functions at an affordable cost (measured in terms of CPU time). Among the proposed heuristic-based techniques, direct cover-based techniques have received the most attention. In this paper, we analyze two of the existing direct cover techniques in terms of the number of implicants needed to synthesize a given function. We introduce five modified techniques and analyze them as well. An overall comparison is conducted among the existing and the proposed techniques. The analysis is based on performance measures of these techniques for 50,000 2-variable 4-valued and 21,000 2-variable 5-valued randomly selected functions. The analysis shows that algorithm DM/spl I.bar/MIN-2 outperforms all other considered algorithms. The algorithm introduced by Besslich is outperformed by all considered algorithms.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132944117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a detailed temporal analysis of two-step switched current (S/sup 2/I) memory cells. Also, a new design of an SI current copier operating with a single 1V supply is presented. The analysis and design are supported and validated by SPICE simulations using 0.25 /spl mu/m CMOS process parameters.
本文对两步开关电流(S/sup 2/I)存储单元进行了详细的时序分析。此外，本文还提出了一种单电源1V的SI电流复制器的新设计。采用0.25 /spl μ m CMOS工艺参数的SPICE仿真验证了分析和设计的正确性。
{"title":"Analysis and design of low-voltage CMOS current memory cells using switched current techniques","authors":"Y. Aki, M. El-Sayed, A. K. Aboul-Seoud","doi":"10.1109/ICM.2003.238305","DOIUrl":"https://doi.org/10.1109/ICM.2003.238305","url":null,"abstract":"This paper presents a detailed temporal analysis of two-step switched current (S/sup 2/I) memory cells. Also, a new design of an SI current copier operating with a single 1V supply is presented. The analysis and design are supported and validated by SPICE simulations using 0.25 /spl mu/m CMOS process parameters.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132698205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Chung, S. Fu, T. Lin, A. Lu, M. Ho, D. Kuo, S. Chou
In this paper, a study on the relationship between UV cured die-attach film (UVDAF) characterizes, process design, and the failure mechanism of reliability test were reported. The novelty films were a multifunctional tape, which consists of the function for dicing tape and die bonding tape. It focused on investigation of the behavior under the JEDEC level 3 precondition conditions, pressure cook test (PCT) and thermal cycle test (TCT). Besides, the paper discusses the thermal history effect on the chemical stability of UVDAF for the reliability issue. For instance, initial crosslinkage temperature of UVDAF affect on effectually contact area after the die-mount process. The cure kinetic and thermal resistances of the UVDAF were analyzed by Differential Scanning Calorimetry (DSC) and Thermo gravimetric Analysis (TGA). The delamination surfaces were analysis by Scanning Acoustic Tomograph (SAT), Cross-section were scanned by electronic microscopy (SEM) and Optical Microscope (OM). The thermo-deformation and pressure-induced flow behaviors of UVDAF were evaluated by both penetration mode in Thermal Mechanical Analyzers (TMA) and dynamic mode in rheology test, respectively. Furthermore, OM and SEM results revealed that the chemical stability of UVDAF in process, from die-mount to molding, affect the final effectually adhesive area that obviously influenced the quality of stack CSP reliability.
{"title":"A study on the characteristic of UV curved die-attach films in stack CSP (Chip Scale Package)","authors":"C. Chung, S. Fu, T. Lin, A. Lu, M. Ho, D. Kuo, S. Chou","doi":"10.1109/ICM.2003.237967","DOIUrl":"https://doi.org/10.1109/ICM.2003.237967","url":null,"abstract":"In this paper, a study on the relationship between UV cured die-attach film (UVDAF) characterizes, process design, and the failure mechanism of reliability test were reported. The novelty films were a multifunctional tape, which consists of the function for dicing tape and die bonding tape. It focused on investigation of the behavior under the JEDEC level 3 precondition conditions, pressure cook test (PCT) and thermal cycle test (TCT). Besides, the paper discusses the thermal history effect on the chemical stability of UVDAF for the reliability issue. For instance, initial crosslinkage temperature of UVDAF affect on effectually contact area after the die-mount process. The cure kinetic and thermal resistances of the UVDAF were analyzed by Differential Scanning Calorimetry (DSC) and Thermo gravimetric Analysis (TGA). The delamination surfaces were analysis by Scanning Acoustic Tomograph (SAT), Cross-section were scanned by electronic microscopy (SEM) and Optical Microscope (OM). The thermo-deformation and pressure-induced flow behaviors of UVDAF were evaluated by both penetration mode in Thermal Mechanical Analyzers (TMA) and dynamic mode in rheology test, respectively. Furthermore, OM and SEM results revealed that the chemical stability of UVDAF in process, from die-mount to molding, affect the final effectually adhesive area that obviously influenced the quality of stack CSP reliability.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131440580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B.S. Makki, M. Kargar, S. Mohajerzadeh, T. Maleki, D. Shahrjerdi
Polycrystalline germanium-based thermopiles are fabricated at reduced temperatures on plastic substrate. The Amorphous Ge film, deposited using electron beam evaporation, is post-treated to form a polycrystalline film. The annealing process has been performed at temperatures ranging from 120 to 175/spl deg/C. The physical characteristics of Ge films have been investigated using XRD and SEM tools confirming the crystallinity of the annealed films. A Seebeck value of 100 /spl mu/V//spl deg/C is extracted for the Ge-Al junctions. A novel ultraviolet assisted micro-machining is presented in which anisotropic etching of PET plastic substrate is achieved. The etching of plastic is performed in a DMF solution and in presence of ultraviolet light illumination with a typical intensity of 15 mW/hr measured at a wavelength of 360 nm. This technique has been applied to realize square membrane, craters, micro-gears and micro-molds.
{"title":"Application of PET plastics in micro-sensor fabrication","authors":"B.S. Makki, M. Kargar, S. Mohajerzadeh, T. Maleki, D. Shahrjerdi","doi":"10.1109/ICM.2003.237932","DOIUrl":"https://doi.org/10.1109/ICM.2003.237932","url":null,"abstract":"Polycrystalline germanium-based thermopiles are fabricated at reduced temperatures on plastic substrate. The Amorphous Ge film, deposited using electron beam evaporation, is post-treated to form a polycrystalline film. The annealing process has been performed at temperatures ranging from 120 to 175/spl deg/C. The physical characteristics of Ge films have been investigated using XRD and SEM tools confirming the crystallinity of the annealed films. A Seebeck value of 100 /spl mu/V//spl deg/C is extracted for the Ge-Al junctions. A novel ultraviolet assisted micro-machining is presented in which anisotropic etching of PET plastic substrate is achieved. The etching of plastic is performed in a DMF solution and in presence of ultraviolet light illumination with a typical intensity of 15 mW/hr measured at a wavelength of 360 nm. This technique has been applied to realize square membrane, craters, micro-gears and micro-molds.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122830572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The design and implementation of a gm-C complex filter for low-IF WLAN is described. Fifth-order transitional complex Bessel-Chebyshev filter is implemented to compromise between high attenuation and low group-delay variation. The circuit is fabricated using 0.18 /spl mu/m CMOS process. Measured results show that the filter provides 30 dB to 40 dB image rejection and 18 dB adjacent channel rejection, while keeping a low group-delay variation of below 6.0ns within the pass-band. High frequency and wide bandwidth filter also requires stringent design specification of the circuitries. Differential inverter transconductor is optimized for this gm-C continuous-time filter design. The complete filter including on-chip tuning circuit and bandgap consumes only 7.5 mA with 1.8 V single supply voltage.
{"title":"Gm-C complex transitional filter for low-IF wireless LAN application","authors":"T. Teo, E. Khoo, D. Uday","doi":"10.1109/ICM.2003.238424","DOIUrl":"https://doi.org/10.1109/ICM.2003.238424","url":null,"abstract":"The design and implementation of a gm-C complex filter for low-IF WLAN is described. Fifth-order transitional complex Bessel-Chebyshev filter is implemented to compromise between high attenuation and low group-delay variation. The circuit is fabricated using 0.18 /spl mu/m CMOS process. Measured results show that the filter provides 30 dB to 40 dB image rejection and 18 dB adjacent channel rejection, while keeping a low group-delay variation of below 6.0ns within the pass-band. High frequency and wide bandwidth filter also requires stringent design specification of the circuitries. Differential inverter transconductor is optimized for this gm-C continuous-time filter design. The complete filter including on-chip tuning circuit and bandgap consumes only 7.5 mA with 1.8 V single supply voltage.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128138808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work. we review the evolution of hardware description languages. We describe the recent needs concerning platform based design. the challenges of the introduction of intellectual property block, the ever increasing part of software components in a digital systems and its impact on the evolution of modeling capabilities. We review the features of object oriented methodologies in dealing with these challenges and in providing design reuse capabilities as well as safe-modeling of hardware/software systems.
{"title":"Recent trends in hardware/software description languages","authors":"E. Aboulhamid, J. Lapalme","doi":"10.1109/ICM.2003.238562","DOIUrl":"https://doi.org/10.1109/ICM.2003.238562","url":null,"abstract":"In this work. we review the evolution of hardware description languages. We describe the recent needs concerning platform based design. the challenges of the introduction of intellectual property block, the ever increasing part of software components in a digital systems and its impact on the evolution of modeling capabilities. We review the features of object oriented methodologies in dealing with these challenges and in providing design reuse capabilities as well as safe-modeling of hardware/software systems.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116622713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Gihan, Sayah, Abdel Halim A. Zekry, Hani F. Ragaie, Fouad A. Soliman
In this work a new SCR model is developed by applying the Gummel-Poon circuit model to the two-transistor configuration. This model naturally takes into consideration the high injection effects. Conductivity modulation is taken into consideration by using nonlinear current sources. The model parameters are defined and extracted according to a new methodology. The simulation results are compared with the measured results. The developed model satisfactorily describes the performance of the thyristor under practical operating conditions.
{"title":"A SPICE model of a thyristor with high injection effects and conductivity modulation","authors":"Gihan, Sayah, Abdel Halim A. Zekry, Hani F. Ragaie, Fouad A. Soliman","doi":"10.1109/ICM.2003.237929","DOIUrl":"https://doi.org/10.1109/ICM.2003.237929","url":null,"abstract":"In this work a new SCR model is developed by applying the Gummel-Poon circuit model to the two-transistor configuration. This model naturally takes into consideration the high injection effects. Conductivity modulation is taken into consideration by using nonlinear current sources. The model parameters are defined and extracted according to a new methodology. The simulation results are compared with the measured results. The developed model satisfactorily describes the performance of the thyristor under practical operating conditions.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"445 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115938987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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