Partially depleted (PD) SOI devices are now of a major interest in becoming one of the more sought devices for the integration of high-performance low-power radiofrequency applications. Along with this strong interest for PD to jump widely into the application era, some basic but crucial points still need to be thoroughly investigated for the 0.13 /spl mu/m CMOS technology node: the low frequency noise (LFN) and the control of novel excess noise sources as well as the hot-carrier (HC) reliability and new degradation mechanisms.
{"title":"On the low-frequency noise and hot-carrier reliability in 0.13 /spl mu/m Partially depleted SOI MOSFETs","authors":"F. Dieudonné, J. Jomaah, F. Balestra","doi":"10.1109/ICM.2003.237776","DOIUrl":"https://doi.org/10.1109/ICM.2003.237776","url":null,"abstract":"Partially depleted (PD) SOI devices are now of a major interest in becoming one of the more sought devices for the integration of high-performance low-power radiofrequency applications. Along with this strong interest for PD to jump widely into the application era, some basic but crucial points still need to be thoroughly investigated for the 0.13 /spl mu/m CMOS technology node: the low frequency noise (LFN) and the control of novel excess noise sources as well as the hot-carrier (HC) reliability and new degradation mechanisms.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124569489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A one-dimensional semiconductor simulator is implemented. This simulator is able to simulate thin film graded-bandgap semiconductors having position dependent device parameters such as: the energy gap, absorption coefficient, the dielectric constant and other parameters. The simulator is able to calculate the conversion efficiency of the solar cells under normal conditions as well as the limiting efficiency of the cells. It calculates the efficiency by solving the coupled semiconductor equations, namely, Poisson's equation and the current continuity equations together with the Boltzmann photon equation. The non-avoidable bulk losses due to carriers recombination, namely, radiative and Auger, are carefully considered. The photon-recycling effect is carefully taken into account.
{"title":"A numerical simulator for graded-bandgap solar cells","authors":"N. Rafat, A.M. Abdel Haleem, S. Habib","doi":"10.1109/ICM.2003.237832","DOIUrl":"https://doi.org/10.1109/ICM.2003.237832","url":null,"abstract":"A one-dimensional semiconductor simulator is implemented. This simulator is able to simulate thin film graded-bandgap semiconductors having position dependent device parameters such as: the energy gap, absorption coefficient, the dielectric constant and other parameters. The simulator is able to calculate the conversion efficiency of the solar cells under normal conditions as well as the limiting efficiency of the cells. It calculates the efficiency by solving the coupled semiconductor equations, namely, Poisson's equation and the current continuity equations together with the Boltzmann photon equation. The non-avoidable bulk losses due to carriers recombination, namely, radiative and Auger, are carefully considered. The photon-recycling effect is carefully taken into account.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121197742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Interconnecting modules in a SoC platform requires modules compatibility. Several solutions are available, but they either lack the necessary throughput or the flexibility. This paper proposes an interconnection architecture for a flexible on-chip high-performance communication medium that can provide variable bandwidth. It is based on the AHB AMBA bus. The proposed architecture has been implemented in the Seamless environment and laid out using a 0.18 /spl mu/m CMOS with Cadence tools to validate the proposed concept.
{"title":"High-speed system bus for a SoC network processing platform","authors":"J.P. Bissou, M. Dubois, Y. Savaria, G. Bois","doi":"10.1109/ICM.2003.238564","DOIUrl":"https://doi.org/10.1109/ICM.2003.238564","url":null,"abstract":"Interconnecting modules in a SoC platform requires modules compatibility. Several solutions are available, but they either lack the necessary throughput or the flexibility. This paper proposes an interconnection architecture for a flexible on-chip high-performance communication medium that can provide variable bandwidth. It is based on the AHB AMBA bus. The proposed architecture has been implemented in the Seamless environment and laid out using a 0.18 /spl mu/m CMOS with Cadence tools to validate the proposed concept.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126835374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As technology scales deeper into the nanometer regime, leakage Power is one of the main obstacles to Moore's law. This paper provides an overview of leakage current highlighting its major mechanisms. Subthreshold leakage current becomes the major focus of this paper, outlining how it is impacted by technology scaling. The major techniques used to manage leakage current in industry are then addressed.
{"title":"Subthreshold leakage current: challenges and solutions","authors":"M. Anis","doi":"10.1109/ICM.2003.238359","DOIUrl":"https://doi.org/10.1109/ICM.2003.238359","url":null,"abstract":"As technology scales deeper into the nanometer regime, leakage Power is one of the main obstacles to Moore's law. This paper provides an overview of leakage current highlighting its major mechanisms. Subthreshold leakage current becomes the major focus of this paper, outlining how it is impacted by technology scaling. The major techniques used to manage leakage current in industry are then addressed.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126683345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Salah, A. Adel, A. Ezeldin, A. Ali, A. Hussein, S. Habib
This paper introduces a complete design of a static earth sensor, used for satellite attitude determination. Our design approach offers high area efficiency, high resolution (10 arc minutes), and modularity relative to previous designs. This sensor is made up of four separate identical chips; each chip represents a complete System on Chip (SoC) including the following main components: the sensor, the electronic read-out sub-circuit, the decision sub-circuit, and the serial interface to the On-Board Computer (OBC). Each chip has two staggered arrays of MEMS bulk-micromachined thermopiles, which sense the IR radiation incident on the chip and convert it into an electrical voltage. A complete design of the IR detector is introduced and its characteristics are estimated. A novel block diagram of one chip is presented including both analog and digital sub-circuits. A low offset amplifier (LOA), based on the Auto-zeroing technique, is used as a front-end to the analog part of the circuit. Finally, a complete layout or the SoC is given.
{"title":"Design and implementation of an area-efficient MEMS-based IR static earth sensor","authors":"A. Salah, A. Adel, A. Ezeldin, A. Ali, A. Hussein, S. Habib","doi":"10.1109/ICM.2003.238499","DOIUrl":"https://doi.org/10.1109/ICM.2003.238499","url":null,"abstract":"This paper introduces a complete design of a static earth sensor, used for satellite attitude determination. Our design approach offers high area efficiency, high resolution (10 arc minutes), and modularity relative to previous designs. This sensor is made up of four separate identical chips; each chip represents a complete System on Chip (SoC) including the following main components: the sensor, the electronic read-out sub-circuit, the decision sub-circuit, and the serial interface to the On-Board Computer (OBC). Each chip has two staggered arrays of MEMS bulk-micromachined thermopiles, which sense the IR radiation incident on the chip and convert it into an electrical voltage. A complete design of the IR detector is introduced and its characteristics are estimated. A novel block diagram of one chip is presented including both analog and digital sub-circuits. A low offset amplifier (LOA), based on the Auto-zeroing technique, is used as a front-end to the analog part of the circuit. Finally, a complete layout or the SoC is given.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128061720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Multi modulus prescalers based on the phase-switching technique suffer from a spur problem due to the finite phase accuracy. The spur problem is outlined and the spurs locations and magnitudes are derived. Simulations revealing the effect of this problem on integer-N and fractional-N PLL are presented.
{"title":"Phase mismatch in phase switching frequency dividers","authors":"M. El sheikh, A. Hafez","doi":"10.1109/ICM.2003.238423","DOIUrl":"https://doi.org/10.1109/ICM.2003.238423","url":null,"abstract":"Multi modulus prescalers based on the phase-switching technique suffer from a spur problem due to the finite phase accuracy. The spur problem is outlined and the spurs locations and magnitudes are derived. Simulations revealing the effect of this problem on integer-N and fractional-N PLL are presented.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133594960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Madbouly, M. Dessouky, M. Zakaria, R. A. Latif, A. Farid
This paper introduces an interface between MATLAB and SPICE, some of its applications will be introduced and examples on these applications will be illustrated. This interface allows the circuit designer to use all the benefits of the circuit level simulators under the MATLAB environment. This avoids many manual steps done on the simulator. Simulation results are transferred to MATLAB to be analyzed using the powerful MATLAB toolboxes. The scope of the applications of MATSPICE is huge and depends on the circuit designer. The applications in this paper will be in the circuit sizing and in the automatic verification of MATLAB circuit and device models. MATSPICE can be a part of a more general synthesis tool as will be shown in the examples.
{"title":"MATLAB - SPICE interface (MATSPICE) and its applications","authors":"M. Madbouly, M. Dessouky, M. Zakaria, R. A. Latif, A. Farid","doi":"10.1109/ICM.2003.238301","DOIUrl":"https://doi.org/10.1109/ICM.2003.238301","url":null,"abstract":"This paper introduces an interface between MATLAB and SPICE, some of its applications will be introduced and examples on these applications will be illustrated. This interface allows the circuit designer to use all the benefits of the circuit level simulators under the MATLAB environment. This avoids many manual steps done on the simulator. Simulation results are transferred to MATLAB to be analyzed using the powerful MATLAB toolboxes. The scope of the applications of MATSPICE is huge and depends on the circuit designer. The applications in this paper will be in the circuit sizing and in the automatic verification of MATLAB circuit and device models. MATSPICE can be a part of a more general synthesis tool as will be shown in the examples.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115225693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Shahrjerdi, B. Hekmatshoar, M. Talaie, O. Shoaei
A fast settling, low power, high dynamic range OPAMP with a DC gain of 96 dB has been designed. Simulations have been performed in 0.35 /spl mu/m CMOS technology for slow, nominal and fast models. High DC gain has been achieved by adding gain boosting active blocks to the main OPAMP. In this design, a telescopic OTA has been chosen as the main opamp due to its fast settling and low power advantages, as well as the gain boosting OPAMPs. Transient simulation indicates a settling time of 17ns for a global feedback with /spl beta/= 1/2 . Although telescopic OPAMPs suffer from inherent low output voltage swing, a dynamic range of 83 dB has been achieved in this design. A power consumption of 4.1 mW is obtained for the total circuit including the main OPAMP, gain boosters and the bias circuitry.
{"title":"A fast settling, high DC gain, low power OPAMP design for high resolution, high speed A/D converters","authors":"D. Shahrjerdi, B. Hekmatshoar, M. Talaie, O. Shoaei","doi":"10.1109/ICM.2003.238614","DOIUrl":"https://doi.org/10.1109/ICM.2003.238614","url":null,"abstract":"A fast settling, low power, high dynamic range OPAMP with a DC gain of 96 dB has been designed. Simulations have been performed in 0.35 /spl mu/m CMOS technology for slow, nominal and fast models. High DC gain has been achieved by adding gain boosting active blocks to the main OPAMP. In this design, a telescopic OTA has been chosen as the main opamp due to its fast settling and low power advantages, as well as the gain boosting OPAMPs. Transient simulation indicates a settling time of 17ns for a global feedback with /spl beta/= 1/2 . Although telescopic OPAMPs suffer from inherent low output voltage swing, a dynamic range of 83 dB has been achieved in this design. A power consumption of 4.1 mW is obtained for the total circuit including the main OPAMP, gain boosters and the bias circuitry.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"106 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120874105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes and represents different algorithms and efficient implementation of One Dimensional 8 point Discrete Cosine Transform on Field Programmable Gate Arrays. One of the main objectives is to minimize the complexity of operations as much as possible while maintaining low delays and high speed throughput. Distributed Arithmetic is a powerful technique that has been used for fast and efficient implementation of 1D DCT on FPGA.
{"title":"An efficient implementation of the 1D DCT using FPGA technology","authors":"H. El-Banna, A. El-Fattah, W. Fakhr","doi":"10.1109/ICM.2003.237829","DOIUrl":"https://doi.org/10.1109/ICM.2003.237829","url":null,"abstract":"This paper describes and represents different algorithms and efficient implementation of One Dimensional 8 point Discrete Cosine Transform on Field Programmable Gate Arrays. One of the main objectives is to minimize the complexity of operations as much as possible while maintaining low delays and high speed throughput. Distributed Arithmetic is a powerful technique that has been used for fast and efficient implementation of 1D DCT on FPGA.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121023528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Esfandyarpour, S. Mohajerzadeh, A. Khodadadi, B.S. Makki
Thin films of SnO/sub 2/ were prepared by a sol-gel technique using tin tetrachloride (SnCl/sub 4/) and isopropyl alcohol solution. Applying standard lithography process, high sensitivity SnO/sub 2/ gas sensors were miniaturized on macromachined Si(100) substrates. Conductivity measurements of the films annealed at different temperatures have been carried out in dry air and in the presence of 5 ppm to 100 ppm ethanol. Response and recovery times of the sensors annealed at 550/spl deg/C at the optimum operating temperature were found to be about 5 and 40 seconds, respectively. Also sensitivity of the sensors was studied towards 500 ppm CO and 1000 ppm H/sub 2/ at different temperatures, indicating the satisfactory selectivity for ethanol.
{"title":"Thin film SnO/sub 2/-based gas sensors fabricated using sol-gel method for the detection of ethanol","authors":"B. Esfandyarpour, S. Mohajerzadeh, A. Khodadadi, B.S. Makki","doi":"10.1109/ICM.2003.238502","DOIUrl":"https://doi.org/10.1109/ICM.2003.238502","url":null,"abstract":"Thin films of SnO/sub 2/ were prepared by a sol-gel technique using tin tetrachloride (SnCl/sub 4/) and isopropyl alcohol solution. Applying standard lithography process, high sensitivity SnO/sub 2/ gas sensors were miniaturized on macromachined Si(100) substrates. Conductivity measurements of the films annealed at different temperatures have been carried out in dry air and in the presence of 5 ppm to 100 ppm ethanol. Response and recovery times of the sensors annealed at 550/spl deg/C at the optimum operating temperature were found to be about 5 and 40 seconds, respectively. Also sensitivity of the sensors was studied towards 500 ppm CO and 1000 ppm H/sub 2/ at different temperatures, indicating the satisfactory selectivity for ethanol.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124679689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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