M. B. Abderrahmen, M. Abid, J. Diguet, J. Philippe
In this paper, we present a series of experiments made with the aim of determining the scheduling mechanism for which the overhead is minimal. And that in the way to adopt it in the algorithm of automatic generation of the scheduled code that we developed.
{"title":"Automatic generation of code within the context of the design of the embedded real-time systems: case study","authors":"M. B. Abderrahmen, M. Abid, J. Diguet, J. Philippe","doi":"10.1109/ICM.2003.237882","DOIUrl":"https://doi.org/10.1109/ICM.2003.237882","url":null,"abstract":"In this paper, we present a series of experiments made with the aim of determining the scheduling mechanism for which the overhead is minimal. And that in the way to adopt it in the algorithm of automatic generation of the scheduled code that we developed.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131193742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Electron beam (1.5 MeV, 25 mA) irradiation increased the output of Light Emitting Diodes (LEDs), yellows from 23 lux up to 32 lux at 5 krads absorbed dose (low dose). Further irradiation, above 8 krads caused permanent damage associated with the attenuation of light emitted (high doses). As the same effect by gamma, in previous work, but in the increase in light intensity and current in low doses up to 1Mrads and damage occurs with 2Mrads. The I-V and C-V curves were sensitive to electron beam and gamma doses. This effect of LEDs can be successfully used for the determination of the absorbed dose in either low or high level. The range of low level was from 1 krad up to 8 krads and the high level is from 1 Mrad up to 20 Mrads or higher. Also /spl gamma/-rays doses behaved the same trend but the damage effect was more than electron beam at the same doses. The LEDs sample annealed after irradiation by electron beam and /spl gamma/-rays at room temperature for 1 year. The values of forward current reviewed to 12/spl plusmn/2% and 15/spl plusmn/2.5% from their original values. Oven annealing at different temperatures were ranging up to 250/spl deg/C. The output light intensity levels recover to around 17%, 23%, 39% and 54% of the initial values with annealing temperatures 100, 150, 200, and 250/spl deg/C respectively, in 1 H.
{"title":"Characterization of electron beam and gamma irradiation in light emitting diodes","authors":"K. Sharshar, M. Rageh, M. Ashry","doi":"10.1109/ICM.2003.238009","DOIUrl":"https://doi.org/10.1109/ICM.2003.238009","url":null,"abstract":"Electron beam (1.5 MeV, 25 mA) irradiation increased the output of Light Emitting Diodes (LEDs), yellows from 23 lux up to 32 lux at 5 krads absorbed dose (low dose). Further irradiation, above 8 krads caused permanent damage associated with the attenuation of light emitted (high doses). As the same effect by gamma, in previous work, but in the increase in light intensity and current in low doses up to 1Mrads and damage occurs with 2Mrads. The I-V and C-V curves were sensitive to electron beam and gamma doses. This effect of LEDs can be successfully used for the determination of the absorbed dose in either low or high level. The range of low level was from 1 krad up to 8 krads and the high level is from 1 Mrad up to 20 Mrads or higher. Also /spl gamma/-rays doses behaved the same trend but the damage effect was more than electron beam at the same doses. The LEDs sample annealed after irradiation by electron beam and /spl gamma/-rays at room temperature for 1 year. The values of forward current reviewed to 12/spl plusmn/2% and 15/spl plusmn/2.5% from their original values. Oven annealing at different temperatures were ranging up to 250/spl deg/C. The output light intensity levels recover to around 17%, 23%, 39% and 54% of the initial values with annealing temperatures 100, 150, 200, and 250/spl deg/C respectively, in 1 H.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133576475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. H. Rasouli, A. Afzali-Kusha, A. Khademzadeh, M. Nourani
In this paper a novel logic family called Low-race Spilt-level Charge-Recycling Pass-transistor Logic (LSCPL) has been proposed that employs a new output driver. LSCPL has high deriving capability due to separating load from pass transistor logic and has less power consumption and smaller delay compared to previously charge recycling logic. It has an additional benefit of lower sensitivity to signal skew. Using new regenerator in LSCPL leads to complete elimination of controller in the circuit, hence the number of transistors was greatly reduced compared to previous Spilt-level Precharge Differential Logic (SPDL). Improvements in the parameters are confirmed by simulating a two input NAND gate.
{"title":"Low-race Split-level Charge-Recycling Pass-transistor Logic (LSCPL) for low power","authors":"S. H. Rasouli, A. Afzali-Kusha, A. Khademzadeh, M. Nourani","doi":"10.1109/ICM.2003.237775","DOIUrl":"https://doi.org/10.1109/ICM.2003.237775","url":null,"abstract":"In this paper a novel logic family called Low-race Spilt-level Charge-Recycling Pass-transistor Logic (LSCPL) has been proposed that employs a new output driver. LSCPL has high deriving capability due to separating load from pass transistor logic and has less power consumption and smaller delay compared to previously charge recycling logic. It has an additional benefit of lower sensitivity to signal skew. Using new regenerator in LSCPL leads to complete elimination of controller in the circuit, hence the number of transistors was greatly reduced compared to previous Spilt-level Precharge Differential Logic (SPDL). Improvements in the parameters are confirmed by simulating a two input NAND gate.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126950607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Interest in multi-mode wireless system and software-defined radio has led to a need for high-speed high-resolution bandpass analog to digital (A/D) converters to digitalize signals near to the front end of a radio receiver. Such high-frequency applications require that the modulator be clocked at a high frequency, which in turn, requires the modulators' loop filters to be built as continuous-time circuits (e.g. using LC resonators) rather than discrete-time circuits (e.g. switched capacitors). All the previous analysis of continuous-time bandpass /spl Sigma//spl Delta/ modulators considered the assumption of having filter with an infinite quality factor (Q). This assumption is impractical especially with on-chip filters which leads to an approximate noise transfer function (an infinitely deep notch in the quantization noise) and approximate signal to noise ratio (SNR). In this paper, a more accurate z-domain loop transfer function is derived. This loop transfer function is used in finding the noise transfer function. The effect of the resonator Q in the depth of the notch on the noise transfer function is analyzed. Derivation of a mathematical expression for SNR, using the exact formula of the loop transfer function, is provided. Also, the dependence of the modulator's SNR on the resonator Q is presented.
{"title":"Exact formulation of the signal to noise ratio in continuous-time noise shaping A/D converters","authors":"A.I. Hussein, N. M. Ibrahim, W. Kuhn","doi":"10.1109/ICM.2003.238613","DOIUrl":"https://doi.org/10.1109/ICM.2003.238613","url":null,"abstract":"Interest in multi-mode wireless system and software-defined radio has led to a need for high-speed high-resolution bandpass analog to digital (A/D) converters to digitalize signals near to the front end of a radio receiver. Such high-frequency applications require that the modulator be clocked at a high frequency, which in turn, requires the modulators' loop filters to be built as continuous-time circuits (e.g. using LC resonators) rather than discrete-time circuits (e.g. switched capacitors). All the previous analysis of continuous-time bandpass /spl Sigma//spl Delta/ modulators considered the assumption of having filter with an infinite quality factor (Q). This assumption is impractical especially with on-chip filters which leads to an approximate noise transfer function (an infinitely deep notch in the quantization noise) and approximate signal to noise ratio (SNR). In this paper, a more accurate z-domain loop transfer function is derived. This loop transfer function is used in finding the noise transfer function. The effect of the resonator Q in the depth of the notch on the noise transfer function is analyzed. Derivation of a mathematical expression for SNR, using the exact formula of the loop transfer function, is provided. Also, the dependence of the modulator's SNR on the resonator Q is presented.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117080538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Artificial Neural Networks are applied for solving a wide variety of problems in several areas such as signal processing, robotics, diagnosis, and pattern recognition. These applications demand a high computing power and the traditional software implementation are not sufficient. Hardware implementation of neural networks is very interesting due to its high performance and can easily be made parallel. This paper presents a hardware implementation of neural network after training and simulation on the MATLAB software. The excellent hardware performance has been performed through the use of field programmable gate array (FPGA). The diagnosis of the Multi-Purpose Research Reactor of Egypt accidents is used to test the proposed system.
{"title":"Hardware implementation of neural network on FPGA for accidents diagnosis of the multi-purpose research reactor of Egypt","authors":"M. Syiam, H. M. Klash, I. Mahmoud, S. S. Haggag","doi":"10.1109/ICM.2003.237885","DOIUrl":"https://doi.org/10.1109/ICM.2003.237885","url":null,"abstract":"Artificial Neural Networks are applied for solving a wide variety of problems in several areas such as signal processing, robotics, diagnosis, and pattern recognition. These applications demand a high computing power and the traditional software implementation are not sufficient. Hardware implementation of neural networks is very interesting due to its high performance and can easily be made parallel. This paper presents a hardware implementation of neural network after training and simulation on the MATLAB software. The excellent hardware performance has been performed through the use of field programmable gate array (FPGA). The diagnosis of the Multi-Purpose Research Reactor of Egypt accidents is used to test the proposed system.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"328 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115225731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To successfully transmit data over any network, a protocol is required to manage the flow or pace at which the data is transmitted. This protocol is defined in Layer 2 of OSI (Open Systems Interconnection) model. High-level Data Link Control (HDLC) is the most commonly used Layer 2 protocol and is suitable for bit oriented packet transmission mode. This paper discusses the VHDL modeling of single-channel HDLC Layer 2 protocol Transmitter and its implementation using Xilinx Virtex FPGA as the target technology. The HDLC Transmitter is used to transmit the HDLC frame structure. Implementing the single-channel HDLC protocol Transmitter in FPGA gives you the flexibility, upgradability and customization benefits of programmable logic.
为了在任何网络上成功地传输数据，需要一个协议来管理数据传输的流或速度。该协议是在OSI(开放系统互连)模型的第二层中定义的。HDLC (High-level Data Link Control)是最常用的第二层协议，适用于面向比特的分组传输模式。本文讨论了单通道HDLC第二层协议发射机的VHDL建模及其以Xilinx Virtex FPGA为目标技术的实现。HDLC发射机用于传输HDLC帧结构。在FPGA中实现单通道HDLC协议发射器为您提供可编程逻辑的灵活性，可升级性和自定义优势。
{"title":"FPGA implementation of a single-channel HDLC Layer-2 protocol transmitter using VHDL","authors":"Syed Manzoor Qasim, S. A. Abbasi","doi":"10.1109/ICM.2003.237826","DOIUrl":"https://doi.org/10.1109/ICM.2003.237826","url":null,"abstract":"To successfully transmit data over any network, a protocol is required to manage the flow or pace at which the data is transmitted. This protocol is defined in Layer 2 of OSI (Open Systems Interconnection) model. High-level Data Link Control (HDLC) is the most commonly used Layer 2 protocol and is suitable for bit oriented packet transmission mode. This paper discusses the VHDL modeling of single-channel HDLC Layer 2 protocol Transmitter and its implementation using Xilinx Virtex FPGA as the target technology. The HDLC Transmitter is used to transmit the HDLC frame structure. Implementing the single-channel HDLC protocol Transmitter in FPGA gives you the flexibility, upgradability and customization benefits of programmable logic.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115530886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we investigated a new class of nanometer scale transistors that use the field generated by an applied gate bias to modulate the transmission probability through a tunnel barrier between drain and source. The characteristics of such transistors were studied using a computer simulation. A 2-D Poisson's equation solver was implemented to calculate the potential distribution using the finite element method. Then, the current was calculated using the transmission coefficient by considering the electron energy distribution. Two forms of the transistors were studied: single-gate MITT and dual-gate MITT. For each form, the key parameters affecting the device operation were studied.
{"title":"Theoretical investigation of single- and dual-gate metal insulator tunnel transistors","authors":"A. Shaker, A. Zekry","doi":"10.1109/ICM.2003.237778","DOIUrl":"https://doi.org/10.1109/ICM.2003.237778","url":null,"abstract":"In this paper, we investigated a new class of nanometer scale transistors that use the field generated by an applied gate bias to modulate the transmission probability through a tunnel barrier between drain and source. The characteristics of such transistors were studied using a computer simulation. A 2-D Poisson's equation solver was implemented to calculate the potential distribution using the finite element method. Then, the current was calculated using the transmission coefficient by considering the electron energy distribution. Two forms of the transistors were studied: single-gate MITT and dual-gate MITT. For each form, the key parameters affecting the device operation were studied.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125402545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. El-Soud, R. Abdelrassoul, H. Soliman, L. El-ghanam
This paper presents an analog VLSI neural network for designing a programmable neural system. Synaptic weights are designed in the triode region using four-MOS transistors. Moreover, the summing element (SE) and the activation function are designed in subthreshold region. This system is realized in a standard 0.8 /spl mu/m CMOS technology and operated with a /spl plusmn/1V power supply.
本文提出了一种用于设计可编程神经系统的模拟VLSI神经网络。在三极管区域使用四个mos晶体管设计突触权重。在阈下区域设计了和元和激活函数。本系统采用标准的0.8 /spl μ m CMOS工艺，采用1 /spl plusmn/1V电源运行。
{"title":"Low-power CMOS circuits for analog VLSI programmable neural networks","authors":"M. El-Soud, R. Abdelrassoul, H. Soliman, L. El-ghanam","doi":"10.1109/ICM.2003.238250","DOIUrl":"https://doi.org/10.1109/ICM.2003.238250","url":null,"abstract":"This paper presents an analog VLSI neural network for designing a programmable neural system. Synaptic weights are designed in the triode region using four-MOS transistors. Moreover, the summing element (SE) and the activation function are designed in subthreshold region. This system is realized in a standard 0.8 /spl mu/m CMOS technology and operated with a /spl plusmn/1V power supply.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114956812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Recent advances in Deep Submicron Design (DSM) have considerably increased the importance of inductive coupling effects for long interconnects. This is especially significant for global interconnect with its wide busses that may run from one corner of a chip to the other. Inductive coupling has been shown to depend on the distance wires run in parallel to each other and the activity on these wires. It has also been shown that the presence of signal wires separating the attacker and the victim leads to a reduction in the inductive coupling between the two. A technique known as swizzling has been proposed to make use of this fact to control inductive coupling in wide global signal busses. In this paper we show that this technique reduces the inductive coupling for the most vulnerable wires neighboring the attacker in significantly long busses by around 20% without negatively impacting the capacitive coupling.
{"title":"The effects of swizzling on inductive and capacitive coupling for wide signal busses","authors":"B. Soudan","doi":"10.1109/ICM.2003.237879","DOIUrl":"https://doi.org/10.1109/ICM.2003.237879","url":null,"abstract":"Recent advances in Deep Submicron Design (DSM) have considerably increased the importance of inductive coupling effects for long interconnects. This is especially significant for global interconnect with its wide busses that may run from one corner of a chip to the other. Inductive coupling has been shown to depend on the distance wires run in parallel to each other and the activity on these wires. It has also been shown that the presence of signal wires separating the attacker and the victim leads to a reduction in the inductive coupling between the two. A technique known as swizzling has been proposed to make use of this fact to control inductive coupling in wide global signal busses. In this paper we show that this technique reduces the inductive coupling for the most vulnerable wires neighboring the attacker in significantly long busses by around 20% without negatively impacting the capacitive coupling.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130201927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. A. Elmisery, A. Khalil, A. Salama, H. F. Hammed
In this work we propose a speech recognition system for Arabic speech based on a hardware/software co-design implementation approach. Speech recognition is a computationally demanding task, specially the pattern matching stage. The Hidden Markov Model (HMM) is considered the most powerful modeling and matching technique in the different speech recognition tasks. Implementing the pattern matching algorithm, which is time consuming, using dedicated hardware will speed up the recognition process. In this paper, a pattern matching algorithm based on HMM is implemented using Field Programmable Gate Array (FPGA). The forward algorithm, core of matching algorithm in HMM, is analyzed and modified to be more suitable for FPGA implementation. Implementation results showed that the recognition accuracy of the modified algorithm is very close to the classical algorithm with the gain of achieving higher speed and less occupied area in the FPGA. The proposed approach is used for isolated Arabic word recognition and achieved a recognition accuracy comparable with the powerful classical recognition system.
{"title":"A FPGA-based HMM for a discrete Arabic speech recognition system","authors":"F. A. Elmisery, A. Khalil, A. Salama, H. F. Hammed","doi":"10.1109/ICM.2003.237884","DOIUrl":"https://doi.org/10.1109/ICM.2003.237884","url":null,"abstract":"In this work we propose a speech recognition system for Arabic speech based on a hardware/software co-design implementation approach. Speech recognition is a computationally demanding task, specially the pattern matching stage. The Hidden Markov Model (HMM) is considered the most powerful modeling and matching technique in the different speech recognition tasks. Implementing the pattern matching algorithm, which is time consuming, using dedicated hardware will speed up the recognition process. In this paper, a pattern matching algorithm based on HMM is implemented using Field Programmable Gate Array (FPGA). The forward algorithm, core of matching algorithm in HMM, is analyzed and modified to be more suitable for FPGA implementation. Implementation results showed that the recognition accuracy of the modified algorithm is very close to the classical algorithm with the gain of achieving higher speed and less occupied area in the FPGA. The proposed approach is used for isolated Arabic word recognition and achieved a recognition accuracy comparable with the powerful classical recognition system.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127737074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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