This article introduces a new method for generating benchmark circuits. Common methods of testing physical design algorithms and functional verifications used today rely on standardised sets of widely accepted benchmark circuits, or on generating a random benchmark circuit based on its desired characteristics. Although these approaches are suitable in many situations, sometimes it is advantageous to know an exact function of a benchmark circuit. This article introduces a new method for generating benchmarks that is based on structural modifications of a user-specified design without altering its function. The method uses a set of pre-defined operations on a circuit netlist. The method is demonstrated on several examples.
{"title":"Invar-a new approach to EDA benchmark generation","authors":"M. Kunes, M. Danek","doi":"10.1109/ICM.2003.238304","DOIUrl":"https://doi.org/10.1109/ICM.2003.238304","url":null,"abstract":"This article introduces a new method for generating benchmark circuits. Common methods of testing physical design algorithms and functional verifications used today rely on standardised sets of widely accepted benchmark circuits, or on generating a random benchmark circuit based on its desired characteristics. Although these approaches are suitable in many situations, sometimes it is advantageous to know an exact function of a benchmark circuit. This article introduces a new method for generating benchmarks that is based on structural modifications of a user-specified design without altering its function. The method uses a set of pre-defined operations on a circuit netlist. The method is demonstrated on several examples.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124647305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper the transient response measurement method is presented which allows the characterization of ferroelectric capacitors for signal slew rates up to 800 MV/s. This method completes the Quasi Static Capacitance Voltage (QSCV) measurement and the Sawyer Tower measurement which is suitable for low and medium frequencies. The comparison of the results obtained by different measurement methods show the usability of the presented method.
{"title":"Characterization of ferroelectric capacitors over wide frequency range","authors":"E. Supriyanto, H. Goebel","doi":"10.1109/ICM.2003.237830","DOIUrl":"https://doi.org/10.1109/ICM.2003.237830","url":null,"abstract":"In this paper the transient response measurement method is presented which allows the characterization of ferroelectric capacitors for signal slew rates up to 800 MV/s. This method completes the Quasi Static Capacitance Voltage (QSCV) measurement and the Sawyer Tower measurement which is suitable for low and medium frequencies. The comparison of the results obtained by different measurement methods show the usability of the presented method.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124682196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The paper focuses on error detection in circuits implemented in FPGAs using error detection codes (ED codes). The incorrect function of a given combinational circuit has to be detected and signalized at the time of its appearance and before its further distribution. It means that a safe operation is guaranteed. The ability to detect an error without stopping circuit function is called concurrent error detection (CED). We have used combinational circuits only to simplify testing process. A previous research was based on benchmarks described by tables. In some cases benchmarks with many inputs cannot be described by tables easily. The benchmarks used in our experiments to compute a quality of the code are described by equations. All of them will be implemented in XILINX FPGA circuits. Therefore the fault model considers the way of configuration data storage in memory. This work is a part of a more complex methodology of fault tolerant design based on FPGAs with a possibility to reconfigure the faulty part of the circuit.
{"title":"Design of self checking circuits based on FPGA","authors":"P. Kubalík, H. Kubátová","doi":"10.1109/ICM.2003.237970","DOIUrl":"https://doi.org/10.1109/ICM.2003.237970","url":null,"abstract":"The paper focuses on error detection in circuits implemented in FPGAs using error detection codes (ED codes). The incorrect function of a given combinational circuit has to be detected and signalized at the time of its appearance and before its further distribution. It means that a safe operation is guaranteed. The ability to detect an error without stopping circuit function is called concurrent error detection (CED). We have used combinational circuits only to simplify testing process. A previous research was based on benchmarks described by tables. In some cases benchmarks with many inputs cannot be described by tables easily. The benchmarks used in our experiments to compute a quality of the code are described by equations. All of them will be implemented in XILINX FPGA circuits. Therefore the fault model considers the way of configuration data storage in memory. This work is a part of a more complex methodology of fault tolerant design based on FPGAs with a possibility to reconfigure the faulty part of the circuit.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"141 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113985258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The use of code compression in embedded systems based on standard RISC instruction set architectures (ISA) has been shown in the past to be of benefit in reducing overall system cost. The 16-bit THUMB ISA from ARM Ltd has a significantly higher density than the original 32-bits ARM ISA. In this paper we propose a new memory compression architecture, which employs a lossless data compression algorithm to achieve a further size reduction of around 20% on the THUMB code. We show that in some applications, the decompression can be performed in software on the main system processor without excessive processing time overheads.
{"title":"ARM/THUMB code compression for embedded systems","authors":"X.H. Xu, S. Jones, C. Clarke","doi":"10.1109/ICM.2003.238300","DOIUrl":"https://doi.org/10.1109/ICM.2003.238300","url":null,"abstract":"The use of code compression in embedded systems based on standard RISC instruction set architectures (ISA) has been shown in the past to be of benefit in reducing overall system cost. The 16-bit THUMB ISA from ARM Ltd has a significantly higher density than the original 32-bits ARM ISA. In this paper we propose a new memory compression architecture, which employs a lossless data compression algorithm to achieve a further size reduction of around 20% on the THUMB code. We show that in some applications, the decompression can be performed in software on the main system processor without excessive processing time overheads.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124054571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The Verilog-AMS language is a high-level language that uses modules to describe the structure and behavior of analog systems and their components. It is an extension to IEEE 1364 Verilog Hardware Description Language (HDL). This paper presents a 2.4 GHz VCO model by Verilog-A for IP and SoC purpose. It fabricated by TSMC 0.25-/spl mu/m; based on the measurement results, the tuning range is 187 MHz (7.78%); phase noise is 91dBc/HZ@1 MHz offset at 2.4 GHz.
{"title":"2.4 GHz CMOS VCO design with Verilog-AMS","authors":"Kuo-Hua Cheng, C. Jou","doi":"10.1109/ICM.2003.238421","DOIUrl":"https://doi.org/10.1109/ICM.2003.238421","url":null,"abstract":"The Verilog-AMS language is a high-level language that uses modules to describe the structure and behavior of analog systems and their components. It is an extension to IEEE 1364 Verilog Hardware Description Language (HDL). This paper presents a 2.4 GHz VCO model by Verilog-A for IP and SoC purpose. It fabricated by TSMC 0.25-/spl mu/m; based on the measurement results, the tuning range is 187 MHz (7.78%); phase noise is 91dBc/HZ@1 MHz offset at 2.4 GHz.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132517109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A new LC voltage-controlled oscillator circuit topology is proposed, in which the flicker noise generated by the tail transistor is noticeably reduced by utilizing the phenomenon of flicker noise intrinsic reduction due to switched biasing. A macro model of MOSFET under switched biasing is used to prove the idea. Circuit simulations are done on two oscillators with the same tail current value; one with fixed biasing and the other with the proposed switching. A 4 dBc/Hz phase noise improvement is achieved at 1 kHz frequency offset in the switched biasing scheme under the same power dissipation and tuning range.
{"title":"Tail current flicker noise reduction in LC VCOs by complementary switched biasing","authors":"A.K. Kassim, K. Sharaf, H. Ragaie","doi":"10.1109/ICM.2003.238422","DOIUrl":"https://doi.org/10.1109/ICM.2003.238422","url":null,"abstract":"A new LC voltage-controlled oscillator circuit topology is proposed, in which the flicker noise generated by the tail transistor is noticeably reduced by utilizing the phenomenon of flicker noise intrinsic reduction due to switched biasing. A macro model of MOSFET under switched biasing is used to prove the idea. Circuit simulations are done on two oscillators with the same tail current value; one with fixed biasing and the other with the proposed switching. A 4 dBc/Hz phase noise improvement is achieved at 1 kHz frequency offset in the switched biasing scheme under the same power dissipation and tuning range.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134581501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Two-dimensional numerical simulation studies of collector-emitter breakdown voltage (BV/sub CEO/) of a novel collector-tub lateral bipolar transistor (CTLBT) on silicon-on-insulator (SOI) are presented. The collector-tub is realized by etching the buried oxide (BOX) at the collector high-low (NN/sup +/) junction side followed by an N-implantation in a conventional lateral bipolar transistor (LBT) on SOI. Such a modification makes the collector potential to be absorbed both by the collector drift and substrate regions and the electric field spreads along the collector drift length. The simulation results show that by choosing appropriate buried oxide (BOX) thickness (t/sub OX/), collector-tub junction depth (X/sub j/), drift region doping (N/sub D/) and substrate doping (N/sub S/), the electric field profile in the collector drift region of the CTLBT can be redistributed so that its BV/sub CEO/ value is more than double when compared with a conventional lateral bipolar transistor on SOI. The reasons for this significant improvement in breakdown performance are explained.
{"title":"A novel collector-tub concept for realizing high-voltage lateral bipolar transistors on SOI","authors":"M. Jagadesh Kumar, S.D. Roy","doi":"10.1109/ICM.2003.237927","DOIUrl":"https://doi.org/10.1109/ICM.2003.237927","url":null,"abstract":"Two-dimensional numerical simulation studies of collector-emitter breakdown voltage (BV/sub CEO/) of a novel collector-tub lateral bipolar transistor (CTLBT) on silicon-on-insulator (SOI) are presented. The collector-tub is realized by etching the buried oxide (BOX) at the collector high-low (NN/sup +/) junction side followed by an N-implantation in a conventional lateral bipolar transistor (LBT) on SOI. Such a modification makes the collector potential to be absorbed both by the collector drift and substrate regions and the electric field spreads along the collector drift length. The simulation results show that by choosing appropriate buried oxide (BOX) thickness (t/sub OX/), collector-tub junction depth (X/sub j/), drift region doping (N/sub D/) and substrate doping (N/sub S/), the electric field profile in the collector drift region of the CTLBT can be redistributed so that its BV/sub CEO/ value is more than double when compared with a conventional lateral bipolar transistor on SOI. The reasons for this significant improvement in breakdown performance are explained.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131765232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work presents a methodology for estimating and minimizing the total amount of gate-tunneling current in CMOS combinatorial circuits. We take advantage of the state-dependency exhibited by the gate-leakage and use signal probabilities to optimize internal circuit interconnections. Results are given for a number of ISCAS-85 benchmark circuits.
{"title":"Gate-leakage estimation and minimization in CMOS combinatorial circuits","authors":"R.S. Guindi","doi":"10.1109/ICM.2003.238361","DOIUrl":"https://doi.org/10.1109/ICM.2003.238361","url":null,"abstract":"This work presents a methodology for estimating and minimizing the total amount of gate-tunneling current in CMOS combinatorial circuits. We take advantage of the state-dependency exhibited by the gate-leakage and use signal probabilities to optimize internal circuit interconnections. Results are given for a number of ISCAS-85 benchmark circuits.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124535584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Savio, M. Carmina, A. Richelli, L. Colalongo, Z. Kovács-Vajna
A new lumped model for on-chip planar (square, hexagonal, octagonal) inductors is presented. The model is simple, it is based on linear passive components with frequency independent parameters and accurately accounts for the substrate leakage currents in a wide frequency range. Furthermore, the model is straightforwardly implementable in circuit simulators such as, for example, SPICE.
{"title":"A new lumped model for on-chip inductors including substrate currents","authors":"A. Savio, M. Carmina, A. Richelli, L. Colalongo, Z. Kovács-Vajna","doi":"10.1109/ICM.2003.238561","DOIUrl":"https://doi.org/10.1109/ICM.2003.238561","url":null,"abstract":"A new lumped model for on-chip planar (square, hexagonal, octagonal) inductors is presented. The model is simple, it is based on linear passive components with frequency independent parameters and accurately accounts for the substrate leakage currents in a wide frequency range. Furthermore, the model is straightforwardly implementable in circuit simulators such as, for example, SPICE.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114765995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A high-frequency low-power sinusoidal quadrature oscillator is presented through a new technique using only CMOS current mirrors. The technique is relatively simple based on (1) internal capacitances of CMOS current mirrors and (2) a resistor of a CMOS current mirror for a negative resistance. No external capacitances or inductances are required. As a particular example, a 3.02-GHz, 0.4-f/sub T/, 0.31-mW, CMOS sinusoidal quadrature oscillator has been demonstrated. The oscillation frequency (f/sub 0/) is 3.02 GHz. The ratio of (f/sub 0//f/sub T/) is 0.4. The power consumption is low at approximately 0.31 mW. Total harmonic distortions (THD) are less than 0.3%. The oscillation frequency is current-tunable over a range of 660 MHz or 21.85%. The amplitude matching and the quadrature phase matching are better than 0.029 dB and 0.15/spl deg/, respectively. A figure of merit called CNR/sub norm/ is 161.68 dBc/Hz at the 2 MHz offset from 3.02 GHz. Comparisons to other approaches are also presented.
{"title":"A high-frequency low-power sinusoidal quadrature oscillator using only CMOS current mirrors","authors":"A. Leelasantitham, B. Srisuchinwong","doi":"10.1109/ICM.2003.238011","DOIUrl":"https://doi.org/10.1109/ICM.2003.238011","url":null,"abstract":"A high-frequency low-power sinusoidal quadrature oscillator is presented through a new technique using only CMOS current mirrors. The technique is relatively simple based on (1) internal capacitances of CMOS current mirrors and (2) a resistor of a CMOS current mirror for a negative resistance. No external capacitances or inductances are required. As a particular example, a 3.02-GHz, 0.4-f/sub T/, 0.31-mW, CMOS sinusoidal quadrature oscillator has been demonstrated. The oscillation frequency (f/sub 0/) is 3.02 GHz. The ratio of (f/sub 0//f/sub T/) is 0.4. The power consumption is low at approximately 0.31 mW. Total harmonic distortions (THD) are less than 0.3%. The oscillation frequency is current-tunable over a range of 660 MHz or 21.85%. The amplitude matching and the quadrature phase matching are better than 0.029 dB and 0.15/spl deg/, respectively. A figure of merit called CNR/sub norm/ is 161.68 dBc/Hz at the 2 MHz offset from 3.02 GHz. Comparisons to other approaches are also presented.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128296915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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