Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649067
Kyungho Ryu, Dong-Hoon Jung, Seong-ook Jung
We propose a timing generator for use in high-performance automatic testing equipment that achieves a high, wide-range test cycle frequency and process variation tolerance using four sub-timing generators and a CLKRATE divider. Each sub-timing generator is composed of an edge vernier, an integer delay generator, and an offset canceller. A prototype chip fabricated using 0.13-μm CMOS technology can achieve an arbitrary test cycle frequency of up to 1.2 GHz, a timing resolution of 1.95 ps, a power consumption of 90 mW, and an area of 1.5 mm2.
{"title":"All-digital process-variation-calibrated timing generator for ATE with 1.95-ps resolution and a maximum 1.2-GHz test rate","authors":"Kyungho Ryu, Dong-Hoon Jung, Seong-ook Jung","doi":"10.1109/ESSCIRC.2013.6649067","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649067","url":null,"abstract":"We propose a timing generator for use in high-performance automatic testing equipment that achieves a high, wide-range test cycle frequency and process variation tolerance using four sub-timing generators and a CLKRATE divider. Each sub-timing generator is composed of an edge vernier, an integer delay generator, and an offset canceller. A prototype chip fabricated using 0.13-μm CMOS technology can achieve an arbitrary test cycle frequency of up to 1.2 GHz, a timing resolution of 1.95 ps, a power consumption of 90 mW, and an area of 1.5 mm2.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127740871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649062
E. Candès, S. Becker
Compressive sensing (CS) [1]-[3] has emerged in the last decade as a powerful tool and paradigm for acquiring signals of interest from fewer measurements than was thought possible. CS capitalizes on the the fact that many real-world signals inherently have far fewer degrees of freedom than the signal size might indicate. For instance, a signal with a sparse spectrum depends upon fewer degrees of freedom than the total bandwidth it may cover. CS theory then asserts that one can use very efficient randomized sensing protocols, which would sample such signals in proportion to their degrees of freedom rather than in proportion to the dimension of the larger space they occupy (e.g., Nyquist-rate sampling). An overview and mathematical description of CS can be found in [4].
{"title":"Compressive sensing: Principles and hardware implementations","authors":"E. Candès, S. Becker","doi":"10.1109/ESSCIRC.2013.6649062","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649062","url":null,"abstract":"Compressive sensing (CS) [1]-[3] has emerged in the last decade as a powerful tool and paradigm for acquiring signals of interest from fewer measurements than was thought possible. CS capitalizes on the the fact that many real-world signals inherently have far fewer degrees of freedom than the signal size might indicate. For instance, a signal with a sparse spectrum depends upon fewer degrees of freedom than the total bandwidth it may cover. CS theory then asserts that one can use very efficient randomized sensing protocols, which would sample such signals in proportion to their degrees of freedom rather than in proportion to the dimension of the larger space they occupy (e.g., Nyquist-rate sampling). An overview and mathematical description of CS can be found in [4].","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"457 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116233725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649072
Michael Schaffner, P. Greisen, Simon Heinzle, Frank K. Gürkaynak, H. Kaeslin, A. Smolic
In this paper, a video rendering ASIC for multiview automultiscopic displays using an image domain warping approach is presented. The video rendering core is able to synthesize up to nine interleaved views from full-HD (1080p) stereoscopic 3D input footage. The design employs elliptical weighted average (EWA) splatting to perform the image resampling. We use the mathematical properties of the Gaussian filters of EWA splatting to analytically integrate display anti-aliasing into the resampling step. The use of realistic assumptions on the image transformation enable a hardware architecture that operates on a video stream in scan-line fashion and that does not require an off-chip memory. The ASIC, fabricated in a 65nm CMOS technology, runs at 260MHz and is able to deliver 28.7 interleaved full-HD (1080p) frames per second with eight views enabled. It has a core power dissipation of 550mW and its complexity is 6.8 MGE, including 4.36 MBit SRAM macros.
{"title":"MADmax: A 1080p stereo-to-multiview rendering ASIC in 65 nm CMOS based on image domain warping","authors":"Michael Schaffner, P. Greisen, Simon Heinzle, Frank K. Gürkaynak, H. Kaeslin, A. Smolic","doi":"10.1109/ESSCIRC.2013.6649072","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649072","url":null,"abstract":"In this paper, a video rendering ASIC for multiview automultiscopic displays using an image domain warping approach is presented. The video rendering core is able to synthesize up to nine interleaved views from full-HD (1080p) stereoscopic 3D input footage. The design employs elliptical weighted average (EWA) splatting to perform the image resampling. We use the mathematical properties of the Gaussian filters of EWA splatting to analytically integrate display anti-aliasing into the resampling step. The use of realistic assumptions on the image transformation enable a hardware architecture that operates on a video stream in scan-line fashion and that does not require an off-chip memory. The ASIC, fabricated in a 65nm CMOS technology, runs at 260MHz and is able to deliver 28.7 interleaved full-HD (1080p) frames per second with eight views enabled. It has a core power dissipation of 550mW and its complexity is 6.8 MGE, including 4.36 MBit SRAM macros.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130375225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649116
Tapio Rapinoja, K. Stadius, J. Ryynänen
This paper presents a wide-band digital frequency synthesizer based on digital period synthesis (DPS). As a direct frequency synthesis method, the DPS architecture achieves inherently wide operational band, high frequency resolution and instantaneous settling. The frequency synthesizer, including reference delay-locked loop (DLL), DPS unit, and frequency multiplying DLL, was implemented in a 65-nm CMOS process and it occupies an active area of 0.3 mm2. The implemented frequency synthesizer covers a frequency range from 0.3 GHz to 8.5 GHz with 1 Hz frequency resolution, 550 fs integrated jitter, and 0.9 μs settling time.
{"title":"A 0.3-to-8.5GHz frequency synthesizer based on digital period synthesis","authors":"Tapio Rapinoja, K. Stadius, J. Ryynänen","doi":"10.1109/ESSCIRC.2013.6649116","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649116","url":null,"abstract":"This paper presents a wide-band digital frequency synthesizer based on digital period synthesis (DPS). As a direct frequency synthesis method, the DPS architecture achieves inherently wide operational band, high frequency resolution and instantaneous settling. The frequency synthesizer, including reference delay-locked loop (DLL), DPS unit, and frequency multiplying DLL, was implemented in a 65-nm CMOS process and it occupies an active area of 0.3 mm2. The implemented frequency synthesizer covers a frequency range from 0.3 GHz to 8.5 GHz with 1 Hz frequency resolution, 550 fs integrated jitter, and 0.9 μs settling time.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128810370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649140
N. Deferm, Wouter Volkaerts, J. Osorio, A. D. Graauw, M. Steyaert, P. Reynaert
In this paper a fully integrated D-band transmitter with on-chip dipole bondwire antenna implemented in 45nm low power CMOS is presented. On-chip frequency generation, insensitive to VCO pulling, is integrated together with a direct carrier quadrature vector modulator, ASK modulator, 4-stage differential transformer-coupled power amplifier and antenna. Digital baseband circuits are also integrated on the same chip. The chip is capable of generating QPSK and Star-QAM modulation formats. Data transmission over a distance up to 1m is achieved for data rates as high as 2Gb/s. For shorter distances, data rates up to 10Gb/s are measured.
{"title":"A 120GHz fully integrated 10Gb/s wireless transmitter with on-chip antenna in 45nm low power CMOS","authors":"N. Deferm, Wouter Volkaerts, J. Osorio, A. D. Graauw, M. Steyaert, P. Reynaert","doi":"10.1109/ESSCIRC.2013.6649140","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649140","url":null,"abstract":"In this paper a fully integrated D-band transmitter with on-chip dipole bondwire antenna implemented in 45nm low power CMOS is presented. On-chip frequency generation, insensitive to VCO pulling, is integrated together with a direct carrier quadrature vector modulator, ASK modulator, 4-stage differential transformer-coupled power amplifier and antenna. Digital baseband circuits are also integrated on the same chip. The chip is capable of generating QPSK and Star-QAM modulation formats. Data transmission over a distance up to 1m is achieved for data rates as high as 2Gb/s. For shorter distances, data rates up to 10Gb/s are measured.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131305145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649089
F. Radice, M. Bruccoleri, M. Ganzerli, Giorgio Spelgatti, D. Sanzogni, M. Pozzoni, A. Mazzanti
A 6-bits 6-GS/s flash ADC is presented. Single-stage integrators are proposed as preamplifiers to drive the comparators. Compared to single-stage voltage amplifiers, integrators limit the gain-bandwidth requirements leading to lower power dissipation and smaller device size. Comparators are interleaved and clocked at half rate, limiting dissipation thanks to the longer available regeneration time. Offsets of the front-end are continuously calibrated in background. The ADC, realized in a 32nm Low Power CMOS technology proves a very robust operation with SNDR degradation of only 1.5dB going from 1GS/s to 6GS/s. ENOB at 6GS/s with Nyquist frequency input is 5.25 with power dissipation of 95mW from 1V supply. The corresponding FoM is 416fJ/conv. To the Authors knowledge the converter displays also the highest speed among CMOS flash ADCs with more than 4 effective bits of resolution.
{"title":"A 6-bit 6-GS/s 95mW background calibrated flash ADC with integrating preamplifiers and half-rate comparators in 32nm LP CMOS","authors":"F. Radice, M. Bruccoleri, M. Ganzerli, Giorgio Spelgatti, D. Sanzogni, M. Pozzoni, A. Mazzanti","doi":"10.1109/ESSCIRC.2013.6649089","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649089","url":null,"abstract":"A 6-bits 6-GS/s flash ADC is presented. Single-stage integrators are proposed as preamplifiers to drive the comparators. Compared to single-stage voltage amplifiers, integrators limit the gain-bandwidth requirements leading to lower power dissipation and smaller device size. Comparators are interleaved and clocked at half rate, limiting dissipation thanks to the longer available regeneration time. Offsets of the front-end are continuously calibrated in background. The ADC, realized in a 32nm Low Power CMOS technology proves a very robust operation with SNDR degradation of only 1.5dB going from 1GS/s to 6GS/s. ENOB at 6GS/s with Nyquist frequency input is 5.25 with power dissipation of 95mW from 1V supply. The corresponding FoM is 416fJ/conv. To the Authors knowledge the converter displays also the highest speed among CMOS flash ADCs with more than 4 effective bits of resolution.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131526652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649059
S. Finkbeiner
Micro-Electro-Mechanical Systems (MEMS) are sensing the environmental conditions and give input to electronic control systems. MEMS are miniature systems which usually combine tiny mechanical structures with electronic circuits. Typical MEMS structures have a size of a few micrometers. MEMS sensors make system reactions to human needs more intelligent, precise, and at much faster reaction rates than humanly possible. Today MEMS sensors can be found in nearly every motor vehicle, smart phone or laptop. Due to continuous product innovations, the sensors find their way into more and more applications in automotive and consumer electronics. According to IHS iSuppli an amount of 4.3 billion micromechanical sensors were sold in 2011 with an impressive increase to 9.8 billion sensors in 2015 - a growth rate of 23% per year! These growth rates are only possible with continuous efforts to improve the performance and to decrease the size, power consumption and costs of the sensors.
{"title":"MEMS for automotive and consumer electronics","authors":"S. Finkbeiner","doi":"10.1109/ESSCIRC.2013.6649059","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649059","url":null,"abstract":"Micro-Electro-Mechanical Systems (MEMS) are sensing the environmental conditions and give input to electronic control systems. MEMS are miniature systems which usually combine tiny mechanical structures with electronic circuits. Typical MEMS structures have a size of a few micrometers. MEMS sensors make system reactions to human needs more intelligent, precise, and at much faster reaction rates than humanly possible. Today MEMS sensors can be found in nearly every motor vehicle, smart phone or laptop. Due to continuous product innovations, the sensors find their way into more and more applications in automotive and consumer electronics. According to IHS iSuppli an amount of 4.3 billion micromechanical sensors were sold in 2011 with an impressive increase to 9.8 billion sensors in 2015 - a growth rate of 23% per year! These growth rates are only possible with continuous efforts to improve the performance and to decrease the size, power consumption and costs of the sensors.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114190746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649154
H. Milosiu, F. Oehler, M. Eppel, Dieter Frühsorger, Stephan Lensing, G. Popken, Thomas Thönes
A ultra-low power wake-up receiver based on a novel fast sampling method is presented. The innovative approach allows the scalability of current consumption versus data rate at a constant sensitivity, meeting both short reaction time and ultra-low power consumption requirements. The 868 MHz OOK receiver comprises an analogue superheterodyne front-end and two digital 31 bit correlating decoders. It is fabricated in a 130 nm CMOS technology. The current consumption of the prototype is 1.2 μA at 2.5 volts supply voltage and a reaction time of 484 ms. The receiver sensitivity is -83 dBm thus obtaining a line-of-sight distance of 1200 metres for an assumed transmit power of 10 mW. Compared to other sub-100 μW receivers, the sensitivity of the presented implementation is best.
{"title":"A 3-µW 868-MHz wake-up receiver with −83 dBm sensitivity and scalable data rate","authors":"H. Milosiu, F. Oehler, M. Eppel, Dieter Frühsorger, Stephan Lensing, G. Popken, Thomas Thönes","doi":"10.1109/ESSCIRC.2013.6649154","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649154","url":null,"abstract":"A ultra-low power wake-up receiver based on a novel fast sampling method is presented. The innovative approach allows the scalability of current consumption versus data rate at a constant sensitivity, meeting both short reaction time and ultra-low power consumption requirements. The 868 MHz OOK receiver comprises an analogue superheterodyne front-end and two digital 31 bit correlating decoders. It is fabricated in a 130 nm CMOS technology. The current consumption of the prototype is 1.2 μA at 2.5 volts supply voltage and a reaction time of 484 ms. The receiver sensitivity is -83 dBm thus obtaining a line-of-sight distance of 1200 metres for an assumed transmit power of 10 mW. Compared to other sub-100 μW receivers, the sensitivity of the presented implementation is best.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114741719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649150
Yao Liu, E. Bonizzoni, Alessandro D'Amato, F. Maloberti
This paper presents a second-order 3-bit incremental converter, which uses a novel Smart-DEM algorithm for mismatch compensation of multi-level DAC unity elements. The circuit, fabricated in a mixed 0.18-0.5-μm CMOS technology, achieves more than 17-bit resolution over a 5-kHz bandwidth using 256 clock periods. A single-step chopping of the input stage leads to a residual offset of 9.7 μV. The measured SFDR and power consumption are -90 dB and 280 μW, respectively. The achieved Figure of Merit is 177.5 dB.
{"title":"A 105-dB SNDR, 10 kSps multi-level second-order incremental converter with smart-DEM consuming 280 µW and 3.3-V supply","authors":"Yao Liu, E. Bonizzoni, Alessandro D'Amato, F. Maloberti","doi":"10.1109/ESSCIRC.2013.6649150","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649150","url":null,"abstract":"This paper presents a second-order 3-bit incremental converter, which uses a novel Smart-DEM algorithm for mismatch compensation of multi-level DAC unity elements. The circuit, fabricated in a mixed 0.18-0.5-μm CMOS technology, achieves more than 17-bit resolution over a 5-kHz bandwidth using 256 clock periods. A single-step chopping of the input stage leads to a residual offset of 9.7 μV. The measured SFDR and power consumption are -90 dB and 280 μW, respectively. The achieved Figure of Merit is 177.5 dB.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121166383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649156
S. Dietrich, Lei Liao, F. Vanselow, R. Wunderlich, S. Heinen
The output voltage ripple is one of the most significant system parameters in switch-mode power supplies. This ripple degrades the performance of application specific integrated circuits (ASICs). The most common way to reduce it is to use additional integrated low drop-out regulators (LDO) on the ASIC. This technique usually suffers from high system efficiency as it is required for portable electronic systems. It also increases the design challenges of on-chip power management circuits and area required for the LDOs. This work presents a low-power fully integrated 0.97mm2 DC-DC Buck converter with a tuned series LDO with 1mV voltage ripple in a 0.25μm BiCMOS process. The converter prodives a power supply rejection ratio of more than 60 dB from 1 to 6MHz and a load current range of 0...400 mA. A peak efficiency of 93.7% has been measured. For high light load efficiency, automatic mode operation is implemented. To decrease the form factor and costs, the external components count has been reduced to a single inductor of 1 μH and two external capacitors of 2 μF each.
{"title":"A 1mV voltage ripple 0.97mm2 fully integrated low-power hybrid buck converter","authors":"S. Dietrich, Lei Liao, F. Vanselow, R. Wunderlich, S. Heinen","doi":"10.1109/ESSCIRC.2013.6649156","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649156","url":null,"abstract":"The output voltage ripple is one of the most significant system parameters in switch-mode power supplies. This ripple degrades the performance of application specific integrated circuits (ASICs). The most common way to reduce it is to use additional integrated low drop-out regulators (LDO) on the ASIC. This technique usually suffers from high system efficiency as it is required for portable electronic systems. It also increases the design challenges of on-chip power management circuits and area required for the LDOs. This work presents a low-power fully integrated 0.97mm2 DC-DC Buck converter with a tuned series LDO with 1mV voltage ripple in a 0.25μm BiCMOS process. The converter prodives a power supply rejection ratio of more than 60 dB from 1 to 6MHz and a load current range of 0...400 mA. A peak efficiency of 93.7% has been measured. For high light load efficiency, automatic mode operation is implemented. To decrease the form factor and costs, the external components count has been reduced to a single inductor of 1 μH and two external capacitors of 2 μF each.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116688986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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