Pub Date : 2025-09-15Epub Date: 2025-02-27DOI: 10.1016/j.mee.2025.112332
Linus Engelmann , IrenaeusWlokas
A deep-learning-based lithography model using a generative neural network (GAN) approach is developed and assessed for its ability to predict aerial images at different resist heights. The performance of the GAN approach is evaluated by analyzing deviations between model-generated aerial images and golden images, as well as differences in critical dimension (CD) values. Additionally, error analysis is conducted based on the feature distribution of each photomask. Selected patterns and their aerial images are compared both qualitatively to assess local errors and quantitatively through root-mean-square (RMS) errors to evaluate global accuracy. Error analysis reveals the features produced by the deep learning model leading to the highest deviation from the rigorous model results, and the error is decomposed into the error contributions of underpredicted and overpredicted features. An array of aerial images for selected resist heights produced by the deep learning model is assessed, revealing increasing errors with increasing resist heights. The limitations of applying deep learning techniques in computational lithography are illustrated by comparing a target pattern with and without optical proximity correction (OPC) features.
{"title":"On the feature accuracy of deep learning mask topography effect models","authors":"Linus Engelmann , IrenaeusWlokas","doi":"10.1016/j.mee.2025.112332","DOIUrl":"10.1016/j.mee.2025.112332","url":null,"abstract":"<div><div>A deep-learning-based lithography model using a generative neural network (GAN) approach is developed and assessed for its ability to predict aerial images at different resist heights. The performance of the GAN approach is evaluated by analyzing deviations between model-generated aerial images and golden images, as well as differences in critical dimension (CD) values. Additionally, error analysis is conducted based on the feature distribution of each photomask. Selected patterns and their aerial images are compared both qualitatively to assess local errors and quantitatively through root-mean-square (RMS) errors to evaluate global accuracy. Error analysis reveals the features produced by the deep learning model leading to the highest deviation from the rigorous model results, and the error is decomposed into the error contributions of underpredicted and overpredicted features. An array of aerial images for selected resist heights produced by the deep learning model is assessed, revealing increasing errors with increasing resist heights. The limitations of applying deep learning techniques in computational lithography are illustrated by comparing a target pattern with and without optical proximity correction (OPC) features.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112332"},"PeriodicalIF":2.6,"publicationDate":"2025-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143529001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-15Epub Date: 2025-05-02DOI: 10.1016/j.mee.2025.112355
Jiaheng Pan , Yanwei Sun , Shengyao Jia , Xudong Shen , Yiran Wang , Shien Wu , Cheng Pan , Mang Shi , Ge Shi
In this research article, we propose a tunable floating-type memristor emulator circuit with long-term memory (LTM) capabilities. The overall circuit consists of a Voltage Differential Transconductance Amplifier (VDTA), a Voltage Differential Complementary Amplifier (VDCA), and other basic components. The proposed emulator effectively prevents charge leakage on the capacitor by incorporating a switching circuit, thereby achieving long-term memory functionality. The emulator operates stably at a frequency of 10 MHz and supports seamless switching between incremental and decremental modes by altering the polarity of the input voltage. Moreover, the emulator exhibits excellent tunability, allowing adjustments to the equivalent memristor model by modifying the bias voltage and the aspect ratio of MOS transistors. The proposed emulator has been laid out and simulated using TSMC 0.18 μm process parameters in the Cadence Virtuoso platform. The simulation results align perfectly with the design and analysis, confirming the feasibility of the circuit. Finally, we explore potential applications of the proposed emulator in read-write circuit and memristor array circuit.
{"title":"A new tunable floating memristor emulator circuit with long-term memory","authors":"Jiaheng Pan , Yanwei Sun , Shengyao Jia , Xudong Shen , Yiran Wang , Shien Wu , Cheng Pan , Mang Shi , Ge Shi","doi":"10.1016/j.mee.2025.112355","DOIUrl":"10.1016/j.mee.2025.112355","url":null,"abstract":"<div><div>In this research article, we propose a tunable floating-type memristor emulator circuit with long-term memory (LTM) capabilities. The overall circuit consists of a Voltage Differential Transconductance Amplifier (VDTA), a Voltage Differential Complementary Amplifier (VDCA), and other basic components. The proposed emulator effectively prevents charge leakage on the capacitor by incorporating a switching circuit, thereby achieving long-term memory functionality. The emulator operates stably at a frequency of 10 MHz and supports seamless switching between incremental and decremental modes by altering the polarity of the input voltage. Moreover, the emulator exhibits excellent tunability, allowing adjustments to the equivalent memristor model by modifying the bias voltage and the aspect ratio of MOS transistors. The proposed emulator has been laid out and simulated using TSMC 0.18 μm process parameters in the Cadence Virtuoso platform. The simulation results align perfectly with the design and analysis, confirming the feasibility of the circuit. Finally, we explore potential applications of the proposed emulator in read-write circuit and memristor array circuit.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112355"},"PeriodicalIF":2.6,"publicationDate":"2025-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143911628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-15Epub Date: 2025-04-26DOI: 10.1016/j.mee.2025.112351
Louise Dumas , Christina Villeneuve-Faure , François Marc , Hélène Fremont , Guillaume Bascoul , Christophe Guerin
This paper presents the methodology to be applied in order to achieve the data retrieval of any magneto-resistive random access memory (MRAM) on the market, whether it's a Toggle MRAM or a STT-MRAM. This methodology consists of four stages: theoretical study of the structure, technological analysis to identify the physical structure of the memory, preparation of the memory to make the data accessible, and readout of those data.
Knowing the structural elements and how the MRAM is read/written allows the possibility to do its technological analysis. Then, this analysis allows the identification of the magnetic tunnel junction (MTJ), where the data (‘0’ / ‘1’) is stored as resistance states, and of its surroundings, mainly the bitline. Once this is done, a complex preparation of the device's backside is achieved to expose both sides of the MTJ: one side to apply the voltage and the other to collect the current. The sample preparation methodology consists of a chemical opening, a polishing down to the transistors, focused ion beam (FIB) etches of metallization levels surrounding the MTJ and metal deposition. Finally, the memory can be read by techniques derived from atomic force microscopy (AFM). For both memory types, the discrimination of the bit states is proved by conductive AFM (C-AFM).
This work demonstrates that it is possible to retrieve data stored in a Toggle MRAM (130 nm technology node) and in a STT-MRAM (40 nm technology node) using invasive techniques. These components thus represent the two types of MRAM on the market, with classical and more advanced technology nodes. The data readout validates the sample preparation flow.
{"title":"Methodology for data retrieval of MRAM: Technological analysis, sample preparation and internal electrical measurements","authors":"Louise Dumas , Christina Villeneuve-Faure , François Marc , Hélène Fremont , Guillaume Bascoul , Christophe Guerin","doi":"10.1016/j.mee.2025.112351","DOIUrl":"10.1016/j.mee.2025.112351","url":null,"abstract":"<div><div>This paper presents the methodology to be applied in order to achieve the data retrieval of any magneto-resistive random access memory (MRAM) on the market, whether it's a Toggle MRAM or a STT-MRAM. This methodology consists of four stages: theoretical study of the structure, technological analysis to identify the physical structure of the memory, preparation of the memory to make the data accessible, and readout of those data.</div><div>Knowing the structural elements and how the MRAM is read/written allows the possibility to do its technological analysis. Then, this analysis allows the identification of the magnetic tunnel junction (MTJ), where the data (‘0’ / ‘1’) is stored as resistance states, and of its surroundings, mainly the bitline. Once this is done, a complex preparation of the device's backside is achieved to expose both sides of the MTJ: one side to apply the voltage and the other to collect the current. The sample preparation methodology consists of a chemical opening, a polishing down to the transistors, focused ion beam (FIB) etches of metallization levels surrounding the MTJ and metal deposition. Finally, the memory can be read by techniques derived from atomic force microscopy (AFM). For both memory types, the discrimination of the bit states is proved by conductive AFM (C-AFM).</div><div>This work demonstrates that it is possible to retrieve data stored in a Toggle MRAM (130 nm technology node) and in a STT-MRAM (40 nm technology node) using invasive techniques. These components thus represent the two types of MRAM on the market, with classical and more advanced technology nodes. The data readout validates the sample preparation flow.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112351"},"PeriodicalIF":2.6,"publicationDate":"2025-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143873883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-15Epub Date: 2025-03-20DOI: 10.1016/j.mee.2025.112344
Georg Zachl , Christoph Mangiavillano , Tim Schumacher , Richard Hüttner , Patrick Fath , Christoph Wagner , Andreas Stelzer , Harald Pretl
A 0.324-THz multiplier-based (x16) transmitter with an on-chip patch antenna for application in phased arrays and plastic microwave fiber links has been implemented in a 130-nm SiGe:C bipolar CMOS technology with an of 350/450 GHz. The chiplet features integrated digitally programmable power management and biasing for post‑silicon optimization. Each radio frequency circuit block can be individually tuned by a bias current generator, and a total of three programmable voltage regulators supply the three bootstrapped doublers used from 20-to-160 GHz, the two-stage 160-GHz power amplifier and the 0.32-THz frequency doubler, respectively. After rigorous optimization, measurements reveal a single-chain dc-to-THz efficiency of 2.65 % with an output power up to 6.6 dBm at 0.324 THz. The dc power consumption was 170 mW. Operated in a 1-by-4 phased array, a maximum effective isotropic radiated power of 13.1 dBm with an output power of 2.9 dBm has been measured. Beam steering is demonstrated, revealing beam scanning over 22° in one plane. Used as a transmitter for plastic microwave fiber links, the on-chip antenna enables contactless coupling to the fiber, showing overall significantly reduced path losses compared to over-the-air links. A close-to-real-world demonstration of a PMF link with up to 3.25 Gbit/s using QPSK modulation is presented, using separate unsynchronized transmitter and receiver LO signal sources.
{"title":"A 0.324-THz transmitter based on individual 2.65 % efficiency x16 frequency multiplier chiplets for phased-array and PMF applications","authors":"Georg Zachl , Christoph Mangiavillano , Tim Schumacher , Richard Hüttner , Patrick Fath , Christoph Wagner , Andreas Stelzer , Harald Pretl","doi":"10.1016/j.mee.2025.112344","DOIUrl":"10.1016/j.mee.2025.112344","url":null,"abstract":"<div><div>A 0.324-THz multiplier-based (x16) transmitter with an on-chip patch antenna for application in phased arrays and plastic microwave fiber links has been implemented in a 130-nm SiGe:C bipolar CMOS technology with an <span><math><msub><mi>f</mi><mi>T</mi></msub><mo>/</mo><msub><mi>f</mi><mi>max</mi></msub></math></span> of 350/450 GHz. The chiplet features integrated digitally programmable power management and biasing for post‑silicon optimization. Each radio frequency circuit block can be individually tuned by a bias current generator, and a total of three programmable voltage regulators supply the three bootstrapped doublers used from 20-to-160 GHz, the two-stage 160-GHz power amplifier and the 0.32-THz frequency doubler, respectively. After rigorous optimization, measurements reveal a single-chain dc-to-THz efficiency of 2.65 % with an output power up to 6.6 dBm at 0.324 THz. The dc power consumption was 170 mW. Operated in a 1-by-4 phased array, a maximum effective isotropic radiated power of 13.1 dBm with an output power of 2.9 dBm has been measured. Beam steering is demonstrated, revealing beam scanning over 22° in one plane. Used as a transmitter for plastic microwave fiber links, the on-chip antenna enables contactless coupling to the fiber, showing overall significantly reduced path losses compared to over-the-air links. A close-to-real-world demonstration of a PMF link with up to 3.25 Gbit/s using QPSK modulation is presented, using separate unsynchronized transmitter and receiver LO signal sources.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112344"},"PeriodicalIF":2.6,"publicationDate":"2025-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143747299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-15Epub Date: 2025-04-11DOI: 10.1016/j.mee.2025.112348
Reshma Ravindran, Ahmed M. Massoud
High-efficiency power electronic converters are imperative for future applications aiming to meet sustainability goals, as increased efficiency translates to reduced energy consumption. The emerging wide bandgap technology is a key enabler, offering better efficiency, power density, switching speed, and reduced size and weight. In view of this, we present an extensive overview of wide bandgap and ultra-wide bandgap devices for present & next-generation power electronics applications. The electrical characteristics of these devices are compared in this article, along with their present state and projected future developments. The current status of wide bandgap and ultra-wide bandgap devices' applicability for a wide range of emerging power electronics application areas, including solid-state transformers, data centers, ultra-fast electric vehicle charging stations, renewable energy generation, energy storage systems, solid-state circuit breakers, military electronic warfare systems, graphics processing units, quantum computers, and 6G networks, is reviewed. Furthermore, the expectations for these devices for the future of each of these applications are assessed, and the related future challenges and opportunities are discussed. The study shows that while SiC semiconductors will continue to dominate in high-power, high-voltage applications like transportation, grid-side converters, solid-state transformers, and renewable energy integration, GaN semiconductors will be crucial for low-voltage, high-frequency applications such as consumer electronics, power supplies, and data centers. Although not yet commercialized, ultra-wide bandgap devices like Diamond, and , with their exceptional material properties, are projected to be indispensable for high-power, high-frequency power electronics applications.
{"title":"An overview of wide and ultra wide bandgap semiconductors for next-generation power electronics applications","authors":"Reshma Ravindran, Ahmed M. Massoud","doi":"10.1016/j.mee.2025.112348","DOIUrl":"10.1016/j.mee.2025.112348","url":null,"abstract":"<div><div>High-efficiency power electronic converters are imperative for future applications aiming to meet sustainability goals, as increased efficiency translates to reduced energy consumption. The emerging wide bandgap technology is a key enabler, offering better efficiency, power density, switching speed, and reduced size and weight. In view of this, we present an extensive overview of wide bandgap and ultra-wide bandgap devices for present & next-generation power electronics applications. The electrical characteristics of these devices are compared in this article, along with their present state and projected future developments. The current status of wide bandgap and ultra-wide bandgap devices' applicability for a wide range of emerging power electronics application areas, including solid-state transformers, data centers, ultra-fast electric vehicle charging stations, renewable energy generation, energy storage systems, solid-state circuit breakers, military electronic warfare systems, graphics processing units, quantum computers, and 6G networks, is reviewed. Furthermore, the expectations for these devices for the future of each of these applications are assessed, and the related future challenges and opportunities are discussed. The study shows that while SiC semiconductors will continue to dominate in high-power, high-voltage applications like transportation, grid-side converters, solid-state transformers, and renewable energy integration, GaN semiconductors will be crucial for low-voltage, high-frequency applications such as consumer electronics, power supplies, and data centers. Although not yet commercialized, ultra-wide bandgap devices like Diamond, and <span><math><mi>β</mi><mo>−</mo><msub><mi>Ga</mi><mn>2</mn></msub><msub><mi>O</mi><mn>3</mn></msub></math></span>, with their exceptional material properties, are projected to be indispensable for high-power, high-frequency power electronics applications.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112348"},"PeriodicalIF":2.6,"publicationDate":"2025-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143815171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-15Epub Date: 2025-05-27DOI: 10.1016/j.mee.2025.112364
A. Kaltzoglou , E. Christopoulos , D.N. Kossyvakis , N.S. Tagiara , P. Falaras , N.K. Nasikas , E.V. Hristoforou , M.M. Elsenety
The commercialization of perovskite solar cells (PSCs) has been restricted so far due to their short life time, which is partly attributed to their instability at high operating temperatures. The current paper studies the performance of the cells under Peltier cooling. The experimental setup includes a perovskite solar cell and a Peltier cooler beneath, where the latter is connected to an external power supply. The temperature on the surface of the solar cell spans over the range ca. 5 °C to 50 °C under 1 sun illumination, depending on the power input of the Peltier cooler. The J-V measurements indicate a non-linear temperature dependence of the power conversion efficiency (PCE), which reaches a maximum of 18.1 % at 27 °C, whereas at temperatures close to 50 °C the PCE drops significantly. The experimental results are combined with more generic theoretical simulations for scaling up the PSC unit, which provides electrical power to the Peltier unit. The simulations examine the ability of different system configurations to maintain the solar cell temperature below 50 °C without significant deterioration of the electrical performance of the hybrid PSC – Peltier device. Overall, the results show that a large-scale PSC – Peltier device is feasible for both roof-integrated and rooftop installation types, in order to protect the solar cell from overheating and degradation.
{"title":"Assessing the performance of perovskite solar cells under Peltier cooling","authors":"A. Kaltzoglou , E. Christopoulos , D.N. Kossyvakis , N.S. Tagiara , P. Falaras , N.K. Nasikas , E.V. Hristoforou , M.M. Elsenety","doi":"10.1016/j.mee.2025.112364","DOIUrl":"10.1016/j.mee.2025.112364","url":null,"abstract":"<div><div>The commercialization of perovskite solar cells (PSCs) has been restricted so far due to their short life time, which is partly attributed to their instability at high operating temperatures. The current paper studies the performance of the cells under Peltier cooling. The experimental setup includes a perovskite solar cell and a Peltier cooler beneath, where the latter is connected to an external power supply. The temperature on the surface of the solar cell spans over the range ca. 5 °C to 50 °C under 1 sun illumination, depending on the power input of the Peltier cooler. The <em>J</em>-<em>V</em> measurements indicate a non-linear temperature dependence of the power conversion efficiency (PCE), which reaches a maximum of 18.1 % at 27 °C, whereas at temperatures close to 50 °C the PCE drops significantly. The experimental results are combined with more generic theoretical simulations for scaling up the PSC unit, which provides electrical power to the Peltier unit. The simulations examine the ability of different system configurations to maintain the solar cell temperature below 50 °C without significant deterioration of the electrical performance of the hybrid PSC – Peltier device. Overall, the results show that a large-scale PSC – Peltier device is feasible for both roof-integrated and rooftop installation types, in order to protect the solar cell from overheating and degradation.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112364"},"PeriodicalIF":2.6,"publicationDate":"2025-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144166750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-15Epub Date: 2025-05-09DOI: 10.1016/j.mee.2025.112356
Haoxiong Bi , Pengju Wang , Jiabao Ye , Liang Zhao , Yuejun Zhang , Bing Chen
Encryption is a crucial aspect of data security, and the Data Encryption Standard (DES) was the first encryption algorithm to gain global recognition. However, due to its dependence on the traditional von Neumann architecture, DES suffers from high resource consumption, transmission delays, and vulnerability to power-based attacks. To address these challenges, this paper introduces a logic-in-memory (LIM) encryption circuit using resistive random-access memory (RRAM). This approach reduces the risk of key interception by minimizing key transfers between the CPU and memory. The DES algorithm was implemented on a Xilinx Spartan-6 FPGA, and power consumption was analyzed using correlation power analysis and template attacks. The results demonstrate that the proposed LIM encryption circuit has better power attack resistance than the conventional designs.
{"title":"A RRAM-based logic in memory DES implementation against power attacks","authors":"Haoxiong Bi , Pengju Wang , Jiabao Ye , Liang Zhao , Yuejun Zhang , Bing Chen","doi":"10.1016/j.mee.2025.112356","DOIUrl":"10.1016/j.mee.2025.112356","url":null,"abstract":"<div><div>Encryption is a crucial aspect of data security, and the Data Encryption Standard (DES) was the first encryption algorithm to gain global recognition. However, due to its dependence on the traditional von Neumann architecture, DES suffers from high resource consumption, transmission delays, and vulnerability to power-based attacks. To address these challenges, this paper introduces a logic-in-memory (LIM) encryption circuit using resistive random-access memory (RRAM). This approach reduces the risk of key interception by minimizing key transfers between the CPU and memory. The DES algorithm was implemented on a Xilinx Spartan-6 FPGA, and power consumption was analyzed using correlation power analysis and template attacks. The results demonstrate that the proposed LIM encryption circuit has better power attack resistance than the conventional designs.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112356"},"PeriodicalIF":2.6,"publicationDate":"2025-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144107775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-15Epub Date: 2025-05-02DOI: 10.1016/j.mee.2025.112358
J. Joslin Percy , S. Kanthamani , S. Mohamed Mansoor Roomi , Thennarasan Sabapathy
The textile industry requires real-time tracking of products for effective inventory management and to prevent inventory shrinkage. Radio Frequency Identification (RFID) Tags have proved to be an efficient solution for tracking products in the textile industry. Several integration methodologies for RFID tags in textile industries have been proposed to enhance the efficiency of real-time product tracking. This paper provides a survey of textile-based RFID tag integration methods. A comparative study of these tags and their performance has been presented. This paper aims to provide insights for researchers to establish new research agendas in adopting various integration methods for RFID tags in the textile industry.
{"title":"Strategies and approaches for RFID tag integration in textiles","authors":"J. Joslin Percy , S. Kanthamani , S. Mohamed Mansoor Roomi , Thennarasan Sabapathy","doi":"10.1016/j.mee.2025.112358","DOIUrl":"10.1016/j.mee.2025.112358","url":null,"abstract":"<div><div>The textile industry requires real-time tracking of products for effective inventory management and to prevent inventory shrinkage. Radio Frequency Identification (RFID) Tags have proved to be an efficient solution for tracking products in the textile industry. Several integration methodologies for RFID tags in textile industries have been proposed to enhance the efficiency of real-time product tracking. This paper provides a survey of textile-based RFID tag integration methods. A comparative study of these tags and their performance has been presented. This paper aims to provide insights for researchers to establish new research agendas in adopting various integration methods for RFID tags in the textile industry.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112358"},"PeriodicalIF":2.6,"publicationDate":"2025-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143918100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-15Epub Date: 2025-05-07DOI: 10.1016/j.mee.2025.112354
Lingrui Zou , Pu Feng , Peipei Jing , Chaoqun Dang , Haiming Zhu , Xin He , Lijie Zhang , Tao Wang , Fei Xue
The recent discovery of two-dimensional ferroelectric semiconductors, such as In2Se3, has opened promising avenues for ultra-thin micro-nano electronic devices, and energy-efficient neuromorphic systems. Despite these exciting prospects, achieving large-area, high-quality, layer-controlled growth of single-phase In2Se3 remains a considerable challenge. In this study, we present a seed-assisted strategy for growing uniform, centimeter-scale β'-In2Se3 thin films by mixing In2O3 and In2Se3 single crystals in a specific ratio. The resulting β'-In2Se3 phase and composition are verified through X-ray diffraction, transmission electron microscopy, and Raman spectroscopy. Furthermore, the ferroelectric properties and domain configurations have been characterized by using polarized light microscopy and piezoresponse force microscopy. Importantly, we investigate the topological evolution of ferroelectric domains across films with varying thicknesses, revealing insights into domain structure modulation. This growth method not only provides a scalable route for synthesizing similar ferroelectric two-dimensional materials but also a possibility for the practical integration of β'-In2Se3 in optoelectronic, neuromorphic, and other advanced micro-nano electronic applications.
{"title":"Seed-assisted growth of large-area β'-In2Se3 ferroelectric thin films","authors":"Lingrui Zou , Pu Feng , Peipei Jing , Chaoqun Dang , Haiming Zhu , Xin He , Lijie Zhang , Tao Wang , Fei Xue","doi":"10.1016/j.mee.2025.112354","DOIUrl":"10.1016/j.mee.2025.112354","url":null,"abstract":"<div><div>The recent discovery of two-dimensional ferroelectric semiconductors, such as In<sub>2</sub>Se<sub>3</sub>, has opened promising avenues for ultra-thin micro-nano electronic devices, and energy-efficient neuromorphic systems. Despite these exciting prospects, achieving large-area, high-quality, layer-controlled growth of single-phase In<sub>2</sub>Se<sub>3</sub> remains a considerable challenge. In this study, we present a seed-assisted strategy for growing uniform, centimeter-scale β'-In<sub>2</sub>Se<sub>3</sub> thin films by mixing In<sub>2</sub>O<sub>3</sub> and In<sub>2</sub>Se<sub>3</sub> single crystals in a specific ratio. The resulting β'-In<sub>2</sub>Se<sub>3</sub> phase and composition are verified through X-ray diffraction, transmission electron microscopy, and Raman spectroscopy. Furthermore, the ferroelectric properties and domain configurations have been characterized by using polarized light microscopy and piezoresponse force microscopy. Importantly, we investigate the topological evolution of ferroelectric domains across films with varying thicknesses, revealing insights into domain structure modulation. This growth method not only provides a scalable route for synthesizing similar ferroelectric two-dimensional materials but also a possibility for the practical integration of β'-In<sub>2</sub>Se<sub>3</sub> in optoelectronic, neuromorphic, and other advanced micro-nano electronic applications.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112354"},"PeriodicalIF":2.6,"publicationDate":"2025-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143918161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-15Epub Date: 2025-03-10DOI: 10.1016/j.mee.2025.112334
P. Favia , G. Eneman , A. Veloso , A. Nalin Mehta , G.T. Martinez , O. Richard , A. Hikavyy , P.P. Gowda , F. Seidel , G. Pourtois , A. De Keersgieter , E. Grieten
Strain engineering is a common approach for enhancing the mobility of semiconductor materials and improving the performance of conventional and novel transistors. Understanding the strain distribution is important for optimizing device characteristics. Transmission electron microscopy (TEM) is a crucial technique for evaluating strain at the nanoscale. However, due to the ongoing reduction in electronic device dimensions, assessing strain via TEM has become increasingly challenging. Many different techniques have been developed in recent years with the aim of analysing complex structures. In this work, we investigate the capabilities of the recently developed Bessel beam electron diffraction (BBED) method to evaluate strain by TEM in fully processed fin-field effect transistor (FinFET) devices and in cutting edge nano-sheet complementary-FET (NS-CFET) technology.
TEM analysis of fully processed devices is challenging due to the presence of artefacts generated by different materials and multiple structures overlapping in projection in TEM images. We demonstrate the capability of the BBED technique to reveal strain in fully processed FinFET while exploring the dependence of strain on layout variations.
NS-CFETs are an attractive device architecture for beyond 1 nm logic technology nodes. Strain distribution in these devices is more complex than in FinFETs due to the presence of very thin layers and reduced channel dimensions. We compare the BBED method with the well-known techniques of nano-beam electron diffraction (NBED) and geometric phase analysis (GPA) for analysing strain in these structures. The BBED technique, despite a simple experimental setup, shows good accuracy and spatial resolution, being able to resolve interlayers thinner than 2 nm. Compared to NBED and GPA, the BBED technique offers better performance and is therefore a promising method to study strain in future transistor devices.
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