This work investigates the impact of the device technological parameter - gate-drain access region spacing () - for GaN High Electron Mobility Transistors (HEMTs), on the design of low noise amplifiers (LNAs) for the 3–4 GHz range. We compare two GaN LNA variants, characterized by values of and , to highlight the significance of gate-drain spacings in determining performance metrics. This study contributes insights into the effect of gate-drain spacing on the GaN LNAs, and evaluates the RF characteristics, Noise Fig. (NF), and power metrics for different values. Based on our findings, we assert that the LNA exhibits superior performance over its counterpart in the evaluated benchmarks, along with the physical reasoning.
{"title":"Comprehensive analysis and investigation of GaN LNA for 3–4 GHz using different gate-drain spacing","authors":"Md Hasnain Ansari , Siddharth Thakur , Neha Bajpai , Paramita Maity , Avinash Lahgere , Sheikh Aamir Ahsan , Manish Shah , Yogesh Singh Chauhan","doi":"10.1016/j.mee.2025.112361","DOIUrl":"10.1016/j.mee.2025.112361","url":null,"abstract":"<div><div>This work investigates the impact of the device technological parameter - gate-drain access region spacing (<span><math><msub><mi>L</mi><mi>GD</mi></msub></math></span>) - for GaN High Electron Mobility Transistors (HEMTs), on the design of low noise amplifiers (LNAs) for the 3–4 GHz range. We compare two GaN LNA variants, characterized by <span><math><msub><mi>L</mi><mi>GD</mi></msub></math></span> values of <span><math><mn>0.875</mn><mspace></mspace><mi>μ</mi><mi>m</mi></math></span> and <span><math><mn>1</mn><mspace></mspace><mi>μ</mi><mi>m</mi></math></span>, to highlight the significance of gate-drain spacings in determining performance metrics. This study contributes insights into the effect of gate-drain spacing on the GaN LNAs, and evaluates the RF characteristics, Noise Fig. (NF), and power metrics for different <span><math><msub><mi>L</mi><mi>GD</mi></msub></math></span> values. Based on our findings, we assert that the <span><math><mn>0.875</mn><mspace></mspace><mi>μ</mi><mi>m</mi><mspace></mspace><msub><mi>L</mi><mi>GD</mi></msub></math></span> LNA exhibits superior performance over its counterpart in the evaluated benchmarks, along with the physical reasoning.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112361"},"PeriodicalIF":2.6,"publicationDate":"2025-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144134427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-05-16DOI: 10.1016/j.mee.2025.112357
Yunfei Shi , Songyi Jiang , Hong Yang , Yongkui Zhang , Longda Zhou , Zhigang Ji , Qianqian Liu , Qi Wang , Huilong Zhu , Jun Luo , Wenwu Wang
In this article, the influence of Forming Gas Annealing (FGA) on the Positive Bias Temperature Instability (PBTI) characteristics of n-vertical C-shaped-channel nanosheet FET (n-VCNFET) is studied. The experimental results show that the extra FGA can significantly suppress both the initial and generated interface traps in PBTI. Moreover, in ultra-fast PBTI the pre-existing trap and total trap of VCNFET due to FGA decreases by 35 % and 31 %, respectively. The energy level of the oxide trap under PBTI and recovery doesn't change, in other words, the FGA induces the oxide trap density of the devices to decrease by 36 % at 125 °C and 1.4 V VOV. The optimization effect of FGA annealing has been further confirmed from the perspective of trap generation. It provides a guideline for the PBTI improvement of VCNFET in trap scopes.
本文研究了成形气体退火（FGA）对n-垂直c形沟道纳米片场效应管（n-VCNFET）正偏置温度不稳定性（PBTI）特性的影响。实验结果表明，额外的FGA可以显著抑制PBTI中初始和生成的界面陷阱。此外，在超高速PBTI中，由于FGA导致的VCNFET的原有陷阱和总陷阱分别减少了35%和31%。在125°C和1.4 V VOV下，FGA诱导器件的氧化阱密度降低了36%。从陷阱生成的角度进一步证实了FGA退火的优化效果。为VCNFET在陷阱范围内的PBTI改进提供了指导。
{"title":"Improved positive bias temperature instability of n-type vertical C-shaped-channel nanosheet FET by forming gas annealing","authors":"Yunfei Shi , Songyi Jiang , Hong Yang , Yongkui Zhang , Longda Zhou , Zhigang Ji , Qianqian Liu , Qi Wang , Huilong Zhu , Jun Luo , Wenwu Wang","doi":"10.1016/j.mee.2025.112357","DOIUrl":"10.1016/j.mee.2025.112357","url":null,"abstract":"<div><div>In this article, the influence of Forming Gas Annealing (FGA) on the Positive Bias Temperature Instability (PBTI) characteristics of n-vertical C-shaped-channel nanosheet FET (n-VCNFET) is studied. The experimental results show that the extra FGA can significantly suppress both the initial and generated interface traps in PBTI. Moreover, in ultra-fast PBTI the pre-existing trap and total trap of VCNFET due to FGA decreases by 35 % and 31 %, respectively. The energy level of the oxide trap under PBTI and recovery doesn't change, in other words, the FGA induces the oxide trap density of the devices to decrease by 36 % at 125 °C and 1.4 V V<sub>OV</sub>. The optimization effect of FGA annealing has been further confirmed from the perspective of trap generation. It provides a guideline for the PBTI improvement of VCNFET in trap scopes.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112357"},"PeriodicalIF":2.6,"publicationDate":"2025-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144068285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-05-14DOI: 10.1016/j.mee.2025.112359
P. Murugapandiyan , A.S. Augustine Fletcher , Md. Tanvir Hasan , N. Ramkumar , A. Revathy
Beta‑gallium oxide (β-Ga2O3) has emerged as a promising semiconductor material for next-generation power electronics due to its ultra-wide bandgap (4.9 eV), exceptional breakdown electric field (8 MV/cm), and compatibility with cost-effective melt growth methods for producing large-area single crystals. This comprehensive review examines recent advances in β-Ga2O3 metal-oxide-semiconductor field-effect transistors (MOSFETs), spanning from material synthesis to device implementation. The review then investigates device architectures, examining both depletion-mode and enhancement-mode β-Ga2O3 MOSFETs. We highlight crucial design elements including field plates, innovative gate structures, and channel engineering techniques that have enabled devices with breakdown voltages exceeding 2.3 kV and power figures of merit surpassing 150 MW/cm2. Additionally, we address significant challenges, particularly thermal management issues stemming from β-Ga2O3's relatively low thermal conductivity (10–20 W/m·K) and the current absence of p-type doping capability, discussing various proposed solutions including diamond heat spreaders, heterogeneous substrate integration, and advanced packaging approaches. Finally, we examine emerging concepts such as nanomembrane transistors, fin structures, and heterojunction FETs, concluding with insights on future research directions for this promising semiconductor technology.
{"title":"Recent advancement in β-Ga2O3 MOSFETs: From material growth to device architectures for high-power electronics","authors":"P. Murugapandiyan , A.S. Augustine Fletcher , Md. Tanvir Hasan , N. Ramkumar , A. Revathy","doi":"10.1016/j.mee.2025.112359","DOIUrl":"10.1016/j.mee.2025.112359","url":null,"abstract":"<div><div>Beta‑gallium oxide (β-Ga<sub>2</sub>O<sub>3</sub>) has emerged as a promising semiconductor material for next-generation power electronics due to its ultra-wide bandgap (4.9 eV), exceptional breakdown electric field (8 MV/cm), and compatibility with cost-effective melt growth methods for producing large-area single crystals. This comprehensive review examines recent advances in β-Ga<sub>2</sub>O<sub>3</sub> metal-oxide-semiconductor field-effect transistors (MOSFETs), spanning from material synthesis to device implementation. The review then investigates device architectures, examining both depletion-mode and enhancement-mode β-Ga<sub>2</sub>O<sub>3</sub> MOSFETs. We highlight crucial design elements including field plates, innovative gate structures, and channel engineering techniques that have enabled devices with breakdown voltages exceeding 2.3 kV and power figures of merit surpassing 150 MW/cm<sup>2</sup>. Additionally, we address significant challenges, particularly thermal management issues stemming from β-Ga<sub>2</sub>O<sub>3</sub>'s relatively low thermal conductivity (10–20 W/m·K) and the current absence of p-type doping capability, discussing various proposed solutions including diamond heat spreaders, heterogeneous substrate integration, and advanced packaging approaches. Finally, we examine emerging concepts such as nanomembrane transistors, fin structures, and heterojunction FETs, concluding with insights on future research directions for this promising semiconductor technology.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112359"},"PeriodicalIF":2.6,"publicationDate":"2025-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144071119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the advent of FinFET technology, especially in the application of 14 nm and above nodes, the front-end-of-line (FEOL) defects at the transistor level have become increasingly significant. These minute FEOL defects have a critical impact on the yield and reliability of the ultimate chipset. This paper focuses on two types of FEOL defects identified in 14 nm FinFET technology. The research shows that both of these FEOL defects can lead to leakage in MOSFETs. We have conducted an in-depth analysis of the distinct failure mechanisms of these two defects and their potential formation causes. It is expected to help wafer factories achieve effective improvements. The study indicates that these two failure modes might be triggered by oxide defects in different steps of the FEOL process flow. Specifically, in one case, dielectric breakdown-induced epitaxy (DBIE) causes NMOS gate leakage, which might be ascribed to the presence of defects in the bottom interface layer (BIL) of the oxide. In another instance, PMOS leakage caused by germanium bridge defects might result from oxide defects as the etch stop layer (ESL) and the influence of subsequent process steps on the defects. This research provides an essential guiding direction for wafer factories to optimize the manufacturing process of 14 nm FinFET products and improve yield and quality. At the same time, this study also offers a valuable reference basis for the failure analysis of FinFET devices.
{"title":"Study on different failure mechanisms of MOSFET caused by different oxide defects in 14 nm FinFET IC","authors":"Yanfen Wang, Shijun Zheng, Shan Zhang, Junsheng Wang, Guang Lu, Gaojie Wen","doi":"10.1016/j.mee.2025.112350","DOIUrl":"10.1016/j.mee.2025.112350","url":null,"abstract":"<div><div>With the advent of FinFET technology, especially in the application of 14 nm and above nodes, the front-end-of-line (FEOL) defects at the transistor level have become increasingly significant. These minute FEOL defects have a critical impact on the yield and reliability of the ultimate chipset. This paper focuses on two types of FEOL defects identified in 14 nm FinFET technology. The research shows that both of these FEOL defects can lead to leakage in MOSFETs. We have conducted an in-depth analysis of the distinct failure mechanisms of these two defects and their potential formation causes. It is expected to help wafer factories achieve effective improvements. The study indicates that these two failure modes might be triggered by oxide defects in different steps of the FEOL process flow. Specifically, in one case, dielectric breakdown-induced epitaxy (DBIE) causes NMOS gate leakage, which might be ascribed to the presence of defects in the bottom interface layer (BIL) of the oxide. In another instance, PMOS leakage caused by germanium bridge defects might result from oxide defects as the etch stop layer (ESL) and the influence of subsequent process steps on the defects. This research provides an essential guiding direction for wafer factories to optimize the manufacturing process of 14 nm FinFET products and improve yield and quality. At the same time, this study also offers a valuable reference basis for the failure analysis of FinFET devices.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112350"},"PeriodicalIF":2.6,"publicationDate":"2025-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143927984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-05-09DOI: 10.1016/j.mee.2025.112356
Haoxiong Bi , Pengju Wang , Jiabao Ye , Liang Zhao , Yuejun Zhang , Bing Chen
Encryption is a crucial aspect of data security, and the Data Encryption Standard (DES) was the first encryption algorithm to gain global recognition. However, due to its dependence on the traditional von Neumann architecture, DES suffers from high resource consumption, transmission delays, and vulnerability to power-based attacks. To address these challenges, this paper introduces a logic-in-memory (LIM) encryption circuit using resistive random-access memory (RRAM). This approach reduces the risk of key interception by minimizing key transfers between the CPU and memory. The DES algorithm was implemented on a Xilinx Spartan-6 FPGA, and power consumption was analyzed using correlation power analysis and template attacks. The results demonstrate that the proposed LIM encryption circuit has better power attack resistance than the conventional designs.
{"title":"A RRAM-based logic in memory DES implementation against power attacks","authors":"Haoxiong Bi , Pengju Wang , Jiabao Ye , Liang Zhao , Yuejun Zhang , Bing Chen","doi":"10.1016/j.mee.2025.112356","DOIUrl":"10.1016/j.mee.2025.112356","url":null,"abstract":"<div><div>Encryption is a crucial aspect of data security, and the Data Encryption Standard (DES) was the first encryption algorithm to gain global recognition. However, due to its dependence on the traditional von Neumann architecture, DES suffers from high resource consumption, transmission delays, and vulnerability to power-based attacks. To address these challenges, this paper introduces a logic-in-memory (LIM) encryption circuit using resistive random-access memory (RRAM). This approach reduces the risk of key interception by minimizing key transfers between the CPU and memory. The DES algorithm was implemented on a Xilinx Spartan-6 FPGA, and power consumption was analyzed using correlation power analysis and template attacks. The results demonstrate that the proposed LIM encryption circuit has better power attack resistance than the conventional designs.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112356"},"PeriodicalIF":2.6,"publicationDate":"2025-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144107775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-05-07DOI: 10.1016/j.mee.2025.112354
Lingrui Zou , Pu Feng , Peipei Jing , Chaoqun Dang , Haiming Zhu , Xin He , Lijie Zhang , Tao Wang , Fei Xue
The recent discovery of two-dimensional ferroelectric semiconductors, such as In2Se3, has opened promising avenues for ultra-thin micro-nano electronic devices, and energy-efficient neuromorphic systems. Despite these exciting prospects, achieving large-area, high-quality, layer-controlled growth of single-phase In2Se3 remains a considerable challenge. In this study, we present a seed-assisted strategy for growing uniform, centimeter-scale β'-In2Se3 thin films by mixing In2O3 and In2Se3 single crystals in a specific ratio. The resulting β'-In2Se3 phase and composition are verified through X-ray diffraction, transmission electron microscopy, and Raman spectroscopy. Furthermore, the ferroelectric properties and domain configurations have been characterized by using polarized light microscopy and piezoresponse force microscopy. Importantly, we investigate the topological evolution of ferroelectric domains across films with varying thicknesses, revealing insights into domain structure modulation. This growth method not only provides a scalable route for synthesizing similar ferroelectric two-dimensional materials but also a possibility for the practical integration of β'-In2Se3 in optoelectronic, neuromorphic, and other advanced micro-nano electronic applications.
{"title":"Seed-assisted growth of large-area β'-In2Se3 ferroelectric thin films","authors":"Lingrui Zou , Pu Feng , Peipei Jing , Chaoqun Dang , Haiming Zhu , Xin He , Lijie Zhang , Tao Wang , Fei Xue","doi":"10.1016/j.mee.2025.112354","DOIUrl":"10.1016/j.mee.2025.112354","url":null,"abstract":"<div><div>The recent discovery of two-dimensional ferroelectric semiconductors, such as In<sub>2</sub>Se<sub>3</sub>, has opened promising avenues for ultra-thin micro-nano electronic devices, and energy-efficient neuromorphic systems. Despite these exciting prospects, achieving large-area, high-quality, layer-controlled growth of single-phase In<sub>2</sub>Se<sub>3</sub> remains a considerable challenge. In this study, we present a seed-assisted strategy for growing uniform, centimeter-scale β'-In<sub>2</sub>Se<sub>3</sub> thin films by mixing In<sub>2</sub>O<sub>3</sub> and In<sub>2</sub>Se<sub>3</sub> single crystals in a specific ratio. The resulting β'-In<sub>2</sub>Se<sub>3</sub> phase and composition are verified through X-ray diffraction, transmission electron microscopy, and Raman spectroscopy. Furthermore, the ferroelectric properties and domain configurations have been characterized by using polarized light microscopy and piezoresponse force microscopy. Importantly, we investigate the topological evolution of ferroelectric domains across films with varying thicknesses, revealing insights into domain structure modulation. This growth method not only provides a scalable route for synthesizing similar ferroelectric two-dimensional materials but also a possibility for the practical integration of β'-In<sub>2</sub>Se<sub>3</sub> in optoelectronic, neuromorphic, and other advanced micro-nano electronic applications.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112354"},"PeriodicalIF":2.6,"publicationDate":"2025-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143918161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-05-05DOI: 10.1016/j.mee.2025.112347
Guoqiang Zhao , Yi Zhao
During the scaling down of hybrid bonding pairs, controllable misalignment is particularly important for ensuring remarkable electrical performance. This article presents the finite element modeling methodology to preview the significance of misalignment on resistance and capacitance values. Design parameters such as the via array, pad size, shape, and asymmetric structure are comprehensively considered. The results show that the electrical properties of interconnects at the small pitch is more sensitive to misalignment. The via array affects the current distribution serving as the inter-metal connection channel. The size and shape of the pad directly determine the effective contact area and effective space under various misalignment. The alignment error redundancy provided by the asymmetric structure is an option to alleviate the problem. This work contributes to understanding the impact weight of misalignment on electrical performance under different design conditions and formulating appropriate alignment rules.
{"title":"Finite element modeling analysis of misalignment impact on simulated electrical RC in scaling hybrid bonding pairs","authors":"Guoqiang Zhao , Yi Zhao","doi":"10.1016/j.mee.2025.112347","DOIUrl":"10.1016/j.mee.2025.112347","url":null,"abstract":"<div><div>During the scaling down of hybrid bonding pairs, controllable misalignment is particularly important for ensuring remarkable electrical performance. This article presents the finite element modeling methodology to preview the significance of misalignment on resistance and capacitance values. Design parameters such as the via array, pad size, shape, and asymmetric structure are comprehensively considered. The results show that the electrical properties of interconnects at the small pitch is more sensitive to misalignment. The via array affects the current distribution serving as the inter-metal connection channel. The size and shape of the pad directly determine the effective contact area and effective space under various misalignment. The alignment error redundancy provided by the asymmetric structure is an option to alleviate the problem. This work contributes to understanding the impact weight of misalignment on electrical performance under different design conditions and formulating appropriate alignment rules.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112347"},"PeriodicalIF":2.6,"publicationDate":"2025-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143903722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-05-02DOI: 10.1016/j.mee.2025.112355
Jiaheng Pan , Yanwei Sun , Shengyao Jia , Xudong Shen , Yiran Wang , Shien Wu , Cheng Pan , Mang Shi , Ge Shi
In this research article, we propose a tunable floating-type memristor emulator circuit with long-term memory (LTM) capabilities. The overall circuit consists of a Voltage Differential Transconductance Amplifier (VDTA), a Voltage Differential Complementary Amplifier (VDCA), and other basic components. The proposed emulator effectively prevents charge leakage on the capacitor by incorporating a switching circuit, thereby achieving long-term memory functionality. The emulator operates stably at a frequency of 10 MHz and supports seamless switching between incremental and decremental modes by altering the polarity of the input voltage. Moreover, the emulator exhibits excellent tunability, allowing adjustments to the equivalent memristor model by modifying the bias voltage and the aspect ratio of MOS transistors. The proposed emulator has been laid out and simulated using TSMC 0.18 μm process parameters in the Cadence Virtuoso platform. The simulation results align perfectly with the design and analysis, confirming the feasibility of the circuit. Finally, we explore potential applications of the proposed emulator in read-write circuit and memristor array circuit.
{"title":"A new tunable floating memristor emulator circuit with long-term memory","authors":"Jiaheng Pan , Yanwei Sun , Shengyao Jia , Xudong Shen , Yiran Wang , Shien Wu , Cheng Pan , Mang Shi , Ge Shi","doi":"10.1016/j.mee.2025.112355","DOIUrl":"10.1016/j.mee.2025.112355","url":null,"abstract":"<div><div>In this research article, we propose a tunable floating-type memristor emulator circuit with long-term memory (LTM) capabilities. The overall circuit consists of a Voltage Differential Transconductance Amplifier (VDTA), a Voltage Differential Complementary Amplifier (VDCA), and other basic components. The proposed emulator effectively prevents charge leakage on the capacitor by incorporating a switching circuit, thereby achieving long-term memory functionality. The emulator operates stably at a frequency of 10 MHz and supports seamless switching between incremental and decremental modes by altering the polarity of the input voltage. Moreover, the emulator exhibits excellent tunability, allowing adjustments to the equivalent memristor model by modifying the bias voltage and the aspect ratio of MOS transistors. The proposed emulator has been laid out and simulated using TSMC 0.18 μm process parameters in the Cadence Virtuoso platform. The simulation results align perfectly with the design and analysis, confirming the feasibility of the circuit. Finally, we explore potential applications of the proposed emulator in read-write circuit and memristor array circuit.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112355"},"PeriodicalIF":2.6,"publicationDate":"2025-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143911628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-05-02DOI: 10.1016/j.mee.2025.112358
J. Joslin Percy , S. Kanthamani , S. Mohamed Mansoor Roomi , Thennarasan Sabapathy
The textile industry requires real-time tracking of products for effective inventory management and to prevent inventory shrinkage. Radio Frequency Identification (RFID) Tags have proved to be an efficient solution for tracking products in the textile industry. Several integration methodologies for RFID tags in textile industries have been proposed to enhance the efficiency of real-time product tracking. This paper provides a survey of textile-based RFID tag integration methods. A comparative study of these tags and their performance has been presented. This paper aims to provide insights for researchers to establish new research agendas in adopting various integration methods for RFID tags in the textile industry.
{"title":"Strategies and approaches for RFID tag integration in textiles","authors":"J. Joslin Percy , S. Kanthamani , S. Mohamed Mansoor Roomi , Thennarasan Sabapathy","doi":"10.1016/j.mee.2025.112358","DOIUrl":"10.1016/j.mee.2025.112358","url":null,"abstract":"<div><div>The textile industry requires real-time tracking of products for effective inventory management and to prevent inventory shrinkage. Radio Frequency Identification (RFID) Tags have proved to be an efficient solution for tracking products in the textile industry. Several integration methodologies for RFID tags in textile industries have been proposed to enhance the efficiency of real-time product tracking. This paper provides a survey of textile-based RFID tag integration methods. A comparative study of these tags and their performance has been presented. This paper aims to provide insights for researchers to establish new research agendas in adopting various integration methods for RFID tags in the textile industry.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112358"},"PeriodicalIF":2.6,"publicationDate":"2025-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143918100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-05-02DOI: 10.1016/j.mee.2025.112353
Anhan Liu , Shijun Yu , Shingo Nakamura , Akinari Sugiyama , Takashi Nishikawa , Dongwei Xu , Xiao Jin , Daixuan Wu , He Tian
The relentless miniaturization of critical feature sizes in integrated circuits has set increasingly stringent demands on the precision of via etching processes. Current research predominantly focuses on the development of gases and optimization of processes. However, the role of etching gas purity and the impact of gas impurities have not yet been the subject of dedicated studies. Here, the etching behavior of silicon dioxide using two different purities of etching gases is investigated, examining the etching rate and morphology of SiO2 films under identical etching parameters. Compared to 99.999 % purity, the 99.99999 % purity C4F8 gas achieves a more stable and uniform etching rate with sidewall angles of 86.6° (closer to a 90° angle). This is primarily attributed to the reduction of etch-active impurities in the C4F8 gas, which decreases etching variability and minimizes damage to the sidewall fluorocarbon protective layer. Our research provides theoretical and experimental support for the advancement of subsequent etching simulation studies and the application of high-purity etching gases.
{"title":"The role of etching gas purity in C4F8/Ar plasma to optimize SiO2 etching process","authors":"Anhan Liu , Shijun Yu , Shingo Nakamura , Akinari Sugiyama , Takashi Nishikawa , Dongwei Xu , Xiao Jin , Daixuan Wu , He Tian","doi":"10.1016/j.mee.2025.112353","DOIUrl":"10.1016/j.mee.2025.112353","url":null,"abstract":"<div><div>The relentless miniaturization of critical feature sizes in integrated circuits has set increasingly stringent demands on the precision of via etching processes. Current research predominantly focuses on the development of gases and optimization of processes. However, the role of etching gas purity and the impact of gas impurities have not yet been the subject of dedicated studies. Here, the etching behavior of silicon dioxide using two different purities of etching gases is investigated, examining the etching rate and morphology of SiO<sub>2</sub> films under identical etching parameters. Compared to 99.999 % purity, the 99.99999 % purity C<sub>4</sub>F<sub>8</sub> gas achieves a more stable and uniform etching rate with sidewall angles of 86.6° (closer to a 90° angle). This is primarily attributed to the reduction of etch-active impurities in the C<sub>4</sub>F<sub>8</sub> gas, which decreases etching variability and minimizes damage to the sidewall fluorocarbon protective layer. Our research provides theoretical and experimental support for the advancement of subsequent etching simulation studies and the application of high-purity etching gases.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112353"},"PeriodicalIF":2.6,"publicationDate":"2025-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143899199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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