Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425743
C. Chang, Ching-Yuan Yang
The paper describes a 16-GHz monolithic varactorless LC-tank VCO implemented in a 0.18-mum CMOS technology. Unlike the traditional tuning method by a varactor, in this work a tunable inductor, which is introduced by a transformer based on tuning currents from the active components controlled by the input voltage, is employed in the VCO. Without a varactor in the LC tank, the oscillator can easily arrive at the requirement for high-frequency operation. The VCO using a symmetry transformer provides the tuning range of 15.44 to 16.64 GHz (7.5%) at 1.8 V supply. With operating at 16-GHz frequency, the measured phase noise is -118.6 dBc/Hz at 1-MHz offset, and the VCO dissipates around 3.3 mA.
本文介绍了一种采用0.18 μ m CMOS技术实现的16ghz单片无变容LC-tank压控振荡器。与传统的变容管调谐方法不同，本工作采用了可调谐电感，该电感是由变压器引入的，基于输入电压控制的有源元件的调谐电流。在LC槽中没有变容管，振荡器可以很容易地达到高频工作的要求。采用对称变压器的压控振荡器在1.8 V电源下提供15.44至16.64 GHz(7.5%)的调谐范围。在16ghz频率下，测量到的相位噪声在1mhz偏移时为-118.6 dBc/Hz，压控振荡器的功耗约为3.3 mA。
{"title":"A 0.18-μm CMOS 16-GHz varactorless LC-VCO with 1.2-GHz tuning range","authors":"C. Chang, Ching-Yuan Yang","doi":"10.1109/ASSCC.2007.4425743","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425743","url":null,"abstract":"The paper describes a 16-GHz monolithic varactorless LC-tank VCO implemented in a 0.18-mum CMOS technology. Unlike the traditional tuning method by a varactor, in this work a tunable inductor, which is introduced by a transformer based on tuning currents from the active components controlled by the input voltage, is employed in the VCO. Without a varactor in the LC tank, the oscillator can easily arrive at the requirement for high-frequency operation. The VCO using a symmetry transformer provides the tuning range of 15.44 to 16.64 GHz (7.5%) at 1.8 V supply. With operating at 16-GHz frequency, the measured phase noise is -118.6 dBc/Hz at 1-MHz offset, and the VCO dissipates around 3.3 mA.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129580906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425782
S. Furuichi, Y. Ueda, A. Wadatt, E. Takahashi, M. Murakawa, T. Susa, T. Higuchi
A new post-fabrication clock-timing adjustment method using a genetic algorithm (GA) has been proposed to improve the performance of sub-100 nm LSIs. In the new method, we propose a new technique for implementing post-fabrication clock-timing adjustment, which is extremely effective in enhancing chip performance at almost negligible costs. The new technique comprises insertion-point prediction that specifies flip-flops to be adjusted in advance, and an improved GA technique for high-speed adjustment. We apply these techniques to an image-processing DCT (Discrete Cosine Transform) circuit that has low-power consumption characteristics, and developed a chip with 1,031 programmable delay circuits. The test chip circuit exhibits a more than 15% reduction in power consumption with an area increase of only 5%. The developed method is expected to realize adjustments within a few seconds.
{"title":"A low-power DCT chip utilizing post-fabrication clock-timing adjustment with area reductions and adjustment speed enhancements","authors":"S. Furuichi, Y. Ueda, A. Wadatt, E. Takahashi, M. Murakawa, T. Susa, T. Higuchi","doi":"10.1109/ASSCC.2007.4425782","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425782","url":null,"abstract":"A new post-fabrication clock-timing adjustment method using a genetic algorithm (GA) has been proposed to improve the performance of sub-100 nm LSIs. In the new method, we propose a new technique for implementing post-fabrication clock-timing adjustment, which is extremely effective in enhancing chip performance at almost negligible costs. The new technique comprises insertion-point prediction that specifies flip-flops to be adjusted in advance, and an improved GA technique for high-speed adjustment. We apply these techniques to an image-processing DCT (Discrete Cosine Transform) circuit that has low-power consumption characteristics, and developed a chip with 1,031 programmable delay circuits. The test chip circuit exhibits a more than 15% reduction in power consumption with an area increase of only 5%. The developed method is expected to realize adjustments within a few seconds.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129706011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425740
Dong-Hun Shin, Jaejin Park, C. Yue
This paper presents the design of a 3-5-GHz CMOS ultra-wideband (UWB) Iow-noise amplifier (LNA) utilizing an on-chip transformer to achieve low-power operation and to realize a compact input matching network. Detailed analyses of the input match, voltage gain, and noise figure of the LNA are provided. Implemented in 0.13-mum CMOS, the LNA achieves a maximum power gain of 16.2 dB, an input return loss of greater than 11.0 dB, and a minimum noise figure of 2.8 dB for the 3-5-GHz UWB while consuming only 6.7 mW from a 1.2-V supply. The active area of the fabricated CMOS UWB LNA is 0.32 mm2.
{"title":"A low-power, 3-5-GHz CMOS UWB LNA using transformer matching technique","authors":"Dong-Hun Shin, Jaejin Park, C. Yue","doi":"10.1109/ASSCC.2007.4425740","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425740","url":null,"abstract":"This paper presents the design of a 3-5-GHz CMOS ultra-wideband (UWB) Iow-noise amplifier (LNA) utilizing an on-chip transformer to achieve low-power operation and to realize a compact input matching network. Detailed analyses of the input match, voltage gain, and noise figure of the LNA are provided. Implemented in 0.13-mum CMOS, the LNA achieves a maximum power gain of 16.2 dB, an input return loss of greater than 11.0 dB, and a minimum noise figure of 2.8 dB for the 3-5-GHz UWB while consuming only 6.7 mW from a 1.2-V supply. The active area of the fabricated CMOS UWB LNA is 0.32 mm2.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132600011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425682
Joo-Young Kim, H. Yoo
In this paper, we present a bitwise competition logic (BCL) for the high performance and area efficient digital comparator. It compares two integer numbers using the location of the first 1 from the MSB, without arithmetic computations. The detail circuits to implement BCL, pre-encoder and selection logics are explained. The implemented BCL comparator shows 16%, 38% and 30% improved result in propagation delay, transistor count, and physical area compared to the other types of comparators. Measurement waveforms of fabricated BCL comparator verify its feasibility and functionality.
{"title":"Bitwise Competition Logic for compact digital comparator","authors":"Joo-Young Kim, H. Yoo","doi":"10.1109/ASSCC.2007.4425682","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425682","url":null,"abstract":"In this paper, we present a bitwise competition logic (BCL) for the high performance and area efficient digital comparator. It compares two integer numbers using the location of the first 1 from the MSB, without arithmetic computations. The detail circuits to implement BCL, pre-encoder and selection logics are explained. The implemented BCL comparator shows 16%, 38% and 30% improved result in propagation delay, transistor count, and physical area compared to the other types of comparators. Measurement waveforms of fabricated BCL comparator verify its feasibility and functionality.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124699348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425759
S. Mochizuki, T. Shibayama, M. Hase, F. Izuhara, Kazushi Akie, Masaki Nobori, Ren Imaoka, H. Ueda, Kazuyuki Ishikawa, H. Watanabe
We have developed an H.264/MPEG-4 video codec IP for mobile applications such as digital still cameras (DSCs) and digital video cameras (DVCs) The codec is capable of encoding/decoding HD sized moving pictures (1280 pixels by 720 lines at 30 fps) in real-time at an operating frequency of 144 MHz, and SD sized at 54 MHz. The original algorithms employed in the codec realize low power of 64 mW for encoding HD with high picture quality equivalent to JM reference encoder.
{"title":"A low power and high picture quality H.264/MPEG-4 video codec IP for HD mobile applications","authors":"S. Mochizuki, T. Shibayama, M. Hase, F. Izuhara, Kazushi Akie, Masaki Nobori, Ren Imaoka, H. Ueda, Kazuyuki Ishikawa, H. Watanabe","doi":"10.1109/ASSCC.2007.4425759","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425759","url":null,"abstract":"We have developed an H.264/MPEG-4 video codec IP for mobile applications such as digital still cameras (DSCs) and digital video cameras (DVCs) The codec is capable of encoding/decoding HD sized moving pictures (1280 pixels by 720 lines at 30 fps) in real-time at an operating frequency of 144 MHz, and SD sized at 54 MHz. The original algorithms employed in the codec realize low power of 64 mW for encoding HD with high picture quality equivalent to JM reference encoder.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122398999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425767
Myounggon Kang, Ki-Whan Song, Hoeju Chung, Jinyoung Kim, Yeong-Taek Lee, Changhyun Kim
A modified SCR (silicon controlled rectifier) is proposed as an ESD protection for high speed signaling systems. With low voltage triggering (LVT) characteristics and good turn-on uniformity, the proposed SCR scheme accomplishes both goals, high discharging capability and Cin (input capacitance) reduction. The fabricated chips with the new ESD scheme passed the severe package level EOS test conditions such as HBM-5 kV and MM-500 V stress. The input capacitance, Cin, was measured to be 1.5 pF which satisfies the DDR3-1066 specification with enough margin. We have observed in SPICE simulation that the data eye can be enlarged to 277 ps (55.3% of UI) in DDR3 interface at 2 Gbps operation due to the Cin reduction effect.
{"title":"SCR-based ESD protection for high bandwidth DRAMs","authors":"Myounggon Kang, Ki-Whan Song, Hoeju Chung, Jinyoung Kim, Yeong-Taek Lee, Changhyun Kim","doi":"10.1109/ASSCC.2007.4425767","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425767","url":null,"abstract":"A modified SCR (silicon controlled rectifier) is proposed as an ESD protection for high speed signaling systems. With low voltage triggering (LVT) characteristics and good turn-on uniformity, the proposed SCR scheme accomplishes both goals, high discharging capability and Cin (input capacitance) reduction. The fabricated chips with the new ESD scheme passed the severe package level EOS test conditions such as HBM-5 kV and MM-500 V stress. The input capacitance, Cin, was measured to be 1.5 pF which satisfies the DDR3-1066 specification with enough margin. We have observed in SPICE simulation that the data eye can be enlarged to 277 ps (55.3% of UI) in DDR3 interface at 2 Gbps operation due to the Cin reduction effect.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127793009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425719
Sheng-Chuan Liang, Ding-Jyun Huang, Chen-Kang Ho, Hao-Chiao Hong
This paper demonstrates a 10 GS/s, 4-bit, flash analog-to-digital converter (ADC) and current-steering digital-to-analog converter (DAC) pair for the design of advanced serial-link transceivers. Current mode logic (CML) gates are used to alleviate the severe power bouncing. The active feedback amplifiers, CML, and wave-pipelining technique help achieve the ultimate 10 GHz sampling rate. A design-for-testability circuit using the digital loop-back scheme is added to address the difficulty of at-speed measurements. The experimental results show that the cascaded ADC and DAC pair achieves a 27.3 dBc spurious-free dynamic range and a 25.0 dB signal-to-noise ratio with the 1.11 GHz, -1 dBm stimulus. It corresponds to an ENOB of 3.86 bits. The test chip totally consumes 420 mW from a 1.2 V supply. The areas of the ADC and DAC are 0.1575 mm2 and 0.0636 mm2, respectively in 0.13 mum CMOS technology.
{"title":"10 GSamples/s, 4-bit, 1.2V, design-for-testability ADC and DAC in 0.13µm CMOS technology","authors":"Sheng-Chuan Liang, Ding-Jyun Huang, Chen-Kang Ho, Hao-Chiao Hong","doi":"10.1109/ASSCC.2007.4425719","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425719","url":null,"abstract":"This paper demonstrates a 10 GS/s, 4-bit, flash analog-to-digital converter (ADC) and current-steering digital-to-analog converter (DAC) pair for the design of advanced serial-link transceivers. Current mode logic (CML) gates are used to alleviate the severe power bouncing. The active feedback amplifiers, CML, and wave-pipelining technique help achieve the ultimate 10 GHz sampling rate. A design-for-testability circuit using the digital loop-back scheme is added to address the difficulty of at-speed measurements. The experimental results show that the cascaded ADC and DAC pair achieves a 27.3 dBc spurious-free dynamic range and a 25.0 dB signal-to-noise ratio with the 1.11 GHz, -1 dBm stimulus. It corresponds to an ENOB of 3.86 bits. The test chip totally consumes 420 mW from a 1.2 V supply. The areas of the ADC and DAC are 0.1575 mm2 and 0.0636 mm2, respectively in 0.13 mum CMOS technology.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114689042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425778
Xiao Wang, Bowei Jiang, Wenyi Che, N. Yan, Hao Min
This paper presents a high performance AC-DC charge pump for RFID tags, with the self-bias feedback and threshold compensation technique. Compared with conventional charge pump, the influence of threshold is greatly reduced and output DC voltage and power conversion efficiency is greatly improved. This proposed charge pump with 5 stages is implemented in SMIC 0.18 mum standard CMOS process. Simulation and measurement results show that for sinusoidal wave (f = 3.56 MHz) with magnitude voltages of 0.5 V, 0.6 V, and 0.7 V the output DC voltages of 1.1 V, 1.5 V and 1.9 V can be generated respectively with 120 KOmega equivalent load. Measurement results show the power conversion efficiency (PCE) reaches as high as 36%. And the sensitivity performance of RFID tags is improved to as low as -14.5 dBm.
{"title":"A high efficiency AC-DC charge pump using feedback compensation technique","authors":"Xiao Wang, Bowei Jiang, Wenyi Che, N. Yan, Hao Min","doi":"10.1109/ASSCC.2007.4425778","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425778","url":null,"abstract":"This paper presents a high performance AC-DC charge pump for RFID tags, with the self-bias feedback and threshold compensation technique. Compared with conventional charge pump, the influence of threshold is greatly reduced and output DC voltage and power conversion efficiency is greatly improved. This proposed charge pump with 5 stages is implemented in SMIC 0.18 mum standard CMOS process. Simulation and measurement results show that for sinusoidal wave (f = 3.56 MHz) with magnitude voltages of 0.5 V, 0.6 V, and 0.7 V the output DC voltages of 1.1 V, 1.5 V and 1.9 V can be generated respectively with 120 KOmega equivalent load. Measurement results show the power conversion efficiency (PCE) reaches as high as 36%. And the sensitivity performance of RFID tags is improved to as low as -14.5 dBm.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129492820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425789
Saeng-Hwan Kim, W. Lee, Jung-Ho Kim, Seong-Seop Lee, Sun-Young Hwang, Chang-Il Kim, T. Kwon, Bong-Seok Han, Sung-Kwon Cho, Daehoon Kim, Jae-Keun Hong, Minyeong Lee, Sung-Wook Yin, Hyeongon Kim, Jin-Hong Ahn, Yongtak Kim, Y. Koh, J. Kih
512 Mb Mobile SDRAM with on-chip error-correction code (ECC), which supports either single or double data rate and operates on a 1.8 V power supply, is developed. The ECC circuit is optimized with respect to the increase in the chip area and the access-time penalty. The ratio of ECC area increase compared with the conventional mobile DRAM is 15%, and the fast comparing circuits of built-in Hamming code technique check 12 cell data simultaneously and satisfy the specification of 400Mbps DDR SDRAM. The self refresh period at standby state shows about 6 times increase reducing the self refresh current to be less than 100uA at 85degC. The newly adopted DCCS in the ECC, which is resistant from the clustered failures, and the concurrent row redundancy produce a synergistic fault-tolerance effect. The reliability could be 106 times higher by the ECC than that of the conventional DRAM.
{"title":"A low power and highly reliable 400Mbps mobile DDR SDRAM with on-chip distributed ECC","authors":"Saeng-Hwan Kim, W. Lee, Jung-Ho Kim, Seong-Seop Lee, Sun-Young Hwang, Chang-Il Kim, T. Kwon, Bong-Seok Han, Sung-Kwon Cho, Daehoon Kim, Jae-Keun Hong, Minyeong Lee, Sung-Wook Yin, Hyeongon Kim, Jin-Hong Ahn, Yongtak Kim, Y. Koh, J. Kih","doi":"10.1109/ASSCC.2007.4425789","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425789","url":null,"abstract":"512 Mb Mobile SDRAM with on-chip error-correction code (ECC), which supports either single or double data rate and operates on a 1.8 V power supply, is developed. The ECC circuit is optimized with respect to the increase in the chip area and the access-time penalty. The ratio of ECC area increase compared with the conventional mobile DRAM is 15%, and the fast comparing circuits of built-in Hamming code technique check 12 cell data simultaneously and satisfy the specification of 400Mbps DDR SDRAM. The self refresh period at standby state shows about 6 times increase reducing the self refresh current to be less than 100uA at 85degC. The newly adopted DCCS in the ECC, which is resistant from the clustered failures, and the concurrent row redundancy produce a synergistic fault-tolerance effect. The reliability could be 106 times higher by the ECC than that of the conventional DRAM.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128725935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425762
H. Ishihara, M. Miyama, Y. Matsuda, Y. Murachi, Y. Fukuyama, R. Yamamoto, J. Miyakoshi, H. Kawaguchi, M. Yoshimoto
This paper describes an optical-flow processor core for real-time video recognition. The processor is based on the Pyramidal Lucas and Kanade algorithm. It has small chip area, a high pixel rate, and high accuracy compared to conventional optical-flow processors. Introduction of search range limitation and the Carman filter to the original algorithm improves the optical-flow accuracy and reduces the processor hardware cost. Furthermore, window interleaving and window overlap methods can reduce the necessary clock frequency of the processor by 70%. The proposed processor can handle a VGA30-fps image sequence with 332 MHz clock frequency. The core size and power consumption in 90-nm process technology are estimated respectively as 3.50 times 3.00 mm2 and 600 mW.
{"title":"A VGA 30-fps optical-flow processor core based on Pyramidal Lucas and Kanade algorithm","authors":"H. Ishihara, M. Miyama, Y. Matsuda, Y. Murachi, Y. Fukuyama, R. Yamamoto, J. Miyakoshi, H. Kawaguchi, M. Yoshimoto","doi":"10.1109/ASSCC.2007.4425762","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425762","url":null,"abstract":"This paper describes an optical-flow processor core for real-time video recognition. The processor is based on the Pyramidal Lucas and Kanade algorithm. It has small chip area, a high pixel rate, and high accuracy compared to conventional optical-flow processors. Introduction of search range limitation and the Carman filter to the original algorithm improves the optical-flow accuracy and reduces the processor hardware cost. Furthermore, window interleaving and window overlap methods can reduce the necessary clock frequency of the processor by 70%. The proposed processor can handle a VGA30-fps image sequence with 332 MHz clock frequency. The core size and power consumption in 90-nm process technology are estimated respectively as 3.50 times 3.00 mm2 and 600 mW.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122439816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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