Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966764
J. Emmert, Jason A. Cheatham
In this paper we present a Fault Tolerant (FT) technique for programmable interconnect on Field Programmable Gate Arrays (FPGAs). Our on-line strategy uses incremental reconfiguration capabilities of FPGAs to avoid faults, and the main advantage of our technique is that it does not require a router at the time FT reconfiguration is performed. Our algorithm generates precompiled FT partial configurations that can be downloaded when faults occur. Since the precompiled partial configurations are stored on a net by net basis, the required storage space and the download time is minimal. We have implemented our technique on the ORCA series FPGAs available from Lucent Technologies, and we demonstrate our technique on a FPGA based, on-line Adaptive Computing System (ACS) implemented with the ORCA FPGAs. Our worst case data indicates we can determine an average of seven alternates per signal net and for most circuits up to ten.
{"title":"On-line incremental routing for interconnect fault tolerance in FPGAs minus the router","authors":"J. Emmert, Jason A. Cheatham","doi":"10.1109/DFTVS.2001.966764","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966764","url":null,"abstract":"In this paper we present a Fault Tolerant (FT) technique for programmable interconnect on Field Programmable Gate Arrays (FPGAs). Our on-line strategy uses incremental reconfiguration capabilities of FPGAs to avoid faults, and the main advantage of our technique is that it does not require a router at the time FT reconfiguration is performed. Our algorithm generates precompiled FT partial configurations that can be downloaded when faults occur. Since the precompiled partial configurations are stored on a net by net basis, the required storage space and the download time is minimal. We have implemented our technique on the ORCA series FPGAs available from Lucent Technologies, and we demonstrate our technique on a FPGA based, on-line Adaptive Computing System (ACS) implemented with the ORCA FPGAs. Our worst case data indicates we can determine an average of seven alternates per signal net and for most circuits up to ten.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130303345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966778
R. Velazco, R. Leveugle, O. Calvo
Investigates an approach allowing one to evaluate the consequences of single event upset phenomena for the reliable operation of processors. The method is based on the simulation of bit flips using a modified version of a high-level circuit description. Preliminary results illustrate the potential of this new strategy.
{"title":"Upset-like fault injection in VHDL descriptions: A method and preliminary results","authors":"R. Velazco, R. Leveugle, O. Calvo","doi":"10.1109/DFTVS.2001.966778","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966778","url":null,"abstract":"Investigates an approach allowing one to evaluate the consequences of single event upset phenomena for the reliable operation of processors. The method is based on the simulation of bit flips using a modified version of a high-level circuit description. Preliminary results illustrate the potential of this new strategy.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126377338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/DFTVS.2001.966797
N. Kamiura, M. Tomita, T. Isokawa, N. Matsui
In this paper we propose a fuzzy controller with the capability of compensating the influence of single stuck-at faults in membership functions. To cope with the faults in each antecedent part, the degree in a candidate regarded as a faulty function is exchanged for one of the following: 0, the degree in the next function to the candidate, and the difference between the constant and the degree in the next function to the candidate. To cope with the faults in the consequent part, several fuzzy variables are shifted, and then the fuzzy inference is executed with the membership functions representing shifted variables. Experimental results for a commercial controller show that the influence of any single fault deviating the normal deterministic output of the controller is compensated completely.
{"title":"On variable-shift-based fault compensation of fuzzy controllers","authors":"N. Kamiura, M. Tomita, T. Isokawa, N. Matsui","doi":"10.1109/DFTVS.2001.966797","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966797","url":null,"abstract":"In this paper we propose a fuzzy controller with the capability of compensating the influence of single stuck-at faults in membership functions. To cope with the faults in each antecedent part, the degree in a candidate regarded as a faulty function is exchanged for one of the following: 0, the degree in the next function to the candidate, and the difference between the constant and the degree in the next function to the candidate. To cope with the faults in the consequent part, several fuzzy variables are shifted, and then the fuzzy inference is executed with the membership functions representing shifted variables. Experimental results for a commercial controller show that the influence of any single fault deviating the normal deterministic output of the controller is compensated completely.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"417 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126703075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}