Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966761
Shu-Yi Yu, E. McCluskey
FPGA fault repair schemes remove faulty elements from designs through reconfiguration. In designs with high FPGA utilization, a sufficient number of routable fault-free elements may not be available for permanent fault repair. We present a new permanent fault repair scheme, in which the original design is reconfigured into another fault tolerant design that has smaller area, so the damaged element can be avoided. Three new schemes that fully utilize available fault-free area and provide low impact on availability are presented. Analytical results show that our schemes improve availability compared to a module removal approach. which removes a redundant module when it becomes faulty.
{"title":"Permanent fault repair for FPGAs with limited redundant area","authors":"Shu-Yi Yu, E. McCluskey","doi":"10.1109/DFTVS.2001.966761","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966761","url":null,"abstract":"FPGA fault repair schemes remove faulty elements from designs through reconfiguration. In designs with high FPGA utilization, a sufficient number of routable fault-free elements may not be available for permanent fault repair. We present a new permanent fault repair scheme, in which the original design is reconfigured into another fault tolerant design that has smaller area, so the damaged element can be avoided. Three new schemes that fully utilize available fault-free area and provide low impact on availability are presented. Analytical results show that our schemes improve availability compared to a module removal approach. which removes a redundant module when it becomes faulty.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123764264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966776
R. Leveugle
It has been recognized that analyzing at an early stage of the design the potential faulty behaviors of a circuit becomes a major concern due to the increasing probability of transient faults. It has been proposed to carry out such an analysis using fault injections in a hardware prototype of the circuit under design. This paper reports on a low cost environment using such a flow. A simple FPGA-based development board is used to emulate the circuit and the execution results are analysed on a PC computer. A generic, scalable, approach is proposed to overcome the limitations of such a simple set-up. Such an environment can for example allow a designer to perform efficient and low cost dependability analyses for IP blocks.
{"title":"A low-cost hardware approach to dependability validation of IPs","authors":"R. Leveugle","doi":"10.1109/DFTVS.2001.966776","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966776","url":null,"abstract":"It has been recognized that analyzing at an early stage of the design the potential faulty behaviors of a circuit becomes a major concern due to the increasing probability of transient faults. It has been proposed to carry out such an analysis using fault injections in a hardware prototype of the circuit under design. This paper reports on a low cost environment using such a flow. A simple FPGA-based development board is used to emulate the circuit and the execution results are analysed on a PC computer. A generic, scalable, approach is proposed to overcome the limitations of such a simple set-up. Such an environment can for example allow a designer to perform efficient and low cost dependability analyses for IP blocks.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126654520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966798
N. Kamiura, M. Tomita, T. Isokawa, N. Matsui
In this paper we propose a fuzzy controller with the capability of compensating the influence of single stuck-at-faults in membership functions. To cope with the faults in each antecedent part, the degree in a candidate regarded as a faulty function is exchanged for one of the following: 0, the degree in the next function to the candidate, and the difference between the constant and the degree in the next function to the candidate. To cope with the faults in the consequent part, several fuzzy variables are shifted, and then the fuzzy inference is executed with the membership functions representing shifted variables. Experimental results for a commercial controller show that the influence of any single fault deviating the normal deterministic output of the controller is compensated completely.
{"title":"On variable-shift-based fault compensation of fuzzy controllers","authors":"N. Kamiura, M. Tomita, T. Isokawa, N. Matsui","doi":"10.1109/DFTVS.2001.966798","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966798","url":null,"abstract":"In this paper we propose a fuzzy controller with the capability of compensating the influence of single stuck-at-faults in membership functions. To cope with the faults in each antecedent part, the degree in a candidate regarded as a faulty function is exchanged for one of the following: 0, the degree in the next function to the candidate, and the difference between the constant and the degree in the next function to the candidate. To cope with the faults in the consequent part, several fuzzy variables are shifted, and then the fuzzy inference is executed with the membership functions representing shifted variables. Experimental results for a commercial controller show that the influence of any single fault deviating the normal deterministic output of the controller is compensated completely.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124402122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966752
H. Manhaeve, Stefaan Kerckenaere
Presents a noninvasive, highly reliable, testable and (boundary) scan controllable on-chip CMOS current monitor, suited for the validation of IC and module connections and its application at SOC, board and system level. The monitor provides a solution to the problem of verifying the multiple power and ground connections, required to assure a proper power distribution to today's complex designs. These connections are very difficult to verify as they are connected in parallel and hence a failing connection will only marginally affect the overall connection characteristics but will affect a device's reliability. The application of the monitor described is an alternative and improvement to the currently used optical. X-ray and other inspection techniques. The monitor presented is designed such that it is fully transparent, testable, guarantees a proper detection, irrespective of local and global process parameter variations -avoiding the need for calibrationand can be put in a power down mode. The application of the monitor is based on the detection of a current flowing through the tested connection, thereby exploiting the inherent resistance of the connection. The sensor can easily be merged to different technologies without making major changes, which makes it well suited for intellectual property re-use.
{"title":"An on-chip detection circuit for the verification of IC supply connections","authors":"H. Manhaeve, Stefaan Kerckenaere","doi":"10.1109/DFTVS.2001.966752","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966752","url":null,"abstract":"Presents a noninvasive, highly reliable, testable and (boundary) scan controllable on-chip CMOS current monitor, suited for the validation of IC and module connections and its application at SOC, board and system level. The monitor provides a solution to the problem of verifying the multiple power and ground connections, required to assure a proper power distribution to today's complex designs. These connections are very difficult to verify as they are connected in parallel and hence a failing connection will only marginally affect the overall connection characteristics but will affect a device's reliability. The application of the monitor described is an alternative and improvement to the currently used optical. X-ray and other inspection techniques. The monitor presented is designed such that it is fully transparent, testable, guarantees a proper detection, irrespective of local and global process parameter variations -avoiding the need for calibrationand can be put in a power down mode. The application of the monitor is based on the detection of a current flowing through the tested connection, thereby exploiting the inherent resistance of the connection. The sensor can easily be merged to different technologies without making major changes, which makes it well suited for intellectual property re-use.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"46 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114130596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966786
A. Walker
A new mixed-signal built-in self-test approach that is based upon the step response of a reconfigurable (or multifunction) analog block is presented in this paper. The technique requires the overlapping step response of the Circuit Under Test (CUT) for two circuit configurations. Each configuration can be realized by changing the topology of the CUT or by sampling two CUT nodes with differing step responses. The technique can effectively detect both soft and hard faults and does not require an analog-to-digital converter (ADC) and/or digital-to-analog converter ( DAC). It also does not require any precision voltage sources or comparators. The approach does not require any additional analog circuits to realize the test signal generator and a two input analog multiplexer for CUT test node sampling. The paper concludes with the application of the proposed approach to a circuit found in the work of Epstein et al. (see IEEE Trans. on CAD, vol. 12, no. 1, p. 102-113, 1993) and two ITC'97 analog benchmark circuits.
本文提出了一种新的基于可重构(或多功能)模拟块阶跃响应的混合信号内置自检方法。该技术要求两种电路配置的被测电路(CUT)具有重叠阶跃响应。每种配置都可以通过改变CUT的拓扑结构或对具有不同阶跃响应的两个CUT节点进行采样来实现。该技术可以有效地检测软故障和硬故障，并且不需要模数转换器(ADC)和/或数模转换器(DAC)。它也不需要任何精密电压源或比较器。该方法不需要任何额外的模拟电路来实现测试信号发生器和用于CUT测试节点采样的双输入模拟多路复用器。本文最后将提出的方法应用于Epstein等人的工作中发现的电路。关于CAD，第12卷，第12期。1, p. 102-113, 1993)和两个ITC'97模拟基准电路。
{"title":"A step response based mixed-signal BIST approach","authors":"A. Walker","doi":"10.1109/DFTVS.2001.966786","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966786","url":null,"abstract":"A new mixed-signal built-in self-test approach that is based upon the step response of a reconfigurable (or multifunction) analog block is presented in this paper. The technique requires the overlapping step response of the Circuit Under Test (CUT) for two circuit configurations. Each configuration can be realized by changing the topology of the CUT or by sampling two CUT nodes with differing step responses. The technique can effectively detect both soft and hard faults and does not require an analog-to-digital converter (ADC) and/or digital-to-analog converter ( DAC). It also does not require any precision voltage sources or comparators. The approach does not require any additional analog circuits to realize the test signal generator and a two input analog multiplexer for CUT test node sampling. The paper concludes with the application of the proposed approach to a circuit found in the work of Epstein et al. (see IEEE Trans. on CAD, vol. 12, no. 1, p. 102-113, 1993) and two ITC'97 analog benchmark circuits.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"114 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124438476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966765
Xiao-Tao Chen, Wei-Kang Huang, N. Park, F. Meyer, F. Lombardi
This paper presents new approaches for the constant (C)-testability of orthogonal (two-dimensional) arrays of combinational cells. A novel testability condition referred to as CO-testability is introduced: a testing approach for CO-testability is fully characterized based on adding states to the table of a cell. A second approach is also proposed. this approach is based on adding a variable number of additional states to a cell with a known table. This approach requires at most (m+k+/spl alpha/)(n+k+/spl alpha/)( m/k+1)(n/k+1) tests, where m and n are the number of states in the two dimensions of signal flow, /spl alpha/=1(0) if (partial) fail observability is applicable to the state table and k is the variable number of additional states per direction (2/spl les/k/spl les/m.n). As an example, the proposed approaches have been applied to a two-dimensional array for maximum/minimum comparison.
{"title":"Novel approaches for fault detection in two-dimensional combinational arrays","authors":"Xiao-Tao Chen, Wei-Kang Huang, N. Park, F. Meyer, F. Lombardi","doi":"10.1109/DFTVS.2001.966765","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966765","url":null,"abstract":"This paper presents new approaches for the constant (C)-testability of orthogonal (two-dimensional) arrays of combinational cells. A novel testability condition referred to as CO-testability is introduced: a testing approach for CO-testability is fully characterized based on adding states to the table of a cell. A second approach is also proposed. this approach is based on adding a variable number of additional states to a cell with a known table. This approach requires at most (m+k+/spl alpha/)(n+k+/spl alpha/)( m/k+1)(n/k+1) tests, where m and n are the number of states in the two dimensions of signal flow, /spl alpha/=1(0) if (partial) fail observability is applicable to the state table and k is the variable number of additional states per direction (2/spl les/k/spl les/m.n). As an example, the proposed approaches have been applied to a two-dimensional array for maximum/minimum comparison.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124938149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966780
P. Lee, Alfred Chen, Dilip Mathew
IDDQ test has been widely used in the industry as a DPM (Defects Per Million) improvement tool for test coverage enhancement. It could detect random defects not caught by traditional "stuck-at-fault" functional testing. While effectiveness of traditional IDDQ test is severely affected by the large background current of deep submicron devices, several approaches have been raised on IDDQ-based methodologies to improve its fault detection sensitivity. This paper presents a new methodology based on one of the field approaches, while taking additional results of a specific test sub-circuit that monitored device speed performance into consideration. Dynamic variation due to process distribution is properly reflected via the test sub-circuit, which then leads to consistent fault detection criteria among all IDDQ measurement vectors.
{"title":"A speed-dependent approach for delta IDDQ implementation","authors":"P. Lee, Alfred Chen, Dilip Mathew","doi":"10.1109/DFTVS.2001.966780","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966780","url":null,"abstract":"IDDQ test has been widely used in the industry as a DPM (Defects Per Million) improvement tool for test coverage enhancement. It could detect random defects not caught by traditional \"stuck-at-fault\" functional testing. While effectiveness of traditional IDDQ test is severely affected by the large background current of deep submicron devices, several approaches have been raised on IDDQ-based methodologies to improve its fault detection sensitivity. This paper presents a new methodology based on one of the field approaches, while taking additional results of a specific test sub-circuit that monitored device speed performance into consideration. Dynamic variation due to process distribution is properly reflected via the test sub-circuit, which then leads to consistent fault detection criteria among all IDDQ measurement vectors.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"265 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123288394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966773
Jayabrata Ghosh-Dastidar, N. Touba
Given an FPGA that has failed to meet its timing specification, techniques are proposed to efficiently diagnose the cause of the faulty behavior. An initial list of suspect configuration logic blocks (CLBs) and interconnects is generated using six-valued fault-free simulation and critical path tracing. The initial list of suspects is then reduced by exploiting the reconfigurability of an FPGA. Experimental results indicate a dramatic reduction in the size of the suspect list.
{"title":"Improving diagnostic resolution of delay faults in FPGAs by exploiting reconfigurability","authors":"Jayabrata Ghosh-Dastidar, N. Touba","doi":"10.1109/DFTVS.2001.966773","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966773","url":null,"abstract":"Given an FPGA that has failed to meet its timing specification, techniques are proposed to efficiently diagnose the cause of the faulty behavior. An initial list of suspect configuration logic blocks (CLBs) and interconnects is generated using six-valued fault-free simulation and critical path tracing. The initial list of suspects is then reduced by exploiting the reconfigurability of an FPGA. Experimental results indicate a dramatic reduction in the size of the suspect list.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130198124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966790
P. Nagaraj, Shambhu Upadhaya, K. Zarrineh, R. Adams
Semiconductor memory failures depend on the behavior of its components. This paper deals with testing of defects occurring in the memory cells of a multi-port memory. We also consider the resistive shorts between word/bit lines of same and different ports of the memory. The memory is modeled at the transistor level and analyzed for electrical defects by applying a set of patterns. Not only have existing models been taken into account in our simulation but also a new fault model for the multi-port memory is introduced. The boundaries of failure for the proposed defects are identified.
{"title":"Defect analysis and a new fault model for multi-port SRAMs","authors":"P. Nagaraj, Shambhu Upadhaya, K. Zarrineh, R. Adams","doi":"10.1109/DFTVS.2001.966790","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966790","url":null,"abstract":"Semiconductor memory failures depend on the behavior of its components. This paper deals with testing of defects occurring in the memory cells of a multi-port memory. We also consider the resistive shorts between word/bit lines of same and different ports of the memory. The memory is modeled at the transistor level and analyzed for electrical defects by applying a set of patterns. Not only have existing models been taken into account in our simulation but also a new fault model for the multi-port memory is introduced. The boundaries of failure for the proposed defects are identified.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129990758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966789
C. Metra, Stefano Di Francescantonio, B. Riccò, T. M. Mak
Starting from the analysis of real process data and considering, as a reference, an Intel microprocessor we evaluate the fault models that better describe the manufacturing defects that are most likely to affect signals of the clock distribution network. The probability of these faults has been estimated by means of Inductive Fault Analysis (IFA) and has been found to be, for the majority of cases, comparable if not one order of magnitude higher than that of other most likely microprocessor faults. The effects of the most likely clock faults has then been analyzed by means of electrical level simulations. Differently from what is generally implicitly assumed, we have found that only a small percentage of these faults results in a catastrophic failure of the microprocessor, thus being possibly easily detectable during manufacturing test, while the majority results in a local failure, which cannot be detected during manufacturing test, although compromising the microprocessor correct operation and causing an unacceptable decrease in its reliability.
{"title":"Evaluation of clock distribution networks' most likely faults and produced effects","authors":"C. Metra, Stefano Di Francescantonio, B. Riccò, T. M. Mak","doi":"10.1109/DFTVS.2001.966789","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966789","url":null,"abstract":"Starting from the analysis of real process data and considering, as a reference, an Intel microprocessor we evaluate the fault models that better describe the manufacturing defects that are most likely to affect signals of the clock distribution network. The probability of these faults has been estimated by means of Inductive Fault Analysis (IFA) and has been found to be, for the majority of cases, comparable if not one order of magnitude higher than that of other most likely microprocessor faults. The effects of the most likely clock faults has then been analyzed by means of electrical level simulations. Differently from what is generally implicitly assumed, we have found that only a small percentage of these faults results in a catastrophic failure of the microprocessor, thus being possibly easily detectable during manufacturing test, while the majority results in a local failure, which cannot be detected during manufacturing test, although compromising the microprocessor correct operation and causing an unacceptable decrease in its reliability.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122592902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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