Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966796
R. Karri, Kaijie Wu, P. Mishra, Yongkook Kim
Fault-based side channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy based Concurrent Error Detection (CED) architectures can be used to thwart such attacks, they entail significant overhead (either area or performance). In this paper we investigate systematic approaches to low-cost, low-latency CED for Rijndael symmetric encryption algorithm. These approaches exploit the inverse relationship that exists between Rijndael encryption and decryption at various levels and develop CED architectures that explore the trade-off between area overhead, performance penalty and error detection latency. The proposed techniques have been validated on FPGA implementations.
{"title":"Fault-based side-channel cryptanalysis tolerant Rijndael symmetric block cipher architecture","authors":"R. Karri, Kaijie Wu, P. Mishra, Yongkook Kim","doi":"10.1109/DFTVS.2001.966796","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966796","url":null,"abstract":"Fault-based side channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy based Concurrent Error Detection (CED) architectures can be used to thwart such attacks, they entail significant overhead (either area or performance). In this paper we investigate systematic approaches to low-cost, low-latency CED for Rijndael symmetric encryption algorithm. These approaches exploit the inverse relationship that exists between Rijndael encryption and decryption at various levels and develop CED architectures that explore the trade-off between area overhead, performance penalty and error detection latency. The proposed techniques have been validated on FPGA implementations.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128555883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966754
Shugang Wei, K. Shimizu
An error detection method for arithmetic circuits is proposed, by using a residue checker which consists of a number of residue arithmetic circuits designed based on radix-2 signed-digit (SD) number arithmetic. Fast modulo m(m=2/sup p//spl plusmn/1) multipliers and binary-to-residue number converters are constructed with a binary tree structure of modulo m SD adders. The modulo m addition is implemented by using a p-digit SD adder, so that the modulo m addition time is independent of the word length of operands. Therefore, the modulo m multiplication is performed in a time proportional to log/sub 2/p and an n-bit binary number is converted into a p-digit SD residue number in a time proportional to log/sub 2/(n/p). The presented residue arithmetic circuits can be applied to error detection for a large product-sum circuit.
{"title":"Error detection of arithmetic circuits using a residue checker with signed-digit number system","authors":"Shugang Wei, K. Shimizu","doi":"10.1109/DFTVS.2001.966754","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966754","url":null,"abstract":"An error detection method for arithmetic circuits is proposed, by using a residue checker which consists of a number of residue arithmetic circuits designed based on radix-2 signed-digit (SD) number arithmetic. Fast modulo m(m=2/sup p//spl plusmn/1) multipliers and binary-to-residue number converters are constructed with a binary tree structure of modulo m SD adders. The modulo m addition is implemented by using a p-digit SD adder, so that the modulo m addition time is independent of the word length of operands. Therefore, the modulo m multiplication is performed in a time proportional to log/sub 2/p and an n-bit binary number is converted into a p-digit SD residue number in a time proportional to log/sub 2/(n/p). The presented residue arithmetic circuits can be applied to error detection for a large product-sum circuit.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"200 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115473983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966791
M. Blyzniuk, I. Kazymyra
The development of special software tool named FIESTA (Faults Identification and Estimation of Test Ability) for the defect/fault analysis in the complex gates from industrial cell library is considered. This software tool is destined for the test developers and IC designers and is aimed at: a) probabilistic-based analysis of CMOS physical defects in VLSI circuits: b) facilitation of the work on development of hierarchical probabilistic automatic generation of test patterns; c) improvement of the layout in order to decrease the influence of spot defects on IC manufacturability. We consider the principle concepts of the FIESTA development. They are based on the developed approaches to 1) the identification and estimation of the probability of actual faulty functions resulting from shorts and opens caused by spot defects in the conductive layers of IC layout, and to 2) the evaluation of the effectiveness/usefulness of the test vector components in faults detection.
针对工业单元库中复杂栅极的缺陷/故障分析，考虑开发专用软件FIESTA (fault Identification and Estimation of Test Ability)。该软件工具面向测试开发人员和集成电路设计人员，旨在:a)基于概率的VLSI电路中CMOS物理缺陷分析;b)促进分层概率自动生成测试模式的开发工作;c)改进布局，以减少斑点缺陷对集成电路可制造性的影响。我们考虑FIESTA开发的主要概念。它们基于以下开发的方法:1)识别和估计由IC布局的导电层中的斑点缺陷引起的短路和打开导致的实际故障功能的概率，以及2)评估测试矢量组件在故障检测中的有效性/有用性。
{"title":"Development of the special software tools for the defect/fault analysis in the complex gates from standard cell library","authors":"M. Blyzniuk, I. Kazymyra","doi":"10.1109/DFTVS.2001.966791","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966791","url":null,"abstract":"The development of special software tool named FIESTA (Faults Identification and Estimation of Test Ability) for the defect/fault analysis in the complex gates from industrial cell library is considered. This software tool is destined for the test developers and IC designers and is aimed at: a) probabilistic-based analysis of CMOS physical defects in VLSI circuits: b) facilitation of the work on development of hierarchical probabilistic automatic generation of test patterns; c) improvement of the layout in order to decrease the influence of spot defects on IC manufacturability. We consider the principle concepts of the FIESTA development. They are based on the developed approaches to 1) the identification and estimation of the probability of actual faulty functions resulting from shorts and opens caused by spot defects in the conductive layers of IC layout, and to 2) the evaluation of the effectiveness/usefulness of the test vector components in faults detection.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126592034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966794
M. Ottavi, G. Cardarilli, D. Cellitti, S. Pontarelli, M. Re, A. Salsano
This paper describes the design of a totally self-checking signature analysis checker to be used to implement self-checking finite state machines. The application of the signature analysis method is studied taking into account trade off criteria concerning area and timing constraints requested in specific applications. In this paper, we propose a novel VHDL realization of this methodology suitable for the implementation of the SSMM for satellite applications. Finally, we present a general criterion to evaluate the optimal solution in terms of area overhead between the proposed method and a typical duplication and compare strategy.
{"title":"Design of a totally self checking signature analysis checker for finite state machines","authors":"M. Ottavi, G. Cardarilli, D. Cellitti, S. Pontarelli, M. Re, A. Salsano","doi":"10.1109/DFTVS.2001.966794","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966794","url":null,"abstract":"This paper describes the design of a totally self-checking signature analysis checker to be used to implement self-checking finite state machines. The application of the signature analysis method is studied taking into account trade off criteria concerning area and timing constraints requested in specific applications. In this paper, we propose a novel VHDL realization of this methodology suitable for the implementation of the SSMM for satellite applications. Finally, we present a general criterion to evaluate the optimal solution in terms of area overhead between the proposed method and a typical duplication and compare strategy.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"1770 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129538141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966766
C. Bolchini
The proposed methodology aims at providing concurrent hardware fault detection properties in data paths for VLIW processor architectures. The approach, carried out on the application software consists in the introduction of additional instructions for controlling the correctness of the computation with respect to failures in one of the data path functional units. The paper presents the methodology and its application to a set of media benchmarks.
{"title":"A software methodology for detecting hardware faults in VLIW data paths","authors":"C. Bolchini","doi":"10.1109/DFTVS.2001.966766","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966766","url":null,"abstract":"The proposed methodology aims at providing concurrent hardware fault detection properties in data paths for VLIW processor architectures. The approach, carried out on the application software consists in the introduction of additional instructions for controlling the correctness of the computation with respect to failures in one of the data path functional units. The paper presents the methodology and its application to a set of media benchmarks.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116742700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966771
Kaijie Wu, R. Karri
Describes a concurrent error detection (CED) technique that uses idle cycles in a data path to do the re-computation and demonstrate its benefits and drawbacks using RC6 encryption as a case study. The idle cycle based CED has low area overhead and performance penalty while maintaining strong CED capability.
{"title":"Idle cycles based concurrent error detection of RC6 encryption, [FPGAs]","authors":"Kaijie Wu, R. Karri","doi":"10.1109/DFTVS.2001.966771","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966771","url":null,"abstract":"Describes a concurrent error detection (CED) technique that uses idle cycles in a data path to do the re-computation and demonstrate its benefits and drawbacks using RC6 encryption as a case study. The idle cycle based CED has low area overhead and performance penalty while maintaining strong CED capability.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131847430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966792
W. Pleskacz, D. Kasprowicz, Tomasz Oleszczak, W. Kuzmicz
This paper extends the CMOS standard cells characterization methodology for defect based testing. The proposed methodology allows to find the types of faults which may occur in a real IC, to determine their probabilities, and to find the input test vectors which detect these faults. For shorts at the inputs two types of cell simulation conditions - "Wired-AND" and "Wired-OR" are used. Examples of industrial standard cells characterization indicate that a single logic fault probability table is not sufficient. Separate tables for " Wired-AND " and " Wired-OR" conditions at the inputs are needed for full characterization and hierarchical test generation.
{"title":"CMOS standard cells characterization for defect based testing","authors":"W. Pleskacz, D. Kasprowicz, Tomasz Oleszczak, W. Kuzmicz","doi":"10.1109/DFTVS.2001.966792","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966792","url":null,"abstract":"This paper extends the CMOS standard cells characterization methodology for defect based testing. The proposed methodology allows to find the types of faults which may occur in a real IC, to determine their probabilities, and to find the input test vectors which detect these faults. For shorts at the inputs two types of cell simulation conditions - \"Wired-AND\" and \"Wired-OR\" are used. Examples of industrial standard cells characterization indicate that a single logic fault probability table is not sufficient. Separate tables for \" Wired-AND \" and \" Wired-OR\" conditions at the inputs are needed for full characterization and hierarchical test generation.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130588161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966753
P. Lala, A. Walker
A technique for designing carry-free adders with on-line error checking capability is presented. The adders use signed binary digits (SBDs) internally. An adder consists of sign-magnitude binary to SBD converters, an intermediate adder block that generates partial sum and carry digits, a second adder block that produces a sum digit computed from a partial sum and a partial carry digit, and an error checker that indicates whether the code word corresponding to a final sum digit is error-free or not.
{"title":"On-line error detectable carry-free adder design","authors":"P. Lala, A. Walker","doi":"10.1109/DFTVS.2001.966753","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966753","url":null,"abstract":"A technique for designing carry-free adders with on-line error checking capability is presented. The adders use signed binary digits (SBDs) internally. An adder consists of sign-magnitude binary to SBD converters, an intermediate adder block that generates partial sum and carry digits, a second adder block that produces a sum digit computed from a partial sum and a partial carry digit, and an error checker that indicates whether the code word corresponding to a final sum digit is error-free or not.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125811380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966757
J. H. Jiang, Shih-Chieh Chang, W. Jone
Based on the concept of test pattern broadcasting, we propose a new core-based testing method that gives core users the maximum level of test freedom. Instead of only using the test patterns delivered by core providers. core users are allowed to broadcast test patterns to the cores for parallel scan testing. The fault coverage of core testing can be evaluated by an enhanced version of any, traditional fault simulator. The net-list of each core is scrambled before it is delivered to core users, thus the net-list will not be revealed. The enhanced fault simulator has the capabilities of decoding the scrambled net-list and performing fault simulation for the test patterns provided by core users. Both random test patterns (applied by core users) and golden test patterns (delivered by core providers) jointly achieve high and flexible fault coverage requirements. The proposed method has the advantages of minimizing the number of scan pins, reducing the test application time, and achieving maximum level of test quality control by core users. Simulation results demonstrate the feasibility of this method.
{"title":"Embedded core testing using broadcast test architecture","authors":"J. H. Jiang, Shih-Chieh Chang, W. Jone","doi":"10.1109/DFTVS.2001.966757","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966757","url":null,"abstract":"Based on the concept of test pattern broadcasting, we propose a new core-based testing method that gives core users the maximum level of test freedom. Instead of only using the test patterns delivered by core providers. core users are allowed to broadcast test patterns to the cores for parallel scan testing. The fault coverage of core testing can be evaluated by an enhanced version of any, traditional fault simulator. The net-list of each core is scrambled before it is delivered to core users, thus the net-list will not be revealed. The enhanced fault simulator has the capabilities of decoding the scrambled net-list and performing fault simulation for the test patterns provided by core users. Both random test patterns (applied by core users) and golden test patterns (delivered by core providers) jointly achieve high and flexible fault coverage requirements. The proposed method has the advantages of minimizing the number of scan pins, reducing the test application time, and achieving maximum level of test quality control by core users. Simulation results demonstrate the feasibility of this method.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"924 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123530367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966747
S. Tewksbury
Defect and fault tolerance techniques have played a substantial role in the evolution of silicon digital integrated circuits (ICs). The complex and several mechanisms causing defects in the as-manufactured IC could be represented by simple functional defects ("stuck-at" faults, etc.) and. given these simple functional defects, a variety of testing techniques (including "built-in self-test") could be deployed. Defect tolerance by reconstructing an IC emerged rather early in RAMs and in various array-based architectures. Field-useable testing techniques capable of isolating the site of a defect causing a functional failure farther extended capabilities to allow field-correction or self-correction when failures occurred. Analog ICs present a more sophisticated challenge, though several capabilities for defect tolerance (e.g., laser adjustment of resistances or capacitances) and for fault tolerance (including modular redundancy) emerged. The microelectromechanical systems (MEMS) technology (also called "microsystems technology"-MST) has matured to the point where more extensive applications can be commercially realized. moving beyond the relatively limited number of significant commercial applications now seen. Addition of defect and fault tolerance to the MEMS technology in a manner which abstracts details to achieve simple models will, however, be difficult.
{"title":"Challenges facing practical DFT for MEMS","authors":"S. Tewksbury","doi":"10.1109/DFTVS.2001.966747","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966747","url":null,"abstract":"Defect and fault tolerance techniques have played a substantial role in the evolution of silicon digital integrated circuits (ICs). The complex and several mechanisms causing defects in the as-manufactured IC could be represented by simple functional defects (\"stuck-at\" faults, etc.) and. given these simple functional defects, a variety of testing techniques (including \"built-in self-test\") could be deployed. Defect tolerance by reconstructing an IC emerged rather early in RAMs and in various array-based architectures. Field-useable testing techniques capable of isolating the site of a defect causing a functional failure farther extended capabilities to allow field-correction or self-correction when failures occurred. Analog ICs present a more sophisticated challenge, though several capabilities for defect tolerance (e.g., laser adjustment of resistances or capacitances) and for fault tolerance (including modular redundancy) emerged. The microelectromechanical systems (MEMS) technology (also called \"microsystems technology\"-MST) has matured to the point where more extensive applications can be commercially realized. moving beyond the relatively limited number of significant commercial applications now seen. Addition of defect and fault tolerance to the MEMS technology in a manner which abstracts details to achieve simple models will, however, be difficult.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131648906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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