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Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems最新文献

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Efficient parity prediction in FPGA FPGA中有效的奇偶预测
S. Ko, T. Xia, Jien-Chung Lo
We propose, in this paper, XOR-based decomposition methods to implement parity prediction circuits efficiently in field programmable gate arrays (FPGAs). The first proposed method is an extension of the Shannon's expansion theorem. Such extension enables us to force decomposing the parity prediction circuit into appropriate size sub-circuits. The second proposed method is based on the Reed-Muller canonical form that transforms AND/OR Boolean functions to AND/XOR functions. The XOR relation enables us to find more efficient grouping for the parity prediction function. The MCNC benchmark circuits are used to demonstrate the effectiveness of the proposed techniques.
在本文中,我们提出了基于xor的分解方法来有效地在现场可编程门阵列(fpga)中实现奇偶预测电路。第一个被提出的方法是香农展开定理的扩展。这种扩展使我们能够将奇偶预测电路强制分解成适当大小的子电路。第二种建议的方法是基于Reed-Muller规范形式,将与/或布尔函数转换为与/异或函数。异或关系使我们能够为奇偶预测函数找到更有效的分组。通过MCNC基准电路验证了所提技术的有效性。
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引用次数: 1
Exploiting FPGA-based techniques for fault injection campaigns on VLSI circuits 利用基于fpga的技术在VLSI电路上进行故障注入活动
P. Civera, L. Macchiarulo, M. Rebaudengo, M. Reorda, M. Violante
Proposes an FPGA-based system to speed-up fault injection campaigns for the evaluation of the fault-tolerant capabilities of VLSI circuits. An environment is described, relying on FPGA-based emulation of the circuit. Suitable techniques are described, allowing one to emulate the effects of faults and to observe faulty behavior. The proposed approach allows the combination of the speed of hardware-based techniques, and the flexibility of simulation-based techniques. Experimental results are provided showing that significant speed-up figures with respect to state-of-the-art simulation-based techniques can be achieved.
提出了一种基于fpga的系统来加速故障注入活动,以评估VLSI电路的容错能力。描述了一种基于fpga的电路仿真环境。描述了适当的技术,使人们能够模拟故障的影响并观察故障行为。所提出的方法结合了基于硬件技术的速度和基于仿真技术的灵活性。实验结果表明,相对于最先进的基于仿真的技术,可以实现显著的加速数字。
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引用次数: 60
Design of fault-secure encoders for a class of systematic error correcting codes 一类系统纠错码的故障安全编码器设计
S. Piestrak, A. Dandache, F. Monteiro
In this paper, we consider the open problem of designing fault-secure encoders for various systematic error correcting codes (ECCs). The main idea relies on generating in parallel both the error correcting and detecting check bits. Then, the latter are compared against error detecting check bits which are regenerated from the former. The complexity evaluation of FPGA implementations of encoders with various degrees of parallelism shows that fault-secure versions compare favorably against their unprotected counterparts both with respect to complexity and the maximal frequency of operation.
本文考虑了为各种系统纠错码(ECCs)设计故障安全编码器的开放性问题。其主要思想是同时产生纠错和检测校验位。然后,将后者与由前者生成的错误检测校验位进行比较。对具有不同并行度的编码器的FPGA实现的复杂性评估表明,在复杂性和最大操作频率方面,故障安全版本比未受保护的版本更有利。
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引用次数: 1
Testing Xilinx XC4000 configurable logic blocks with carry logic-modules 测试带有携带逻辑模块的Xilinx XC4000可配置逻辑块
Xiaoling Sun, Jian Xu, P. Trouborst
This paper presents a novel built-in self-test (BIST) scheme for configurable logic blocks (CLBs) of Xilinx XC4000 field programmable gate arrays (FPGAs). The test of the dedicated carry logic module (CLM) within a CLB is included for the first time. A minimum of eight CLB test configurations is given. A centralized BIST architecture supports the single stuck-at fault test of the CLM and the whole CLB. The scheme is also capable of locating any faulty CLBs with the maximum diagnostic resolution, two adjacent CLBs.
针对Xilinx XC4000现场可编程门阵列(fpga)的可配置逻辑块(clb),提出了一种新的内置自检(BIST)方案。本文首次纳入了CLB内专用进位逻辑模块(CLM)的测试。给出了至少8个CLB测试配置。集中式BIST架构支持对CLM和整个CLB进行单卡故障测试。该方案还能够以最大诊断分辨率定位任何故障clb,两个相邻的clb。
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引用次数: 8
Yield-reliability modeling for fault tolerant integrated circuits 容错集成电路的屈服可靠性建模
T. S. Barnett, A. Singh, V. Nelson
An integrated yield-reliability model for defect tolerant integrated circuits is presented that allows one to estimate the yield following both wafer probe and burn-in testing. The model is based on the long observed clustering of defects and the experimentally verified relation between defects causing wafer probe failures and defects causing infant mortality failures. The two-parameter negative binomial distribution is used to describe the distribution of defects over a semiconductor wafer. The clustering parameter /spl alpha/, while known to play a key role in accurately determining wafer probe yields of defect tolerant chips, is shown for the first time. to play a similar role in determining burn-in fall-out. Numerical results indicate that the number of infant mortality failures predicted by the clustering model can differ significantly from calculations that ignore clustering.
提出了一种容限缺陷集成电路的成品率-可靠性综合模型,该模型可以估计晶圆探头和烧蚀测试后的成品率。该模型基于长期观察到的缺陷聚类和实验验证的导致晶圆探针失效的缺陷与导致婴儿死亡失效的缺陷之间的关系。用双参数负二项分布来描述半导体晶圆上缺陷的分布。聚类参数/spl alpha/,虽然已知在准确确定缺陷容限芯片的晶圆探头良率方面起关键作用,但首次显示。在决定倦怠效应方面扮演类似的角色。数值结果表明,聚类模型预测的婴儿死亡率失败数与忽略聚类的计算结果有显著差异。
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引用次数: 6
Analyzing BIST robustness 分析BIST的鲁棒性
J. Sosnowski
Deals with the problem of fault detection and fault handling robustness in BIST schemes. In particular we analyze the susceptibility of signature analyzers to internal faults. Various fault models (black box) within the analyzer circuitry are taken into account. Moreover we check fault impact on software procedures related to BIST and error handling mechanisms using software implemented fault injector.
研究了BIST方案中的故障检测和故障处理鲁棒性问题。我们特别分析了特征分析器对内部故障的敏感性。分析仪电路中的各种故障模型(黑箱)被考虑在内。此外,我们还使用软件实现的故障注入器检查故障对与BIST相关的软件过程和错误处理机制的影响。
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引用次数: 1
Relation between reliability and yield of ICs based on discrete defect distribution model 基于离散缺陷分布模型的集成电路可靠性与良率关系
Tianxu Zhao, Y. Hao, Peijun Ma, Ta-Te Chen
Yield and reliability are two important factors affecting the development of semiconductor manufacturing. It is an important problem, how to express the relation between yield and reliability. In this paper, a model of the relation is given between yield and reliability based on a discrete yield model, many factors are considered in this model, such as the line width, the spacing between the lines as well as the distribution of the defect size and so on. Finally, the validity of this model is shown by simulation.
良率和可靠性是影响半导体制造业发展的两个重要因素。如何表达成品率与可靠性之间的关系是一个重要的问题。本文在离散良率模型的基础上,建立了良率与可靠性的关系模型,该模型考虑了线宽、线间距、缺陷尺寸分布等因素。最后,通过仿真验证了该模型的有效性。
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引用次数: 1
Fail-safe synchronization circuit for duplicated systems 用于重复系统的故障安全同步电路
E. Kolonis, M. Nicolaidis
Actuators in safety critical systems must be driven by fail-safe signals. Under a failure in the system, such a signal must be either correct or on the safe state (e.g. red colour in traffic control lights). To achieve the fail-safe property, processors controlling such actuators use hardware and/or software redundancy (e.g. duplicated processors, software coding techniques). Each of the signals delivered by such a system must be fail-safe individually in order to drive an actuator. To create such signals, one has to use an interface that transforms the redundant signals delivered by the control processor into fail-safe signals. This can be performed by a fail-safe interface. The present work treats the case where the inputs of the interface are delivered by a duplicated system. To avoid common mode failures the two copies of the system do not share hardware resources. Thus, they use different clocks, and the two system copies are not mutually synchronized at clock cycle level. Any attempt to synchronise them will require to share some resources and will introduce common mode failures. This work proposes a circuit that transforms two copies of non-synchronised signals into synchronised signals, while at the same time preserves the safety of the system under the introduced common mode failures.
安全关键系统中的执行器必须由故障安全信号驱动。在系统发生故障时,这样的信号必须是正确的或处于安全状态(例如交通管制灯的红色)。为了实现故障安全特性,控制此类执行器的处理器使用硬件和/或软件冗余(例如,重复处理器,软件编码技术)。为了驱动执行器,这种系统所传递的每个信号都必须是独立的故障安全的。要创建这样的信号,必须使用一个接口,将控制处理器传递的冗余信号转换为故障安全信号。这可以通过故障安全接口执行。目前的工作处理的情况下,接口的输入是由一个重复的系统交付。为避免共模故障,系统的两个副本不共享硬件资源。因此,它们使用不同的时钟,并且两个系统副本在时钟周期级别上不会相互同步。任何同步它们的尝试都需要共享一些资源,并将引入公共模式故障。这项工作提出了一种电路,将非同步信号的两个副本转换为同步信号,同时在引入的共模故障下保持系统的安全性。
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引用次数: 2
Test pattern for supply current test of open defects by applying time-variable electric field 应用时变电场对开路缺陷进行供电电流检测的试验方法
H. Yotsuyanagi, M. Hashizume, Taisuke Iwakiri, M. Ichimiya, T. Tamesada
Test input vectors for a supply current test method are discussed which is used for detecting open defects in CMOS ICs. In the test method, time-variable electric field is applied from the outside of ICs so as to vary the voltage at a floating node. To generate excessive supply current by the induced voltage change at the floating node, test pattern must be provided so that a conducting path from V/sub DD/ to GND can be generated in the faulty circuit. In this paper, the requirements are denoted to be satisfied as a test input vector of the test method. Also, it is shown that test pattern of functional tests based on stuck-at fault models can be used for the open defect detection method. Furthermore, the experimental results in this paper promise that high fault coverage can be achieved by applying the subset of the stuck-at test pattern to the detection of open defects.
讨论了一种用于检测CMOS芯片开路缺陷的电源电流测试方法的测试输入向量。在测试方法中,从集成电路外部施加时变电场,从而改变浮动节点的电压。为了通过浮动节点的感应电压变化产生过大的电源电流,必须提供测试模式,以便在故障电路中产生从V/sub DD/到GND的导通路径。本文将满足的要求表示为测试方法的测试输入向量。研究表明,基于卡滞故障模型的功能测试模式可用于开放式缺陷检测方法。此外,本文的实验结果表明,将卡在测试模式的子集应用于开放缺陷的检测可以获得较高的故障覆盖率。
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引用次数: 2
Analog BIST generator for ADC testing 用于ADC测试的模拟BIST发生器
S. Bernard, F. Azaïs, Y. Bertrand, M. Renovell
In the context of analog BIST for A/D converters, this paper presents an implementation of an on-chip ramp generator. It is demonstrated that the proposed original adaptive scheme allows the internal generation of a highly sawtooth signal with a very precise control of the signal amplitude. In addition, the implementation of the adaptive ramp generator exhibits a very low silicon area.
在A/D转换器模拟BIST的背景下,本文提出了一种片上斜坡发生器的实现方法。结果表明,所提出的原始自适应方案允许内部产生高度锯齿信号,并对信号幅度进行非常精确的控制。此外,自适应斜坡发生器的实现显示出非常低的硅面积。
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引用次数: 13
期刊
Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
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