Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966767
S. Ko, T. Xia, Jien-Chung Lo
We propose, in this paper, XOR-based decomposition methods to implement parity prediction circuits efficiently in field programmable gate arrays (FPGAs). The first proposed method is an extension of the Shannon's expansion theorem. Such extension enables us to force decomposing the parity prediction circuit into appropriate size sub-circuits. The second proposed method is based on the Reed-Muller canonical form that transforms AND/OR Boolean functions to AND/XOR functions. The XOR relation enables us to find more efficient grouping for the parity prediction function. The MCNC benchmark circuits are used to demonstrate the effectiveness of the proposed techniques.
{"title":"Efficient parity prediction in FPGA","authors":"S. Ko, T. Xia, Jien-Chung Lo","doi":"10.1109/DFTVS.2001.966767","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966767","url":null,"abstract":"We propose, in this paper, XOR-based decomposition methods to implement parity prediction circuits efficiently in field programmable gate arrays (FPGAs). The first proposed method is an extension of the Shannon's expansion theorem. Such extension enables us to force decomposing the parity prediction circuit into appropriate size sub-circuits. The second proposed method is based on the Reed-Muller canonical form that transforms AND/OR Boolean functions to AND/XOR functions. The XOR relation enables us to find more efficient grouping for the parity prediction function. The MCNC benchmark circuits are used to demonstrate the effectiveness of the proposed techniques.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124165839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966777
P. Civera, L. Macchiarulo, M. Rebaudengo, M. Reorda, M. Violante
Proposes an FPGA-based system to speed-up fault injection campaigns for the evaluation of the fault-tolerant capabilities of VLSI circuits. An environment is described, relying on FPGA-based emulation of the circuit. Suitable techniques are described, allowing one to emulate the effects of faults and to observe faulty behavior. The proposed approach allows the combination of the speed of hardware-based techniques, and the flexibility of simulation-based techniques. Experimental results are provided showing that significant speed-up figures with respect to state-of-the-art simulation-based techniques can be achieved.
{"title":"Exploiting FPGA-based techniques for fault injection campaigns on VLSI circuits","authors":"P. Civera, L. Macchiarulo, M. Rebaudengo, M. Reorda, M. Violante","doi":"10.1109/DFTVS.2001.966777","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966777","url":null,"abstract":"Proposes an FPGA-based system to speed-up fault injection campaigns for the evaluation of the fault-tolerant capabilities of VLSI circuits. An environment is described, relying on FPGA-based emulation of the circuit. Suitable techniques are described, allowing one to emulate the effects of faults and to observe faulty behavior. The proposed approach allows the combination of the speed of hardware-based techniques, and the flexibility of simulation-based techniques. Experimental results are provided showing that significant speed-up figures with respect to state-of-the-art simulation-based techniques can be achieved.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128253444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966784
S. Piestrak, A. Dandache, F. Monteiro
In this paper, we consider the open problem of designing fault-secure encoders for various systematic error correcting codes (ECCs). The main idea relies on generating in parallel both the error correcting and detecting check bits. Then, the latter are compared against error detecting check bits which are regenerated from the former. The complexity evaluation of FPGA implementations of encoders with various degrees of parallelism shows that fault-secure versions compare favorably against their unprotected counterparts both with respect to complexity and the maximal frequency of operation.
{"title":"Design of fault-secure encoders for a class of systematic error correcting codes","authors":"S. Piestrak, A. Dandache, F. Monteiro","doi":"10.1109/DFTVS.2001.966784","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966784","url":null,"abstract":"In this paper, we consider the open problem of designing fault-secure encoders for various systematic error correcting codes (ECCs). The main idea relies on generating in parallel both the error correcting and detecting check bits. Then, the latter are compared against error detecting check bits which are regenerated from the former. The complexity evaluation of FPGA implementations of encoders with various degrees of parallelism shows that fault-secure versions compare favorably against their unprotected counterparts both with respect to complexity and the maximal frequency of operation.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134480862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966774
Xiaoling Sun, Jian Xu, P. Trouborst
This paper presents a novel built-in self-test (BIST) scheme for configurable logic blocks (CLBs) of Xilinx XC4000 field programmable gate arrays (FPGAs). The test of the dedicated carry logic module (CLM) within a CLB is included for the first time. A minimum of eight CLB test configurations is given. A centralized BIST architecture supports the single stuck-at fault test of the CLM and the whole CLB. The scheme is also capable of locating any faulty CLBs with the maximum diagnostic resolution, two adjacent CLBs.
{"title":"Testing Xilinx XC4000 configurable logic blocks with carry logic-modules","authors":"Xiaoling Sun, Jian Xu, P. Trouborst","doi":"10.1109/DFTVS.2001.966774","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966774","url":null,"abstract":"This paper presents a novel built-in self-test (BIST) scheme for configurable logic blocks (CLBs) of Xilinx XC4000 field programmable gate arrays (FPGAs). The test of the dedicated carry logic module (CLM) within a CLB is included for the first time. A minimum of eight CLB test configurations is given. A centralized BIST architecture supports the single stuck-at fault test of the CLM and the whole CLB. The scheme is also capable of locating any faulty CLBs with the maximum diagnostic resolution, two adjacent CLBs.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124598631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966749
T. S. Barnett, A. Singh, V. Nelson
An integrated yield-reliability model for defect tolerant integrated circuits is presented that allows one to estimate the yield following both wafer probe and burn-in testing. The model is based on the long observed clustering of defects and the experimentally verified relation between defects causing wafer probe failures and defects causing infant mortality failures. The two-parameter negative binomial distribution is used to describe the distribution of defects over a semiconductor wafer. The clustering parameter /spl alpha/, while known to play a key role in accurately determining wafer probe yields of defect tolerant chips, is shown for the first time. to play a similar role in determining burn-in fall-out. Numerical results indicate that the number of infant mortality failures predicted by the clustering model can differ significantly from calculations that ignore clustering.
{"title":"Yield-reliability modeling for fault tolerant integrated circuits","authors":"T. S. Barnett, A. Singh, V. Nelson","doi":"10.1109/DFTVS.2001.966749","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966749","url":null,"abstract":"An integrated yield-reliability model for defect tolerant integrated circuits is presented that allows one to estimate the yield following both wafer probe and burn-in testing. The model is based on the long observed clustering of defects and the experimentally verified relation between defects causing wafer probe failures and defects causing infant mortality failures. The two-parameter negative binomial distribution is used to describe the distribution of defects over a semiconductor wafer. The clustering parameter /spl alpha/, while known to play a key role in accurately determining wafer probe yields of defect tolerant chips, is shown for the first time. to play a similar role in determining burn-in fall-out. Numerical results indicate that the number of infant mortality failures predicted by the clustering model can differ significantly from calculations that ignore clustering.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126325611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966758
J. Sosnowski
Deals with the problem of fault detection and fault handling robustness in BIST schemes. In particular we analyze the susceptibility of signature analyzers to internal faults. Various fault models (black box) within the analyzer circuitry are taken into account. Moreover we check fault impact on software procedures related to BIST and error handling mechanisms using software implemented fault injector.
{"title":"Analyzing BIST robustness","authors":"J. Sosnowski","doi":"10.1109/DFTVS.2001.966758","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966758","url":null,"abstract":"Deals with the problem of fault detection and fault handling robustness in BIST schemes. In particular we analyze the susceptibility of signature analyzers to internal faults. Various fault models (black box) within the analyzer circuitry are taken into account. Moreover we check fault impact on software procedures related to BIST and error handling mechanisms using software implemented fault injector.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121651400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966751
Tianxu Zhao, Y. Hao, Peijun Ma, Ta-Te Chen
Yield and reliability are two important factors affecting the development of semiconductor manufacturing. It is an important problem, how to express the relation between yield and reliability. In this paper, a model of the relation is given between yield and reliability based on a discrete yield model, many factors are considered in this model, such as the line width, the spacing between the lines as well as the distribution of the defect size and so on. Finally, the validity of this model is shown by simulation.
{"title":"Relation between reliability and yield of ICs based on discrete defect distribution model","authors":"Tianxu Zhao, Y. Hao, Peijun Ma, Ta-Te Chen","doi":"10.1109/DFTVS.2001.966751","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966751","url":null,"abstract":"Yield and reliability are two important factors affecting the development of semiconductor manufacturing. It is an important problem, how to express the relation between yield and reliability. In this paper, a model of the relation is given between yield and reliability based on a discrete yield model, many factors are considered in this model, such as the line width, the spacing between the lines as well as the distribution of the defect size and so on. Finally, the validity of this model is shown by simulation.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125468788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966795
E. Kolonis, M. Nicolaidis
Actuators in safety critical systems must be driven by fail-safe signals. Under a failure in the system, such a signal must be either correct or on the safe state (e.g. red colour in traffic control lights). To achieve the fail-safe property, processors controlling such actuators use hardware and/or software redundancy (e.g. duplicated processors, software coding techniques). Each of the signals delivered by such a system must be fail-safe individually in order to drive an actuator. To create such signals, one has to use an interface that transforms the redundant signals delivered by the control processor into fail-safe signals. This can be performed by a fail-safe interface. The present work treats the case where the inputs of the interface are delivered by a duplicated system. To avoid common mode failures the two copies of the system do not share hardware resources. Thus, they use different clocks, and the two system copies are not mutually synchronized at clock cycle level. Any attempt to synchronise them will require to share some resources and will introduce common mode failures. This work proposes a circuit that transforms two copies of non-synchronised signals into synchronised signals, while at the same time preserves the safety of the system under the introduced common mode failures.
{"title":"Fail-safe synchronization circuit for duplicated systems","authors":"E. Kolonis, M. Nicolaidis","doi":"10.1109/DFTVS.2001.966795","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966795","url":null,"abstract":"Actuators in safety critical systems must be driven by fail-safe signals. Under a failure in the system, such a signal must be either correct or on the safe state (e.g. red colour in traffic control lights). To achieve the fail-safe property, processors controlling such actuators use hardware and/or software redundancy (e.g. duplicated processors, software coding techniques). Each of the signals delivered by such a system must be fail-safe individually in order to drive an actuator. To create such signals, one has to use an interface that transforms the redundant signals delivered by the control processor into fail-safe signals. This can be performed by a fail-safe interface. The present work treats the case where the inputs of the interface are delivered by a duplicated system. To avoid common mode failures the two copies of the system do not share hardware resources. Thus, they use different clocks, and the two system copies are not mutually synchronized at clock cycle level. Any attempt to synchronise them will require to share some resources and will introduce common mode failures. This work proposes a circuit that transforms two copies of non-synchronised signals into synchronised signals, while at the same time preserves the safety of the system under the introduced common mode failures.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129516287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966781
H. Yotsuyanagi, M. Hashizume, Taisuke Iwakiri, M. Ichimiya, T. Tamesada
Test input vectors for a supply current test method are discussed which is used for detecting open defects in CMOS ICs. In the test method, time-variable electric field is applied from the outside of ICs so as to vary the voltage at a floating node. To generate excessive supply current by the induced voltage change at the floating node, test pattern must be provided so that a conducting path from V/sub DD/ to GND can be generated in the faulty circuit. In this paper, the requirements are denoted to be satisfied as a test input vector of the test method. Also, it is shown that test pattern of functional tests based on stuck-at fault models can be used for the open defect detection method. Furthermore, the experimental results in this paper promise that high fault coverage can be achieved by applying the subset of the stuck-at test pattern to the detection of open defects.
{"title":"Test pattern for supply current test of open defects by applying time-variable electric field","authors":"H. Yotsuyanagi, M. Hashizume, Taisuke Iwakiri, M. Ichimiya, T. Tamesada","doi":"10.1109/DFTVS.2001.966781","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966781","url":null,"abstract":"Test input vectors for a supply current test method are discussed which is used for detecting open defects in CMOS ICs. In the test method, time-variable electric field is applied from the outside of ICs so as to vary the voltage at a floating node. To generate excessive supply current by the induced voltage change at the floating node, test pattern must be provided so that a conducting path from V/sub DD/ to GND can be generated in the faulty circuit. In this paper, the requirements are denoted to be satisfied as a test input vector of the test method. Also, it is shown that test pattern of functional tests based on stuck-at fault models can be used for the open defect detection method. Furthermore, the experimental results in this paper promise that high fault coverage can be achieved by applying the subset of the stuck-at test pattern to the detection of open defects.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130092441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-24DOI: 10.1109/DFTVS.2001.966787
S. Bernard, F. Azaïs, Y. Bertrand, M. Renovell
In the context of analog BIST for A/D converters, this paper presents an implementation of an on-chip ramp generator. It is demonstrated that the proposed original adaptive scheme allows the internal generation of a highly sawtooth signal with a very precise control of the signal amplitude. In addition, the implementation of the adaptive ramp generator exhibits a very low silicon area.
{"title":"Analog BIST generator for ADC testing","authors":"S. Bernard, F. Azaïs, Y. Bertrand, M. Renovell","doi":"10.1109/DFTVS.2001.966787","DOIUrl":"https://doi.org/10.1109/DFTVS.2001.966787","url":null,"abstract":"In the context of analog BIST for A/D converters, this paper presents an implementation of an on-chip ramp generator. It is demonstrated that the proposed original adaptive scheme allows the internal generation of a highly sawtooth signal with a very precise control of the signal amplitude. In addition, the implementation of the adaptive ramp generator exhibits a very low silicon area.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120892557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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