Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0049
John Bescup
This paper describes a project to develop and deploy a systematic screening methodology involving computed tomography (CT) to inspect a set of electromagnetic interference (EMI) filter components for a spacecraft application. The goal was to deploy the nondestructive CT test to replace the destructive test method typically deployed for such components. The paper describes the development of test criteria, fixturing, inspection process, and data analysis, including quantitative image analysis of voids and cracks. The initial results indicated that the parts would not pass the requirements established in the test design. A waiver was written to the project clarifying that if the parts were to be used in the assembly, they should be considered as simple conductors with EMI filtering capability viewed as an added benefit rather than a guaranteed design requirement.
{"title":"Large-Scale CT Inspection of Feed-Through EMI Filters for Space Application","authors":"John Bescup","doi":"10.31399/asm.cp.istfa2021p0049","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0049","url":null,"abstract":"\u0000 This paper describes a project to develop and deploy a systematic screening methodology involving computed tomography (CT) to inspect a set of electromagnetic interference (EMI) filter components for a spacecraft application. The goal was to deploy the nondestructive CT test to replace the destructive test method typically deployed for such components. The paper describes the development of test criteria, fixturing, inspection process, and data analysis, including quantitative image analysis of voids and cracks. The initial results indicated that the parts would not pass the requirements established in the test design. A waiver was written to the project clarifying that if the parts were to be used in the assembly, they should be considered as simple conductors with EMI filtering capability viewed as an added benefit rather than a guaranteed design requirement.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129038502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0190
Maria Brodovoi, K. Gruel, L. Chapuis, A. Masseboeuf, C. Marcelot, M. Hÿtch, F. Lorut, C. Gatel
In response to a continually rising demand for high performance and low-cost devices, and equally driven by competitivity, the microelectronics industry excels in meeting innovation challenges and further miniaturizing products. However, device shrinkage and the increasing complexity of device architecture require local quantitative studies. In this paper, we demonstrate with a case study on a nanocapacitor, the capability of transmission electron microscopy in electron holography mode to be a unique in-situ technique for mapping electric fields and charge distributions on a single device.
{"title":"In-Situ Electrical Biasing of Electrically Connected TEM Lamellae with Embedded Nanodevices","authors":"Maria Brodovoi, K. Gruel, L. Chapuis, A. Masseboeuf, C. Marcelot, M. Hÿtch, F. Lorut, C. Gatel","doi":"10.31399/asm.cp.istfa2021p0190","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0190","url":null,"abstract":"\u0000 In response to a continually rising demand for high performance and low-cost devices, and equally driven by competitivity, the microelectronics industry excels in meeting innovation challenges and further miniaturizing products. However, device shrinkage and the increasing complexity of device architecture require local quantitative studies. In this paper, we demonstrate with a case study on a nanocapacitor, the capability of transmission electron microscopy in electron holography mode to be a unique in-situ technique for mapping electric fields and charge distributions on a single device.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127648654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0179
Tasnuva Farheen, Ulbert J. Botero, Nitin Varshney, D. Woodard, M. Tehranipoor, Domenic Forte, Haoting Shen
IC camouflaging has been proposed as a promising countermeasure against malicious reverse engineering. Camouflaged gates contain multiple functional device structures, but appear as one single layout under microscope imaging, thereby hiding the real circuit functionality from adversaries. The recent covert gate camouflaging design comes with a significantly reduced overhead cost, allowing numerous camouflaged gates in circuits and thus being resilient against various invasive and semi-invasive attacks. Dummy inputs are used in the design, but SEM imaging analysis was only performed on simplified dummy contact structures in prior work. Whether the e-beam during SEM imaging will charge differently on different contacts and further reveal the different structures or not requires extended research. In this study, we fabricated real and dummy contacts in various structures and performed a systematic SEM imaging analysis to investigate the possible charging and the consequent passive voltage contrast on contacts. In addition, machine-learning based pattern recognition was also employed to examine the possibility of differentiating real and dummy contacts. Based on our experimental results, we found that the difference between real and dummy contacts is insignificant in SEM imaging, which effectively prevents adversarial SEM-based reverse engineering. Index Terms—Reverse Engineering, IC Camouflaging, Scanning Electron Microscopy, Machine Learning, Countermeasure.
{"title":"Proof of Reverse Engineering Barrier: SEM Image Analysis on Covert Gates","authors":"Tasnuva Farheen, Ulbert J. Botero, Nitin Varshney, D. Woodard, M. Tehranipoor, Domenic Forte, Haoting Shen","doi":"10.31399/asm.cp.istfa2021p0179","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0179","url":null,"abstract":"\u0000 IC camouflaging has been proposed as a promising countermeasure against malicious reverse engineering. Camouflaged gates contain multiple functional device structures, but appear as one single layout under microscope imaging, thereby hiding the real circuit functionality from adversaries. The recent covert gate camouflaging design comes with a significantly reduced overhead cost, allowing numerous camouflaged gates in circuits and thus being resilient against various invasive and semi-invasive attacks. Dummy inputs are used in the design, but SEM imaging analysis was only performed on simplified dummy contact structures in prior work. Whether the e-beam during SEM imaging will charge differently on different contacts and further reveal the different structures or not requires extended research. In this study, we fabricated real and dummy contacts in various structures and performed a systematic SEM imaging analysis to investigate the possible charging and the consequent passive voltage contrast on contacts. In addition, machine-learning based pattern recognition was also employed to examine the possibility of differentiating real and dummy contacts. Based on our experimental results, we found that the difference between real and dummy contacts is insignificant in SEM imaging, which effectively prevents adversarial SEM-based reverse engineering.\u0000 Index Terms—Reverse Engineering, IC Camouflaging, Scanning Electron Microscopy, Machine Learning, Countermeasure.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124508267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0172
John True, Chengjie Xi, Aslam A. Khan, J. Hihath, N. Asadizanjani
Semiconductor manufacturing has been outsourced to un-trusted regions due to globalization. The complex multistep fabrication of micro-scale integrated circuits (ICs) and the tedious assembly of macro-scale Printed Circuit Boards (PCBs) are vulnerable to malicious attacks from design to final delivery. PCBs provide the functional connections of Integrated Circuits (ICs), sensors, power supplies, etc. of many critical electronic systems for consumers, corporations, and governments. The feature sizes of PCB signal traces in 2D and vias in 3D are an order of magnitude larger than IC devices, and are thereby more vulnerable to non-destructive attacks such as X-ray or probing. Active and passive countermeasures have been successfully developed for IC devices, however PCBs devices are difficult to wholly secure from all attacks. Passive countermeasures for X-ray attacks using high-z materials to block and scatter X-rays are effective, but there is a lack of active and passive countermeasures for PCB. In this paper, a framework for passively obfuscating a PCB's critical connections between components, such as ICs, from non-destructive attacks is demonstrated. This framework can be further extended to incorporate active countermeasures in future work. A proof of concept for a PCB electronic design automation (EDA) tool which combines the small features of micro electro-mechanical systems (MEMS), simulation of X-ray, and 3D PCB Manufacturing to iteratively optimize PCB design to thwart reverse engineering and probing attacks. Index Terms—Additive Manufacturing, MEMS, Hardware Assurance, Physical Inspection, Non-Destructive Technology
{"title":"PCB Netlist Obfuscation with Micro Electro Mechanical Systems and Additive Manufacturing Techniques","authors":"John True, Chengjie Xi, Aslam A. Khan, J. Hihath, N. Asadizanjani","doi":"10.31399/asm.cp.istfa2021p0172","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0172","url":null,"abstract":"\u0000 Semiconductor manufacturing has been outsourced to un-trusted regions due to globalization. The complex multistep fabrication of micro-scale integrated circuits (ICs) and the tedious assembly of macro-scale Printed Circuit Boards (PCBs) are vulnerable to malicious attacks from design to final delivery. PCBs provide the functional connections of Integrated Circuits (ICs), sensors, power supplies, etc. of many critical electronic systems for consumers, corporations, and governments. The feature sizes of PCB signal traces in 2D and vias in 3D are an order of magnitude larger than IC devices, and are thereby more vulnerable to non-destructive attacks such as X-ray or probing. Active and passive countermeasures have been successfully developed for IC devices, however PCBs devices are difficult to wholly secure from all attacks. Passive countermeasures for X-ray attacks using high-z materials to block and scatter X-rays are effective, but there is a lack of active and passive countermeasures for PCB. In this paper, a framework for passively obfuscating a PCB's critical connections between components, such as ICs, from non-destructive attacks is demonstrated. This framework can be further extended to incorporate active countermeasures in future work. A proof of concept for a PCB electronic design automation (EDA) tool which combines the small features of micro electro-mechanical systems (MEMS), simulation of X-ray, and 3D PCB Manufacturing to iteratively optimize PCB design to thwart reverse engineering and probing attacks.\u0000 Index Terms—Additive Manufacturing, MEMS, Hardware Assurance, Physical Inspection, Non-Destructive Technology","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121542312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0306
Doo-chan Jung, Young-Ha Choi, Jae In Lee, Bu-Il Nam, Ki-Young Dong, Bohchang Kim, Eun-Kyoung Kim, Ki-Whan Song, J. Song, Myungsuk Kim, W. Choi
A novel electrical screening method of channel hole bending (ChB) defects is proposed for the implementation of high-density vertical NAND (VNAND) flash memory. The ChB defects induces the leakage current between the two adjacent channel holes, which leads to fatal failure in storage systems. Thus, it is one of the key requirements for VNAND mass production to screen ChB defects electrically in advance. In the proposed screening method, a 3D checkerboard (CKBD) pattern is introduced, which consists of alternating programed (‘0’) and inhibited (‘1’) memory cells in a diagonal and horizontal direction. By measuring the leakage current between the channel holes, ChB defects can be successfully detected electrically.
{"title":"Electrical Screening Method of VNAND Flash Channel Hole Bending Defects","authors":"Doo-chan Jung, Young-Ha Choi, Jae In Lee, Bu-Il Nam, Ki-Young Dong, Bohchang Kim, Eun-Kyoung Kim, Ki-Whan Song, J. Song, Myungsuk Kim, W. Choi","doi":"10.31399/asm.cp.istfa2021p0306","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0306","url":null,"abstract":"\u0000 A novel electrical screening method of channel hole bending (ChB) defects is proposed for the implementation of high-density vertical NAND (VNAND) flash memory. The ChB defects induces the leakage current between the two adjacent channel holes, which leads to fatal failure in storage systems. Thus, it is one of the key requirements for VNAND mass production to screen ChB defects electrically in advance. In the proposed screening method, a 3D checkerboard (CKBD) pattern is introduced, which consists of alternating programed (‘0’) and inhibited (‘1’) memory cells in a diagonal and horizontal direction. By measuring the leakage current between the channel holes, ChB defects can be successfully detected electrically.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128510876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0253
Gregory M. Johnson, A. Rummel
An experimental study was undertaken to determine the minimum level of leakage or shorting current could be detected by EBIRCH. A 22 nm SRAM array was overstressed with a series gradually increasing bias, followed by EBIRCH scans with 1 V applied bias and 2 kV SEM imaging, until fins were observed. The result was that with only 12 nA of shorting current, the fins of a pulldown device could be imaged by EBIRCH. Higher stresses created an ohmic short, and careful consideration of experiments with current direction provide additional evidence that EBIRCH is largely a temperaturedriven, or Seebeck effect.
{"title":"EBIRCH Localization for Low-Current Soft Fails","authors":"Gregory M. Johnson, A. Rummel","doi":"10.31399/asm.cp.istfa2021p0253","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0253","url":null,"abstract":"An experimental study was undertaken to determine the minimum level of leakage or shorting current could be detected by EBIRCH. A 22 nm SRAM array was overstressed with a series gradually increasing bias, followed by EBIRCH scans with 1 V applied bias and 2 kV SEM imaging, until fins were observed. The result was that with only 12 nA of shorting current, the fins of a pulldown device could be imaged by EBIRCH. Higher stresses created an ohmic short, and careful consideration of experiments with current direction provide additional evidence that EBIRCH is largely a temperaturedriven, or Seebeck effect.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125270225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0394
Y. Chan, S. H. Goh
Narrowing design and manufacturing process margins with technology scaling are one of the causes for a reduction in IC chip test margin. This situation is further aggravated by the extensive use of third-party design blocks in contemporary system-on-chips which complicates chip timing constraint. Since a thorough timing verification prior to silicon fabrication is usually not done due to aggressive product launch schedules and escalating design cost, occasionally, a post-silicon timing optimization process is required to eliminate false fails encountered on ATE. An iterative two-dimensional shmoo plots and pin margin analysis are custom optimization methods to accomplish this. However, these methods neglect the interdependencies between different IO timing edges such that a truly optimized condition cannot be attained. In this paper, we present a robust and automated solution based on a genetic algorithm approach. Elimination of shmoo holes and widening of test margins (up to 2x enhancements) are demonstrated on actual product test cases. Besides test margin optimization, this method also offers insights into the criticality of test pins to accelerate failure debug turnaround time.
{"title":"Genetic Algorithm-Based Digital Test Optimization Method and its Application to Yield Improvement","authors":"Y. Chan, S. H. Goh","doi":"10.31399/asm.cp.istfa2021p0394","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0394","url":null,"abstract":"\u0000 Narrowing design and manufacturing process margins with technology scaling are one of the causes for a reduction in IC chip test margin. This situation is further aggravated by the extensive use of third-party design blocks in contemporary system-on-chips which complicates chip timing constraint. Since a thorough timing verification prior to silicon fabrication is usually not done due to aggressive product launch schedules and escalating design cost, occasionally, a post-silicon timing optimization process is required to eliminate false fails encountered on ATE. An iterative two-dimensional shmoo plots and pin margin analysis are custom optimization methods to accomplish this. However, these methods neglect the interdependencies between different IO timing edges such that a truly optimized condition cannot be attained. In this paper, we present a robust and automated solution based on a genetic algorithm approach. Elimination of shmoo holes and widening of test margins (up to 2x enhancements) are demonstrated on actual product test cases. Besides test margin optimization, this method also offers insights into the criticality of test pins to accelerate failure debug turnaround time.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129927679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0034
J. Demarest, N. Arnold, K. Brew, V. Chan, A. Cote, T. Gordon, M. Iwatake, G. Lian, J. Li, I. Ok, S. Mcdermott, I. Saraf, N. Saulnier, L. Tierney, A. Varghese
There are several variants of artificial intelligence (AI) hardware structures which are under study by the semiconductor industry as potential future synergistic technology adders to existing complementary metal–oxide–semiconductor (CMOS) designs. This paper will discuss some of the failure analysis challenges which have appeared in discrete test structures and test arrays of an exploratory PCM program at IBM's Albany AI Hardware Research Center.
{"title":"Failure Analysis Challenges of Phase Change Memory Test Structures with Two Case Studies","authors":"J. Demarest, N. Arnold, K. Brew, V. Chan, A. Cote, T. Gordon, M. Iwatake, G. Lian, J. Li, I. Ok, S. Mcdermott, I. Saraf, N. Saulnier, L. Tierney, A. Varghese","doi":"10.31399/asm.cp.istfa2021p0034","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0034","url":null,"abstract":"\u0000 There are several variants of artificial intelligence (AI) hardware structures which are under study by the semiconductor industry as potential future synergistic technology adders to existing complementary metal–oxide–semiconductor (CMOS) designs. This paper will discuss some of the failure analysis challenges which have appeared in discrete test structures and test arrays of an exploratory PCM program at IBM's Albany AI Hardware Research Center.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126825576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0224
Randal E. Mulder
A major customer had been returning devices for nonvolatile memory (NVM) data retention bit failures. The ppm level was low but the continued fallout at the customer location was causing a quality and reliability concern. The customer wanted a resolution as to the cause of the failures and for a corrective action. An NVM bit data retention failure occurs when a programmed bit loses it programmed data state over time and flips to the opposite data state (0 -> 1 or 1 -> 0) causing a programming error. Previous failure analysis results on several failing devices with a single NVM bit data retention failure was inconclusive. TEM analysis showed no difference between the failing bit and neighboring passing bit. The lack of results led to the questioning of the accuracy of the bit map documentation and if the TEM analysis was being performed at the correct bit location. Bit map documentation takes the failing bit's electrical address and converts it to a physical address location. If the bit map documentation is incorrect, locating the failing bit is not possible and physical failure analysis will not be performed at the correct bit location. This paper will demonstrate how Atomic Force Probe (AFP) nanoprobe analysis was used to first verify the bit map documentation by determining the programming of bits at specific locations through bit cell characterization; and then characterize the failing bit location to verify the programming error and determine the possible failure mechanism based on its electrical signature followed by the appropriate physical analysis to determine the failure mechanism.
{"title":"Resolution of Customer Return Non-Volatile Memory Data Retention Bit Failures through Bit Map Verification and Bit Cell Characterization by Nanoprobe Analysis","authors":"Randal E. Mulder","doi":"10.31399/asm.cp.istfa2021p0224","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0224","url":null,"abstract":"\u0000 A major customer had been returning devices for nonvolatile memory (NVM) data retention bit failures. The ppm level was low but the continued fallout at the customer location was causing a quality and reliability concern. The customer wanted a resolution as to the cause of the failures and for a corrective action.\u0000 An NVM bit data retention failure occurs when a programmed bit loses it programmed data state over time and flips to the opposite data state (0 -> 1 or 1 -> 0) causing a programming error. Previous failure analysis results on several failing devices with a single NVM bit data retention failure was inconclusive. TEM analysis showed no difference between the failing bit and neighboring passing bit. The lack of results led to the questioning of the accuracy of the bit map documentation and if the TEM analysis was being performed at the correct bit location. Bit map documentation takes the failing bit's electrical address and converts it to a physical address location. If the bit map documentation is incorrect, locating the failing bit is not possible and physical failure analysis will not be performed at the correct bit location.\u0000 This paper will demonstrate how Atomic Force Probe (AFP) nanoprobe analysis was used to first verify the bit map documentation by determining the programming of bits at specific locations through bit cell characterization; and then characterize the failing bit location to verify the programming error and determine the possible failure mechanism based on its electrical signature followed by the appropriate physical analysis to determine the failure mechanism.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133011018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The emergence of Heterogenous Integration (HI) in today's wave of systems-in-package (SiP) has not only increased the complexity of semiconductor Failure Analysis (FA), but also introduced new challenges that go beyond the traditional FA lab, into market verticals such as Assembly and Test. Today's market requires semiconductor companies to collaborate with these verticals to efficiently debug failures in advanced package devices. In this increasingly collaborative industry, FA engineers struggle to maintain adequate security of their company's intellectual property (IP) while sharing design information that is required for effective fault localization of SiP products. On top of these growing complications, increased commercial competition and the drastic rise in the demand for consumer electronics has made time-to-market (TTM) the top priority for all global chip makers. To address these challenges, companies strive for ways to integrate various design sources into a normalized and controllable Computer-Aided Design (CAD) database that can be seamlessly navigated across multiple components without exposing sensitive information. This paper covers an approach to enhance the efficiency of advanced package FA by integrating a full heterogeneous system into a single CAD Navigation (CADNav) database with added security measures to enable data sharing for industry-wide collaboration.
{"title":"Heterogeneous Industry Collaboration and System CAD Navigation for Advanced Package Failure Analysis","authors":"Arpan Bhattacherjee, Anand Shankar, Arshdeep Singh, Mehak Singla","doi":"10.31399/asm.cp.istfa2021p0108","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0108","url":null,"abstract":"\u0000 The emergence of Heterogenous Integration (HI) in today's wave of systems-in-package (SiP) has not only increased the complexity of semiconductor Failure Analysis (FA), but also introduced new challenges that go beyond the traditional FA lab, into market verticals such as Assembly and Test. Today's market requires semiconductor companies to collaborate with these verticals to efficiently debug failures in advanced package devices. In this increasingly collaborative industry, FA engineers struggle to maintain adequate security of their company's intellectual property (IP) while sharing design information that is required for effective fault localization of SiP products. On top of these growing complications, increased commercial competition and the drastic rise in the demand for consumer electronics has made time-to-market (TTM) the top priority for all global chip makers. To address these challenges, companies strive for ways to integrate various design sources into a normalized and controllable Computer-Aided Design (CAD) database that can be seamlessly navigated across multiple components without exposing sensitive information. This paper covers an approach to enhance the efficiency of advanced package FA by integrating a full heterogeneous system into a single CAD Navigation (CADNav) database with added security measures to enable data sharing for industry-wide collaboration.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130581960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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