Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0334
A. Merassi, M. Medda
The aim of this paper is to disclose an alternative FA approach to handle complex cases, showing multiple chain failures with multiple candidates. Starting from a commonality layout analysis of candidates resulting from the diagnosis, it is possible to identify a common interconnection shared between the several candidates, already at schematic level. The effectiveness of such analysis has been successfully verified by means of a photo-emission microscopy (PEM) analysis, while running scan chain patterns and by physical analysis.
{"title":"Commonality Analysis for Multiple Chain Integrity Failures","authors":"A. Merassi, M. Medda","doi":"10.31399/asm.cp.istfa2021p0334","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0334","url":null,"abstract":"\u0000 The aim of this paper is to disclose an alternative FA approach to handle complex cases, showing multiple chain failures with multiple candidates. Starting from a commonality layout analysis of candidates resulting from the diagnosis, it is possible to identify a common interconnection shared between the several candidates, already at schematic level. The effectiveness of such analysis has been successfully verified by means of a photo-emission microscopy (PEM) analysis, while running scan chain patterns and by physical analysis.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134115865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0352
Lori L. Sarnecki, Regina Kuan
The integrity of a P-type or N-type epitaxial layer, implanted wells, or dopants (i.e. P-epi, N-well, P-imp, N-imp, etc.) oftentimes can affect the performance of an integrated circuit (IC), especially in analog/mixed signal devices. At onsemi, we had encountered a poor P-N junction of a Zener diode that caused a Cross-Coupled-Switched-Cap voltage doubler to have a lower output voltage which eventually affected the performance of the IC. The integrity of any P-N junction can be electrically verified through curve tracing with in-SEM nano-probing and fault isolation (PEM, OBIRCH, etc.) techniques. However, physical defect revelation using junction stain, either top-down or in cross section, can be challenging due to the three-dimensional (3D) form of any P-N junction. With Electron Beam Induced Current (EBIC), we can easily identify an abnormal P-N junction through both topdown and cross section. This paper is to characterize EBIC analysis on IC cross sectional view in mapping the P-N junctions and provide the information of its doping profiles. In this paper, limitation of both chemical etching and EBIC will be discussed as well as introducing the use of ion mill after FIB cross section during cross sectional EBIC sample prep as a potential method for resolution enhancement. These findings add to the understanding in using this technique and further improvement to its application in failure analysis.
{"title":"P-N Junction Analysis using Electron Beam Induced Current (EBIC) Technique","authors":"Lori L. Sarnecki, Regina Kuan","doi":"10.31399/asm.cp.istfa2021p0352","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0352","url":null,"abstract":"\u0000 The integrity of a P-type or N-type epitaxial layer, implanted wells, or dopants (i.e. P-epi, N-well, P-imp, N-imp, etc.) oftentimes can affect the performance of an integrated circuit (IC), especially in analog/mixed signal devices. At onsemi, we had encountered a poor P-N junction of a Zener diode that caused a Cross-Coupled-Switched-Cap voltage doubler to have a lower output voltage which eventually affected the performance of the IC. The integrity of any P-N junction can be electrically verified through curve tracing with in-SEM nano-probing and fault isolation (PEM, OBIRCH, etc.) techniques. However, physical defect revelation using junction stain, either top-down or in cross section, can be challenging due to the three-dimensional (3D) form of any P-N junction. With Electron Beam Induced Current (EBIC), we can easily identify an abnormal P-N junction through both topdown and cross section. This paper is to characterize EBIC analysis on IC cross sectional view in mapping the P-N junctions and provide the information of its doping profiles. In this paper, limitation of both chemical etching and EBIC will be discussed as well as introducing the use of ion mill after FIB cross section during cross sectional EBIC sample prep as a potential method for resolution enhancement. These findings add to the understanding in using this technique and further improvement to its application in failure analysis.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133298411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0163
C. Pawlowicz, Bruno Trindade, Michael Green
A modern reverse engineering (RE) workflow contains many challenges, especially as process nodes drop below the 5nm node. With increased complexity, more circuitry is packed into a smaller area, requiring large quantities of raw data collected and subsequently processed to help reconstruct the original schematics. By leveraging inexpensive cloud computing, orders of magnitude improvement in throughput were achieved for 2D image registration and high quality image segmentation was achieved using machine learning.
{"title":"The Role of Cloud Computing in a Modern Reverse Engineering Workflow at the 5nm Node and Beyond","authors":"C. Pawlowicz, Bruno Trindade, Michael Green","doi":"10.31399/asm.cp.istfa2021p0163","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0163","url":null,"abstract":"\u0000 A modern reverse engineering (RE) workflow contains many challenges, especially as process nodes drop below the 5nm node. With increased complexity, more circuitry is packed into a smaller area, requiring large quantities of raw data collected and subsequently processed to help reconstruct the original schematics. By leveraging inexpensive cloud computing, orders of magnitude improvement in throughput were achieved for 2D image registration and high quality image segmentation was achieved using machine learning.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130855156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0154
S. Chef, C. T. Chua, J. Tay, C. Gan
The use of optical techniques for attacking integrated circuits (ICs) at the silicon level is increasingly being reported. Although these attacks can be complex to set and require skilled attacker that can access expensive equipment, they are nonetheless very powerful. Among the different applications described in literature, there has been a focus on extracting data directly from embedded SRAM. Such attacks can provide access to highly sensitive information such as encryption keys and bypass various security strategies. An attacker usually exploits one of the several interactions that exist between light and semiconductor to generate an image where content can be directly qualified by the data in memory (Logic State Image – LSI). Thermal laser stimulation (TLS) and laser probing (EOFM-Electro-Optical Frequency Mapping) have been reported in the literature recently but Photoelectric Laser Stimulation (PLS) did not get as much attention. Considering the potential advantages of PLS over other techniques (e.g. lower power requirements to generate current/voltage change, effect can be triggered at shorter wavelength which may lead to an improved spatial resolution), we investigate in this paper if logic state images can be generated with PLS on a variety of devices and do a comparative assessment with state-of-the-art technologies to assess potential benefits and limitations.
{"title":"Quantitative Study of Photoelectric Laser Stimulation for Logic State Imaging in Embedded SRAM","authors":"S. Chef, C. T. Chua, J. Tay, C. Gan","doi":"10.31399/asm.cp.istfa2021p0154","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0154","url":null,"abstract":"\u0000 The use of optical techniques for attacking integrated circuits (ICs) at the silicon level is increasingly being reported. Although these attacks can be complex to set and require skilled attacker that can access expensive equipment, they are nonetheless very powerful. Among the different applications described in literature, there has been a focus on extracting data directly from embedded SRAM. Such attacks can provide access to highly sensitive information such as encryption keys and bypass various security strategies. An attacker usually exploits one of the several interactions that exist between light and semiconductor to generate an image where content can be directly qualified by the data in memory (Logic State Image – LSI). Thermal laser stimulation (TLS) and laser probing (EOFM-Electro-Optical Frequency Mapping) have been reported in the literature recently but Photoelectric Laser Stimulation (PLS) did not get as much attention. Considering the potential advantages of PLS over other techniques (e.g. lower power requirements to generate current/voltage change, effect can be triggered at shorter wavelength which may lead to an improved spatial resolution), we investigate in this paper if logic state images can be generated with PLS on a variety of devices and do a comparative assessment with state-of-the-art technologies to assess potential benefits and limitations.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121326833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0196
M. Lo, Jay Anderson, E. Dillon, M. Kansiz, C. Marcott
We introduce a new infrared (IR) technique that provides submicron spatial resolution by making use of an infraredvisible, pump-probe arrangement that also offers a simultaneous Raman measurement in formerly challenging failure and contamination analyses. These challenges are typically due to the lack of spatial resolution and sample preparation restrictions from conventional FTIR, plus auto-fluorescence (AF) from Raman spectroscopy. Such a combined Optical PhotoThermal InfraRed (O-PTIR) and Raman instrumentation offers spatial resolution improvement over conventional IR measurements by 30 times at 1000 cm-1. The technique also improves sensitivity to exceptionally small quantities (? 400 femtogram) in reflection mode by sensing the photothermal response arising from absorbing infrared radiation (Fig. 1) [1]. The AF-free O-PTIR technique also delivers constant spatial resolution over the entire mid-IR range due to the use of a fixed wavelength probe beam at 532 nm [2]. Simultaneous Raman confirms and complements the O-PTIR measurements in cases with low AF. We will illustrate three examples that will highlight the advantage of the novel technique commonly observed in the failure and contamination analysis community.
{"title":"Submicron Non-contact Simultaneous Infrared and Raman Spectroscopy for Challenging Failure Analysis","authors":"M. Lo, Jay Anderson, E. Dillon, M. Kansiz, C. Marcott","doi":"10.31399/asm.cp.istfa2021p0196","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0196","url":null,"abstract":"\u0000 We introduce a new infrared (IR) technique that provides submicron spatial resolution by making use of an infraredvisible, pump-probe arrangement that also offers a simultaneous Raman measurement in formerly challenging failure and contamination analyses. These challenges are typically due to the lack of spatial resolution and sample preparation restrictions from conventional FTIR, plus auto-fluorescence (AF) from Raman spectroscopy. Such a combined Optical PhotoThermal InfraRed (O-PTIR) and Raman instrumentation offers spatial resolution improvement over conventional IR measurements by 30 times at 1000 cm-1. The technique also improves sensitivity to exceptionally small quantities (? 400 femtogram) in reflection mode by sensing the photothermal response arising from absorbing infrared radiation (Fig. 1) [1]. The AF-free O-PTIR technique also delivers constant spatial resolution over the entire mid-IR range due to the use of a fixed wavelength probe beam at 532 nm [2]. Simultaneous Raman confirms and complements the O-PTIR measurements in cases with low AF. We will illustrate three examples that will highlight the advantage of the novel technique commonly observed in the failure and contamination analysis community.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126610693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0269
K. C. Cheong, Gabriel Pragay, Wiwy Wudjud, Rafael Lainez
Planar deprocessing is a vital failure analysis (FA) technique for semiconductor chip reverse engineering. The basic concept of planar deprocessing is to remove all the “unnecessary” materials of a chip to expose an area of interest (AOI) and maintain the chip planarity and surface evenness. Finger deprocessing is one of the common techniques applied to this concept. This technique is essential in physical FA, especially for advanced bulk fin field-effect transistor (FinFET) devices. The success of finger deprocessing technique depends on certain factors, one of which is the location of AOI region. Application of finger deprocessing becomes incredibly challenging for AOI close to chip edge due to the chip edge effect, i. e. the chip edge is deprocessed much faster than the chip center. Plasma focused ion beam (PFIB) planar deprocessing is the primary solution to solve this problem. However, the PFIB capability is a luxury tool for most analysis labs. To overcome this challenge, a novel chip recombination method is introduced. With this method, planar deprocess can be achieved by conventional finger deprocessing technique and more importantly can be applied in general analysis labs. This paper will discuss the newly developed method in a step-by-step guide basis and show two cases with AOI(s) in the chip edge region to demonstrate its capability.
{"title":"Chip Recombination Method in Planar Deprocessing – A Solution for Failure Analysis on Chip Edge Defects","authors":"K. C. Cheong, Gabriel Pragay, Wiwy Wudjud, Rafael Lainez","doi":"10.31399/asm.cp.istfa2021p0269","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0269","url":null,"abstract":"\u0000 Planar deprocessing is a vital failure analysis (FA) technique for semiconductor chip reverse engineering. The basic concept of planar deprocessing is to remove all the “unnecessary” materials of a chip to expose an area of interest (AOI) and maintain the chip planarity and surface evenness. Finger deprocessing is one of the common techniques applied to this concept. This technique is essential in physical FA, especially for advanced bulk fin field-effect transistor (FinFET) devices. The success of finger deprocessing technique depends on certain factors, one of which is the location of AOI region. Application of finger deprocessing becomes incredibly challenging for AOI close to chip edge due to the chip edge effect, i. e. the chip edge is deprocessed much faster than the chip center. Plasma focused ion beam (PFIB) planar deprocessing is the primary solution to solve this problem. However, the PFIB capability is a luxury tool for most analysis labs. To overcome this challenge, a novel chip recombination method is introduced. With this method, planar deprocess can be achieved by conventional finger deprocessing technique and more importantly can be applied in general analysis labs. This paper will discuss the newly developed method in a step-by-step guide basis and show two cases with AOI(s) in the chip edge region to demonstrate its capability.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114613153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0146
Besmeh F. Raya
The sub-50 nm Indium Arsenide Composite Channel (IACC) High Electron Mobility Transistors (HEMTs) are fabricated on 100 mm Indium Phosphide (InP) substrates. This technology offers the best performance for low-noise and high-frequency, space and military applications. Typical failure mechanisms are observed in III-V HEMT technologies, including gate sinking, impact ionization and electromigration. Experiments were conducted to understand failure mechanisms of the IACC HEMTs by life testing devices at accelerated temperatures and biases; their electrical characteristics were measured at each stress interval. In order to determine which devices and where any defects occurred after the accelerated life tests, an additional test was completed, a Low-Noise Amplifier (LNA) Circuit assessment. The Low-Noise Amplifier (LNA) Circuit assessment determines which HEMT device is the weakest amongst the LNA circuit. Since many of the known III-V semiconductor failure mechanisms physically degrade or damage HEMTs, cross-sections are important to prepare to detect these mechanisms. In this presentation, advanced microscopy techniques with sub-nanometer resolutions, will examine physical characteristics of the HEMT at the atomic scale. The microscopy techniques will include a Focused Ion Beam/Scanning Electron Microscope (FIB/SEM), Nanomill and a Transmission Electron Microscope (TEM) along with Energy Dispersive Spectroscopy (EDS).
{"title":"Nanomilling and STEM Imaging of Sub-50 nm InP HEMT","authors":"Besmeh F. Raya","doi":"10.31399/asm.cp.istfa2021p0146","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0146","url":null,"abstract":"\u0000 The sub-50 nm Indium Arsenide Composite Channel (IACC) High Electron Mobility Transistors (HEMTs) are fabricated on 100 mm Indium Phosphide (InP) substrates. This technology offers the best performance for low-noise and high-frequency, space and military applications. Typical failure mechanisms are observed in III-V HEMT technologies, including gate sinking, impact ionization and electromigration. Experiments were conducted to understand failure mechanisms of the IACC HEMTs by life testing devices at accelerated temperatures and biases; their electrical characteristics were measured at each stress interval. In order to determine which devices and where any defects occurred after the accelerated life tests, an additional test was completed, a Low-Noise Amplifier (LNA) Circuit assessment. The Low-Noise Amplifier (LNA) Circuit assessment determines which HEMT device is the weakest amongst the LNA circuit. Since many of the known III-V semiconductor failure mechanisms physically degrade or damage HEMTs, cross-sections are important to prepare to detect these mechanisms. In this presentation, advanced microscopy techniques with sub-nanometer resolutions, will examine physical characteristics of the HEMT at the atomic scale. The microscopy techniques will include a Focused Ion Beam/Scanning Electron Microscope (FIB/SEM), Nanomill and a Transmission Electron Microscope (TEM) along with Energy Dispersive Spectroscopy (EDS).","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129701895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0040
Yong Guo, Jason D. Jones, Yanan Guo, J. Hurst, Jinyoung Lee, Stuart Son
The effect of copper (Cu) contamination inside the Si substrate from the wafer edge to the nearby devices has been investigated. After the Cu seed layer deposition, Cu contacted directly with Si at wafer edge where dielectric isolation layer was removed. Under the routine BEOL metallization and after the capping SiON/Si2O layers, SEM and AES analysis located a strip of islets of Cu contaminants. TEM analysis revealed that the seed Cu had interacted with Si substrate to form a stable ?-Cu3Si intermetallic compound that appeared to be planted into the Si substrate at the surface. SIMS analysis from the wafer backside, opposite to this strip of ?-Cu3Si islets at front, showed no Cu detection even after the majority of the backside Si was removed by grinding. Electrical nano-probing did not discern any parametric drift for the nanometer FinFET devices on chips near the edge surface of massive ?-Cu3Si islets in comparison with a reference chip from an uncontaminated wafer center. These results indicate that the formation of ?-Cu3Si, with a well-defined crystalline structure and a relatively stable stoichiometry, immobilizes Cu diffusion inside the Si substrate. In other word, the impact of Cu diffusion in Si has no effect on device performances as long as ?-Cu3Si is not directly formed in the FinFET channel or presents to short any structures within the chip.
{"title":"The Effect of Wafer Edge Cu Contamination on FinFET Devices","authors":"Yong Guo, Jason D. Jones, Yanan Guo, J. Hurst, Jinyoung Lee, Stuart Son","doi":"10.31399/asm.cp.istfa2021p0040","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0040","url":null,"abstract":"\u0000 The effect of copper (Cu) contamination inside the Si substrate from the wafer edge to the nearby devices has been investigated. After the Cu seed layer deposition, Cu contacted directly with Si at wafer edge where dielectric isolation layer was removed. Under the routine BEOL metallization and after the capping SiON/Si2O layers, SEM and AES analysis located a strip of islets of Cu contaminants. TEM analysis revealed that the seed Cu had interacted with Si substrate to form a stable ?-Cu3Si intermetallic compound that appeared to be planted into the Si substrate at the surface. SIMS analysis from the wafer backside, opposite to this strip of ?-Cu3Si islets at front, showed no Cu detection even after the majority of the backside Si was removed by grinding. Electrical nano-probing did not discern any parametric drift for the nanometer FinFET devices on chips near the edge surface of massive ?-Cu3Si islets in comparison with a reference chip from an uncontaminated wafer center. These results indicate that the formation of ?-Cu3Si, with a well-defined crystalline structure and a relatively stable stoichiometry, immobilizes Cu diffusion inside the Si substrate. In other word, the impact of Cu diffusion in Si has no effect on device performances as long as ?-Cu3Si is not directly formed in the FinFET channel or presents to short any structures within the chip.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130228290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0446
K. Jacobs, A. Jourdain, I. De Wolf, E. Beyne
We report optical and electron beam-based fault isolation approaches for short and open defects in nanometer scale through silicon via (TSV) interconnects (180×250 nm, 500 nm height). Short defects are localized by photon emission microscopy (PEM) and optical beam-induced current (OBIC) techniques, and open defects are isolated by active voltage contrast imaging in the scanning electron microscope (SEM). We confirm our results by transmission electron microscopy (TEM) based cross sectioning.
{"title":"Fault Isolation Approaches for Nanoscale TSV Interconnects in 3D Heterogenous Integration","authors":"K. Jacobs, A. Jourdain, I. De Wolf, E. Beyne","doi":"10.31399/asm.cp.istfa2021p0446","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0446","url":null,"abstract":"\u0000 We report optical and electron beam-based fault isolation approaches for short and open defects in nanometer scale through silicon via (TSV) interconnects (180×250 nm, 500 nm height). Short defects are localized by photon emission microscopy (PEM) and optical beam-induced current (OBIC) techniques, and open defects are isolated by active voltage contrast imaging in the scanning electron microscope (SEM). We confirm our results by transmission electron microscopy (TEM) based cross sectioning.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128819355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0337
Sean Morgan-Jones, P. Carleson, M. Najarian, Gavin Mitchson, N. Franco, Sophia Weeks, Suri Mandala
The development of advanced logic processing technologies has hit a critical slowing period over the past 10 years. Long gone are the booming days of exponential growth seen in chip transistor density as described by Moore's Law back in 1965.[1] With modern logic manufacturers now capable of creating transistors in the 5-7 nm node range, having the ability to isolate, inspect, and probe individual metal and via layers is of utmost importance for defect inspection and design validation. In this realm of failure analysis, it is critical that design manufacturers possess the ability to isolate any given single layer of their logic samples. These isolated layers can be inspected for defects via SEM, provide validation of CAD designs, or tested with electrical probing for failure analysis. The work here-in describes a functional workflow that enables manufacturers to perform this kind of sample preparation in an automated fashion using the Thermo Scientific™ Helios™ G5 PFIB platform. This workflow can be utilized by both the Thermo Scientific Full Wafer and Small Dual Beam PFIB platforms to streamline sample analysis and failure testing in both the lab and fabrication environments.
{"title":"Enabling Automated Sample Delayering, Imaging, and Probing Prep with an Adaptive Endpointing Workflow","authors":"Sean Morgan-Jones, P. Carleson, M. Najarian, Gavin Mitchson, N. Franco, Sophia Weeks, Suri Mandala","doi":"10.31399/asm.cp.istfa2021p0337","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0337","url":null,"abstract":"\u0000 The development of advanced logic processing technologies has hit a critical slowing period over the past 10 years. Long gone are the booming days of exponential growth seen in chip transistor density as described by Moore's Law back in 1965.[1] With modern logic manufacturers now capable of creating transistors in the 5-7 nm node range, having the ability to isolate, inspect, and probe individual metal and via layers is of utmost importance for defect inspection and design validation. In this realm of failure analysis, it is critical that design manufacturers possess the ability to isolate any given single layer of their logic samples. These isolated layers can be inspected for defects via SEM, provide validation of CAD designs, or tested with electrical probing for failure analysis. The work here-in describes a functional workflow that enables manufacturers to perform this kind of sample preparation in an automated fashion using the Thermo Scientific™ Helios™ G5 PFIB platform. This workflow can be utilized by both the Thermo Scientific Full Wafer and Small Dual Beam PFIB platforms to streamline sample analysis and failure testing in both the lab and fabrication environments.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125187652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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