Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0403
Lindarti Purwaningsih, Philipp Konsulke, Markus Tonhaeuser, H. Jantoljak
Defect detection and defect control are crucial for yield improvement in semiconductor industry. A discrepancy between detected defects compared to yield data regarding a common defect type was found. Historical data show a different behavior was seen on different product groups. A product design analysis on affected layer shows a striking difference in the Terminal Metal Layer (TML) line orientation between those product groups. A particle deposition system was used to distribute a fixed number of PSL spheres on to wafers prior etch process and defect inspections with different wafer notch orientations were performed at the final step. Those deposited PSL spheres prior etch process resulted in extra pattern defects at the inspection step. Extra pattern defects were mostly detected using a certain wafer notch orientation recipe to the majority of TML line orientation compared to the other one. This case study discusses the influence of a defect inspection wafer notch orientation to the defect capture rate on TML layer. Based on this result, the industry should consider the majority line orientation of respective layer on each inspection step when creating a new defect scanning recipe, especially for TML layer.
{"title":"Defect Inspection Wafer Notch Orientation and Defect Detection Dependency","authors":"Lindarti Purwaningsih, Philipp Konsulke, Markus Tonhaeuser, H. Jantoljak","doi":"10.31399/asm.cp.istfa2021p0403","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0403","url":null,"abstract":"\u0000 Defect detection and defect control are crucial for yield improvement in semiconductor industry. A discrepancy between detected defects compared to yield data regarding a common defect type was found. Historical data show a different behavior was seen on different product groups. A product design analysis on affected layer shows a striking difference in the Terminal Metal Layer (TML) line orientation between those product groups. A particle deposition system was used to distribute a fixed number of PSL spheres on to wafers prior etch process and defect inspections with different wafer notch orientations were performed at the final step. Those deposited PSL spheres prior etch process resulted in extra pattern defects at the inspection step. Extra pattern defects were mostly detected using a certain wafer notch orientation recipe to the majority of TML line orientation compared to the other one. This case study discusses the influence of a defect inspection wafer notch orientation to the defect capture rate on TML layer. Based on this result, the industry should consider the majority line orientation of respective layer on each inspection step when creating a new defect scanning recipe, especially for TML layer.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123002410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0053
Kevin A. Distelhurst, Dan Bader
Analog components are still an important aspect of our society's electronic portfolio. They play a role in the emerging and expanding 5G electronic industry, for instance. The NPN bipolar junction transistor (BJT) is the foundation of many analog circuits and has continually evolved to meet more demanding specifications [1], [2]. Certain embodiments of these NPNs pose difficulties in failure analysis. One such embodiment is a vertical NPN BJT with high aspect ratio dimensions. Specifically, the dimensions involved are nanometer thick NP & PN junctions that extend microns in length. These dimensions provide desired performance improvements but a subtle, nanometer scale defect present anywhere along this length can cause substantial electrical shifts detrimental to an analog circuit. Several simple and complex techniques using common failure analysis tools can isolate these defects as discussed in this paper.
{"title":"High Aspect Ratio, Vertical Bipolar Junction Transistor NPN Device Fault Isolation & Analysis Techniques","authors":"Kevin A. Distelhurst, Dan Bader","doi":"10.31399/asm.cp.istfa2021p0053","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0053","url":null,"abstract":"\u0000 Analog components are still an important aspect of our society's electronic portfolio. They play a role in the emerging and expanding 5G electronic industry, for instance. The NPN bipolar junction transistor (BJT) is the foundation of many analog circuits and has continually evolved to meet more demanding specifications [1], [2]. Certain embodiments of these NPNs pose difficulties in failure analysis. One such embodiment is a vertical NPN BJT with high aspect ratio dimensions. Specifically, the dimensions involved are nanometer thick NP & PN junctions that extend microns in length. These dimensions provide desired performance improvements but a subtle, nanometer scale defect present anywhere along this length can cause substantial electrical shifts detrimental to an analog circuit. Several simple and complex techniques using common failure analysis tools can isolate these defects as discussed in this paper.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129068994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0135
C. Bonifacio, P. Nowakowski, R. Li, M. Ray, P. Fischione
With the introduction of new materials, new device structures, and shrinking device dimensions, failure mechanisms evolve, which can make identifying defects challenging. Therefore, an accurate and controllable delayering process to target defects is desirable. We present a workflow comprised of bulk device delayering by broad Ar ion beam milling, plan view specimen preparation by focused ion beam tool, followed by site-specific delayering by concentrated Ar ion beam milling. The result is an accurately delayered device, without sample preparation-induced artifacts, that is suitable for uncovering defects during physical failure analysis.
{"title":"Accurate Sub-micron Device Delayering of Plan View TEM Specimens By Ar Ion Milling","authors":"C. Bonifacio, P. Nowakowski, R. Li, M. Ray, P. Fischione","doi":"10.31399/asm.cp.istfa2021p0135","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0135","url":null,"abstract":"With the introduction of new materials, new device structures, and shrinking device dimensions, failure mechanisms evolve, which can make identifying defects challenging. Therefore, an accurate and controllable delayering process to target defects is desirable. We present a workflow comprised of bulk device delayering by broad Ar ion beam milling, plan view specimen preparation by focused ion beam tool, followed by site-specific delayering by concentrated Ar ion beam milling. The result is an accurately delayered device, without sample preparation-induced artifacts, that is suitable for uncovering defects during physical failure analysis.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"322 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125836969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0248
Chuan Zhang, Jane Y. Li, John Aguada, H. Marks
This paper introduced a novel defect localization approach by performing EBIRCH isolation from backside of flip-chips. Sample preparation and probing consideration was discussed, and then a case study was used to illustrate how the backside EBIRCH technique provides a powerful solution in capturing and root-causing subtle defects in challenging flip-chip failures.
{"title":"Backside EBIRCH Defect Localization for Advanced Flip-Chip Failure Analysis","authors":"Chuan Zhang, Jane Y. Li, John Aguada, H. Marks","doi":"10.31399/asm.cp.istfa2021p0248","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0248","url":null,"abstract":"\u0000 This paper introduced a novel defect localization approach by performing EBIRCH isolation from backside of flip-chips. Sample preparation and probing consideration was discussed, and then a case study was used to illustrate how the backside EBIRCH technique provides a powerful solution in capturing and root-causing subtle defects in challenging flip-chip failures.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126164365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0441
K. Yamasue, Yasuo Cho
We investigate non-uniformity at SiO2/SiC interfaces by time-resolved scanning nonlinear dielectric microscopy, which permits the simultaneous nanoscale imaging of interface defect density (Dit) and differential capacitance (dC/dV) at insulator-semiconductor interfaces. Here we perform the cross correlation analysis of the images with spatially non-uniform clustering distributions reported previously. We show that Dit images are not correlated with the simultaneous dC/dV images significantly but with the difference image between the two dC/dV images taken with different voltage sweep directions. The results indicate that the dC/dV images visualize the non-uniformity of the total interface charge density and the difference images reflect that of Dit at a particular energy range.
{"title":"Simultaneous Interface Defect Density and Differential Capacitance Imaging by Time-Resolved Scanning Nonlinear Dielectric Microscopy","authors":"K. Yamasue, Yasuo Cho","doi":"10.31399/asm.cp.istfa2021p0441","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0441","url":null,"abstract":"\u0000 We investigate non-uniformity at SiO2/SiC interfaces by time-resolved scanning nonlinear dielectric microscopy, which permits the simultaneous nanoscale imaging of interface defect density (Dit) and differential capacitance (dC/dV) at insulator-semiconductor interfaces. Here we perform the cross correlation analysis of the images with spatially non-uniform clustering distributions reported previously. We show that Dit images are not correlated with the simultaneous dC/dV images significantly but with the difference image between the two dC/dV images taken with different voltage sweep directions. The results indicate that the dC/dV images visualize the non-uniformity of the total interface charge density and the difference images reflect that of Dit at a particular energy range.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114970368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：