Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0406
Jeongin Choe, Taehyeon Kim, Saetbyeol Yoon, Sangyong Yoon, Ki-Whan Song, J. Song, Myungsuk Kim, Woo Young Choi
We have adopted various defect detection systems in the front stage of manufacturing in order to effectively manage the quality of flash memory products. In this paper, we propose an intelligent pattern recognition methodology which enables us to discriminate abnormal wafer automatically in the course of NAND flash memory manufacturing. Our proposed technique consists of the two steps: pre-processing and hybrid clustering. The pre-processing step based on process primitives efficiently eliminates noisy data. Then, the hybrid clustering step dramatically reduces the total amount of computing, which makes our technique practical for the mass production of NAND flash memory.
{"title":"Wafer Pattern Recognition for Detecting Process Abnormalities in NAND Flash Memory Manufacturing","authors":"Jeongin Choe, Taehyeon Kim, Saetbyeol Yoon, Sangyong Yoon, Ki-Whan Song, J. Song, Myungsuk Kim, Woo Young Choi","doi":"10.31399/asm.cp.istfa2021p0406","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0406","url":null,"abstract":"\u0000 We have adopted various defect detection systems in the front stage of manufacturing in order to effectively manage the quality of flash memory products. In this paper, we propose an intelligent pattern recognition methodology which enables us to discriminate abnormal wafer automatically in the course of NAND flash memory manufacturing. Our proposed technique consists of the two steps: pre-processing and hybrid clustering. The pre-processing step based on process primitives efficiently eliminates noisy data. Then, the hybrid clustering step dramatically reduces the total amount of computing, which makes our technique practical for the mass production of NAND flash memory.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126256035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0084
A. Norico, Rommel Estores
Temperature dependent failures are some of the most challenging cases that will be encountered by the analyst. Soft Defect Localization (SDL) is a technique used to analyze such temperature-dependent, ‘soft defect’ failures [1]. There are many literatures that discuss this technique and its different applications [2-7]. Dynamic Analysis by Laser Stimulation (DALS) is one of the known SDL implementations [8-11]. However, there are cases where the failure is occurring at a temperature where the laser alone is not sufficient to effectively induce a change of device behavior. In these situations, the analyst needs to think out of the box by understanding how the device will react to external conditions and to make necessary adjustments in DALS settings. This paper will discuss three cases that presents different challenges such as performing DALS analysis where the failing temperature is too high for the laser to induce a change of behavior from ambient temperature, cold temperature failure, complex triggering (Serial Peripheral Interface, SPI), and using an internal signal as input for DALS analysis. The approach used for a successful DALS analysis of each case will be discussed in detail.
{"title":"Pushing Failure Mode Stimulus to Overcome the Limitation/Boundaries of Soft Defect Localization Tools","authors":"A. Norico, Rommel Estores","doi":"10.31399/asm.cp.istfa2021p0084","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0084","url":null,"abstract":"\u0000 Temperature dependent failures are some of the most challenging cases that will be encountered by the analyst. Soft Defect Localization (SDL) is a technique used to analyze such temperature-dependent, ‘soft defect’ failures [1]. There are many literatures that discuss this technique and its different applications [2-7]. Dynamic Analysis by Laser Stimulation (DALS) is one of the known SDL implementations [8-11]. However, there are cases where the failure is occurring at a temperature where the laser alone is not sufficient to effectively induce a change of device behavior. In these situations, the analyst needs to think out of the box by understanding how the device will react to external conditions and to make necessary adjustments in DALS settings. This paper will discuss three cases that presents different challenges such as performing DALS analysis where the failing temperature is too high for the laser to induce a change of behavior from ambient temperature, cold temperature failure, complex triggering (Serial Peripheral Interface, SPI), and using an internal signal as input for DALS analysis. The approach used for a successful DALS analysis of each case will be discussed in detail.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128771814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0359
Seungjun Son, C. Penley, J. Hurst, Chris Michon, Yong Guo, Rafael Lainez, J. Reifsnider
For a specific IDDQ failure only around SRAM cell boundary, we conducted a systematic investigation in the lab involving electrical, physical, and chemical analysis. Following electrical test locating the failure area according to PEM (photon emission microscopy) and physical defect analysis resulting in NDF (no defect found), we explored an alternative method to define the failure. In this paper, we demonstrated the success of using tunneling AFM (TUNA) in diagnosing such an IDDQ failure occurring in FinFET devices. AFM (TUNA) analysis was able to visualize clearly the dopant discrepancies in comparison between the IDDQ fail and pass references in FinFET transistors. The dopant abnormalities indicated the current IDDQ fail was caused by processes that impaired the dopant implantation.
{"title":"Non-Visual Defect Identification by Dopant Analysis Method in FinFET Devices","authors":"Seungjun Son, C. Penley, J. Hurst, Chris Michon, Yong Guo, Rafael Lainez, J. Reifsnider","doi":"10.31399/asm.cp.istfa2021p0359","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0359","url":null,"abstract":"\u0000 For a specific IDDQ failure only around SRAM cell boundary, we conducted a systematic investigation in the lab involving electrical, physical, and chemical analysis. Following electrical test locating the failure area according to PEM (photon emission microscopy) and physical defect analysis resulting in NDF (no defect found), we explored an alternative method to define the failure. In this paper, we demonstrated the success of using tunneling AFM (TUNA) in diagnosing such an IDDQ failure occurring in FinFET devices. AFM (TUNA) analysis was able to visualize clearly the dopant discrepancies in comparison between the IDDQ fail and pass references in FinFET transistors. The dopant abnormalities indicated the current IDDQ fail was caused by processes that impaired the dopant implantation.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"71 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132693483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0301
Kuang-Tse Ho, Cheng-Che Li
This research summarizes failure analysis results about ionimplantation related issues in Si-based power devices, including diode, MOSFET and IGBT. To find out this kind of defects, sample preparation, fault isolation and SCM inspection are critical steps, which will be explained in detail in this paper.
{"title":"SCM Application and Failure Analysis Procedure for Ion-Implantation Issues in Power Devices","authors":"Kuang-Tse Ho, Cheng-Che Li","doi":"10.31399/asm.cp.istfa2021p0301","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0301","url":null,"abstract":"\u0000 This research summarizes failure analysis results about ionimplantation related issues in Si-based power devices, including diode, MOSFET and IGBT. To find out this kind of defects, sample preparation, fault isolation and SCM inspection are critical steps, which will be explained in detail in this paper.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113997210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0115
F. Stellari, E. Wu, T. Ando, M. Frank, P. Song
In this paper, we discuss the use of spontaneous Photon Emission Microscopy (PEM) for observing filaments formed in HfO2 Resistive Random Access Memory (ReRAM) cells. A CCD and an InGaAs camera can be used to quickly observe photon emission in both reverse (reset) and forward (set) bias conditions. An electric field model and a uniform Poisson spatial distribution model are used to explain the intensity and location of the experimental data. Single filament fluctuations and multiple filaments are also observed for the first time.
{"title":"Photon Emission Microscopy of HfO2 ReRAM Cells","authors":"F. Stellari, E. Wu, T. Ando, M. Frank, P. Song","doi":"10.31399/asm.cp.istfa2021p0115","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0115","url":null,"abstract":"\u0000 In this paper, we discuss the use of spontaneous Photon Emission Microscopy (PEM) for observing filaments formed in HfO2 Resistive Random Access Memory (ReRAM) cells. A CCD and an InGaAs camera can be used to quickly observe photon emission in both reverse (reset) and forward (set) bias conditions. An electric field model and a uniform Poisson spatial distribution model are used to explain the intensity and location of the experimental data. Single filament fluctuations and multiple filaments are also observed for the first time.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121415584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0263
Jeongwon Bae, Minjoo Kim, Jongbum Lee, Myunghoon Oak, Choongsun Park, Sunghun Park, Sungsoo Yim, Hee-Il Hong, Jooyoung Lee
In semiconductor manufacturing or testing, when changing the items such as parts, materials or equipment, many engineers use the equivalence test to hedge the risk of new process. Equivalence Test Procedure (ETP) uses a modified algorithm of Cohen's d and F-ratio for comparing two test samples when it evaluates the statistical allowance in the second stage. These logics are estimated under the assumption of normality for the underlying population. However, there are many wafer level test items such as Fail Bit Count (FBC) where their populations are non-normal distribution. Because the standard deviation in the two algorithms is over-estimated in wafer level test distribution, the two algorithms fail to represent the size of difference for the two samples exactly. Therefore, we introduce quantile comparison equivalence criteria (QCEC) which is robust to overall data distribution and outlier-free. To instruct engineers about the change cause of the data distribution, we create new statistics called ‘Center or Dispersion’ (CoD) that distinguish between center difference and dispersion difference. For practical application, we conduct the case study on Dynamic Random Access Memory (DRAM) FBC data. For wafer level test 199 items, it is found that the QCEC's accuracy improves by 20% compared to the accuracy of Cohen's d. It also shows a 75% improvement over the accuracy of the F-ratio.
{"title":"Quantile Based Statistical Failure Analysis for Wafer Level Test Comparison","authors":"Jeongwon Bae, Minjoo Kim, Jongbum Lee, Myunghoon Oak, Choongsun Park, Sunghun Park, Sungsoo Yim, Hee-Il Hong, Jooyoung Lee","doi":"10.31399/asm.cp.istfa2021p0263","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0263","url":null,"abstract":"\u0000 In semiconductor manufacturing or testing, when changing the items such as parts, materials or equipment, many engineers use the equivalence test to hedge the risk of new process. Equivalence Test Procedure (ETP) uses a modified algorithm of Cohen's d and F-ratio for comparing two test samples when it evaluates the statistical allowance in the second stage. These logics are estimated under the assumption of normality for the underlying population. However, there are many wafer level test items such as Fail Bit Count (FBC) where their populations are non-normal distribution. Because the standard deviation in the two algorithms is over-estimated in wafer level test distribution, the two algorithms fail to represent the size of difference for the two samples exactly. Therefore, we introduce quantile comparison equivalence criteria (QCEC) which is robust to overall data distribution and outlier-free. To instruct engineers about the change cause of the data distribution, we create new statistics called ‘Center or Dispersion’ (CoD) that distinguish between center difference and dispersion difference. For practical application, we conduct the case study on Dynamic Random Access Memory (DRAM) FBC data. For wafer level test 199 items, it is found that the QCEC's accuracy improves by 20% compared to the accuracy of Cohen's d. It also shows a 75% improvement over the accuracy of the F-ratio.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127526012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0203
D. Fishmana, L. Neemana, N. Meira, Y. Orena, G. Baraka, A. Avidana, J. Ofeka
As semiconductor device dimensions scale down, process variation impact on reliability becomes increasingly severe. This trend stems from the high-reliability requirements typical for advanced system applications, the narrowing process margins and the high sensitivity of devices to material and dimensional variations. At the process level, many deviations from nominal conditions can degrade the devices' reliability. Examples are induced charge traps in the various types of memory cells, electrical performance inhibitors due to lattice defects or poor stress management and poor data retention due to contamination by killer elements. We claim that monitoring and correcting deviations throughout the fabrication process provides an effective approach for preventing reliability failures. By restricting deviations below specific threshold levels and screening out reliability and End Of line (EOL) related parameters, eventual device reliability can be safeguarded. This paper addresses the relationship between various process parameters and reliability, and reviews the enablers of preventive, early-detection inline metrology in the fab.
随着半导体器件尺寸的缩小，工艺变化对可靠性的影响日益严重。这一趋势源于先进系统应用的高可靠性要求，工艺边际的缩小以及设备对材料和尺寸变化的高灵敏度。在工艺层面，许多偏离标称条件会降低器件的可靠性。例如，各种类型的存储单元中的诱导电荷陷阱，由于晶格缺陷或应力管理不良而导致的电性能抑制，以及由于杀手元素污染而导致的数据保留不良。我们声称在整个制造过程中监测和纠正偏差为防止可靠性故障提供了有效的方法。通过限制偏差低于特定阈值水平，筛选可靠性和EOL (End Of line)相关参数，可以保障最终的设备可靠性。本文讨论了各种工艺参数与可靠性之间的关系，并回顾了fab中预防性、早期检测在线计量的实现因素。
{"title":"Early Fault-Analysis Using In-Line Raman Spectroscopy Metrology","authors":"D. Fishmana, L. Neemana, N. Meira, Y. Orena, G. Baraka, A. Avidana, J. Ofeka","doi":"10.31399/asm.cp.istfa2021p0203","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0203","url":null,"abstract":"\u0000 As semiconductor device dimensions scale down, process variation impact on reliability becomes increasingly severe. This trend stems from the high-reliability requirements typical for advanced system applications, the narrowing process margins and the high sensitivity of devices to material and dimensional variations. At the process level, many deviations from nominal conditions can degrade the devices' reliability. Examples are induced charge traps in the various types of memory cells, electrical performance inhibitors due to lattice defects or poor stress management and poor data retention due to contamination by killer elements.\u0000 We claim that monitoring and correcting deviations throughout the fabrication process provides an effective approach for preventing reliability failures. By restricting deviations below specific threshold levels and screening out reliability and End Of line (EOL) related parameters, eventual device reliability can be safeguarded. This paper addresses the relationship between various process parameters and reliability, and reviews the enablers of preventive, early-detection inline metrology in the fab.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125445174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0130
V. Dixit, B. Gauntt, Taehun Lee
The automation of both, transmission electron microscopy (TEM) imaging and lamella preparation using focused ion beam (FIB) has gathered an enormous momentum in last few years, especially in the semiconductor industry. The process development of current and future microprocessors requires a precise control on the patterning of a multitude of ultrafine layers, several of which are in the order of nanometers. The statistical accuracy and reliability of TEM based metrology and failure analysis of such complex and refined structures across the wafer needs a large-scale sampling, which is feasible only with an automation. An inherent requirement of automating TEM sample preparation entails a need of a robust and repeatable methodology that provides both, a good thickness control and an accurate targeting, on the intended feature in the ultra-thin lamella. In this work, key factors that impact both these aspects of a TEM lamella preparation will be discussed. In addition, steps needed to ensure that FIB toolsets consistently and reliably produce high quality samples, will be highlighted.
{"title":"Thickness Control and Targeting in Large Scale Automated XTEM Lamella Preparation","authors":"V. Dixit, B. Gauntt, Taehun Lee","doi":"10.31399/asm.cp.istfa2021p0130","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0130","url":null,"abstract":"\u0000 The automation of both, transmission electron microscopy (TEM) imaging and lamella preparation using focused ion beam (FIB) has gathered an enormous momentum in last few years, especially in the semiconductor industry. The process development of current and future microprocessors requires a precise control on the patterning of a multitude of ultrafine layers, several of which are in the order of nanometers. The statistical accuracy and reliability of TEM based metrology and failure analysis of such complex and refined structures across the wafer needs a large-scale sampling, which is feasible only with an automation. An inherent requirement of automating TEM sample preparation entails a need of a robust and repeatable methodology that provides both, a good thickness control and an accurate targeting, on the intended feature in the ultra-thin lamella. In this work, key factors that impact both these aspects of a TEM lamella preparation will be discussed. In addition, steps needed to ensure that FIB toolsets consistently and reliably produce high quality samples, will be highlighted.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126232107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The 3D NAND sample with high aspect ratio (HAR) etched by plasma was investigated. By controlling the plasma etching parameters, a relatively high etch rate could be obtained. Moreover, with appropriately controlling the etch time, we could etch top region of HAR sample with expected number of layers, which could help us to completely analyze the high aspect ratio sample with TEM cross-section analysis, especially for the middle region of 3D NAND.
{"title":"Plasma Etching Pre-treatment for a TEM Lamella Preparation of 3D NAND with High Aspect Ratio","authors":"Yu-Chi Chen, Bing-Chang Li, Pei-Ling Hsu, Tsung-Yi Lin, I-An Chen, Chun-Hung Lin, Hsin-Cheng Hsu, C. Yeh, N. Lian, Ta-Hone Yang, Kuang-Chao Chen","doi":"10.31399/asm.cp.istfa2021p0141","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0141","url":null,"abstract":"\u0000 The 3D NAND sample with high aspect ratio (HAR) etched by plasma was investigated. By controlling the plasma etching parameters, a relatively high etch rate could be obtained. Moreover, with appropriately controlling the etch time, we could etch top region of HAR sample with expected number of layers, which could help us to completely analyze the high aspect ratio sample with TEM cross-section analysis, especially for the middle region of 3D NAND.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125751626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0342
M. Najarian
Manufacturers of the emerging 3D NAND market are working to continually add more memory capacity by increasing the number of layers in the device stacks. As the device stacks get taller, the manufacturers face many challenges for creating the devices with very high aspect ratios (HAR)1 such as those shown in Figure 1. In order to monitor and improve the processes, metrology information is required for 3D analysis of critical dimensions and tilt/shift relative positions of the channels through the device height2.
{"title":"Workflow Solution for Positional Characterization of 3D NAND Channel Tilt/Shift","authors":"M. Najarian","doi":"10.31399/asm.cp.istfa2021p0342","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0342","url":null,"abstract":"\u0000 Manufacturers of the emerging 3D NAND market are working to continually add more memory capacity by increasing the number of layers in the device stacks. As the device stacks get taller, the manufacturers face many challenges for creating the devices with very high aspect ratios (HAR)1 such as those shown in Figure 1. In order to monitor and improve the processes, metrology information is required for 3D analysis of critical dimensions and tilt/shift relative positions of the channels through the device height2.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134595345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：