Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457883
J. Pak, Jonghyun Cho, Joohee Kim, Heegon Kim, Kiyeong Kim, Joungho Kim, Junho Lee, Kunwoo Park
This paper presents the wafer-lvel TSV connectivity test method using ring oscillator scheme by showing its good immunity to TSV and chip process variations, efficient use of a chip area, simplicity of the test circuitry design, and low cost from its application before expensive wafer thinning and stacking processes. The proposed method can detect a delamination failure between TSVs and back end lines on a single TSV processed wafer.
{"title":"Wafer-level TSV connectivity test using ring oscillator scheme","authors":"J. Pak, Jonghyun Cho, Joohee Kim, Heegon Kim, Kiyeong Kim, Joungho Kim, Junho Lee, Kunwoo Park","doi":"10.1109/EPEPS.2012.6457883","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457883","url":null,"abstract":"This paper presents the wafer-lvel TSV connectivity test method using ring oscillator scheme by showing its good immunity to TSV and chip process variations, efficient use of a chip area, simplicity of the test circuitry design, and low cost from its application before expensive wafer thinning and stacking processes. The proposed method can detect a delamination failure between TSVs and back end lines on a single TSV processed wafer.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130408586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457855
F. Broydé, E. Clavelier, D. De Zutter, D. Ginste
An analytical model for the per-unit-length impedance matrix of a multiconductor interconnection has recently been introduced and shown to be physically reasonable. The present discussion addresses the determination of the model parameters and the model accuracy.
{"title":"A discussion of an analytical per-unit-length impedance matrix model","authors":"F. Broydé, E. Clavelier, D. De Zutter, D. Ginste","doi":"10.1109/EPEPS.2012.6457855","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457855","url":null,"abstract":"An analytical model for the per-unit-length impedance matrix of a multiconductor interconnection has recently been introduced and shown to be physically reasonable. The present discussion addresses the determination of the model parameters and the model accuracy.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130621660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457858
B. Young
Current mirrors are an established technique for reducing memory requirements and run time in Spice-based bus simulations with many simultaneously switching outputs (SSO). Mismatched delayss can reduce accuracy, and a current mirror bus architecture enhanced with a bridge circuit is shown to restore accuracy with mismatched package delays.
{"title":"An enhanced current mirror for SSO simulation","authors":"B. Young","doi":"10.1109/EPEPS.2012.6457858","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457858","url":null,"abstract":"Current mirrors are an established technique for reducing memory requirements and run time in Spice-based bus simulations with many simultaneously switching outputs (SSO). Mismatched delayss can reduce accuracy, and a current mirror bus architecture enhanced with a bridge circuit is shown to restore accuracy with mismatched package delays.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"20 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133471015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457838
S. Mukherjee, D. Oh, A. Vaidyanath, D. Dressler, A. Sendhil
While the need for higher graphics memory bandwidth continues to grow, it is evident that owing to the multitude of challenges in single ended signaling, pushing data rates beyond 6 Gbps is exceedingly difficult. To isolate, quantify and combat the most important factors that limit the performance of modern high speed single ended systems, a high speed GDDR5 memory system (link width: ×32) has been designed using a Rambus prototype test-chip (TSMC 40 nm process node) and a leading single ended signaling graphics GDDR5 DRAM. Critical challenges faced in scaling the data rates up to 8 Gbps are presented and the varying impact of these challenges on the system margin is shown for increasing speeds. An example of a chip-to-chip system between two prototype test chips, that mitigates these performance limiting determinants, is shown to operate robustly at data rates beyond 8 Gbps. The ingredients of this system are likely techniques for the future graphics memories.
{"title":"Challenges in extending single-ended graphics memory data rates","authors":"S. Mukherjee, D. Oh, A. Vaidyanath, D. Dressler, A. Sendhil","doi":"10.1109/EPEPS.2012.6457838","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457838","url":null,"abstract":"While the need for higher graphics memory bandwidth continues to grow, it is evident that owing to the multitude of challenges in single ended signaling, pushing data rates beyond 6 Gbps is exceedingly difficult. To isolate, quantify and combat the most important factors that limit the performance of modern high speed single ended systems, a high speed GDDR5 memory system (link width: ×32) has been designed using a Rambus prototype test-chip (TSMC 40 nm process node) and a leading single ended signaling graphics GDDR5 DRAM. Critical challenges faced in scaling the data rates up to 8 Gbps are presented and the varying impact of these challenges on the system margin is shown for increasing speeds. An example of a chip-to-chip system between two prototype test chips, that mitigates these performance limiting determinants, is shown to operate robustly at data rates beyond 8 Gbps. The ingredients of this system are likely techniques for the future graphics memories.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124311892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457907
D. Dreps, L. Daniels, R. Mandrekar, N. Pham, L. Shan
This paper outlines when designing a front side bus that is source synchronous the clock needs special consideration. If the clock is treated the same as data bit the bus performance or bit rate can be limited by the clock distortion effects. Investigations of the components of the distortion are described along with prevention rules and silicon architecture impacts.
{"title":"Findings and considerations for I/O clock jitter on a source synchronous front side bus","authors":"D. Dreps, L. Daniels, R. Mandrekar, N. Pham, L. Shan","doi":"10.1109/EPEPS.2012.6457907","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457907","url":null,"abstract":"This paper outlines when designing a front side bus that is source synchronous the clock needs special consideration. If the clock is treated the same as data bit the bus performance or bit rate can be limited by the clock distortion effects. Investigations of the components of the distortion are described along with prevention rules and silicon architecture impacts.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128483231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457844
Paolo Manfredi, D. Ginste, D. Zutter, F. Canavero
This paper presents an improvement of the state-of-the-art polynomial chaos (PC) modeling of high-speed interconnects with parameter uncertainties via SPICE-like tools. While the previous model, due to its mathematical formulation, was limited to lossless lines, the introduction of modified classes of polynomials yields a formulation that allows to account for lossess and dispersion as well. Thanks to this, the new implementation can also take full advantage of the combination of the PC technique with macromodels that accurately describe the interconnect properties. An application example, i.e. the stochastic analysis of an on-chip line, validates and demonstrates the improved method.
{"title":"Frequency- and time-domain stochastic analysis of lossy and dispersive interconnects in a SPICE-like environment","authors":"Paolo Manfredi, D. Ginste, D. Zutter, F. Canavero","doi":"10.1109/EPEPS.2012.6457844","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457844","url":null,"abstract":"This paper presents an improvement of the state-of-the-art polynomial chaos (PC) modeling of high-speed interconnects with parameter uncertainties via SPICE-like tools. While the previous model, due to its mathematical formulation, was limited to lossless lines, the introduction of modified classes of polynomials yields a formulation that allows to account for lossess and dispersion as well. Thanks to this, the new implementation can also take full advantage of the combination of the PC technique with macromodels that accurately describe the interconnect properties. An application example, i.e. the stochastic analysis of an on-chip line, validates and demonstrates the improved method.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125281964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457891
Arghya Sain, K. Melde
This paper presents a way to include the effects of conductor surface roughness in three-dimensional full wave simulation tools. A comparison of the computational load and attenuation coefficient as a function of the number and area of different surfaces roughened is given.
{"title":"Characterizing the impact of conductor surface roughness on CB-CPW behavior via reduced computational complexity","authors":"Arghya Sain, K. Melde","doi":"10.1109/EPEPS.2012.6457891","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457891","url":null,"abstract":"This paper presents a way to include the effects of conductor surface roughness in three-dimensional full wave simulation tools. A comparison of the computational load and attenuation coefficient as a function of the number and area of different surfaces roughened is given.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126933818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457890
K. Yamanaga, T. Sato
Low cost board-level antiresonance control method has been proposed. In the proposed method, two capacitors having equal dimensions and capacitances with different series resistances will be used to reduce impedance peak at antireso-nance while suppressing impedance increase at low frequencies. Experimental measurements using a 180-nm CMOS test chip mounted on a PCB confirmed the effectiveness of the proposed method.
{"title":"The odd couple: Antiresonance control by two capacitors of unequal series resistances","authors":"K. Yamanaga, T. Sato","doi":"10.1109/EPEPS.2012.6457890","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457890","url":null,"abstract":"Low cost board-level antiresonance control method has been proposed. In the proposed method, two capacitors having equal dimensions and capacitances with different series resistances will be used to reduce impedance peak at antireso-nance while suppressing impedance increase at low frequencies. Experimental measurements using a 180-nm CMOS test chip mounted on a PCB confirmed the effectiveness of the proposed method.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122828590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457900
Tsui-Wei Weng, Tzong-Lin Wu
A novel wide stopband and compact bandstop filter (BSF) is proposed and realized based on defected ground structure (DGS) and meandered signal line on SiP. An equivalent circuit model is built to characterize the filter behaviors. At the same time, a condition for transmission zeros is derived. It can be observed that the equivalent circuit model reasonably agrees with the full-wave simulation and measurement results. Also, it is found that the proposed filter has high rejection over 25 dB in its stopband. The filter has a compact size of 0.21 λg × 0.19 λg, where λg is the wavelength of the center frequency of the stopband, and its -10 dB fractional bandwidth (FBW) is up to 90%.
{"title":"A novel miniaturized bandstop filter using defected ground on system in package (SiP)","authors":"Tsui-Wei Weng, Tzong-Lin Wu","doi":"10.1109/EPEPS.2012.6457900","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457900","url":null,"abstract":"A novel wide stopband and compact bandstop filter (BSF) is proposed and realized based on defected ground structure (DGS) and meandered signal line on SiP. An equivalent circuit model is built to characterize the filter behaviors. At the same time, a condition for transmission zeros is derived. It can be observed that the equivalent circuit model reasonably agrees with the full-wave simulation and measurement results. Also, it is found that the proposed filter has high rejection over 25 dB in its stopband. The filter has a compact size of 0.21 λg × 0.19 λg, where λg is the wavelength of the center frequency of the stopband, and its -10 dB fractional bandwidth (FBW) is up to 90%.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131807995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457831
W. Beyene, A. Amirkhany, K. Kaviani, A. Abbasfar
This paper introduces the design and analysis of a high-speed channel for a new signaling scheme called Coded Differential signaling. The coding scheme is designed in such a way that the parallel interface preserves many of the attractive properties of a differential link such as low supply noise generation and immunity to common-mode noise. In addition, the coding completely eliminates the first post-cursor intersymbol interference of the channel over the entire unit-interval at no loss in throughput. As a result, Coded Differential signaling leads to substantial increase in timing margin compared to a differential link with 1-tap post-cursor equalizer, consequently without the associated complexity. The design of the channel, however, requires an innovative approach to optimize the performance and cost of the system. The theory of Coded Differential signaling, the minimization of the timing skew in the channel, and the details of the implementation of a prototype system developed based on proposed scheme for graphics memory interfaces are described in this paper. On-scope measured eye diagrams indicate 30% improvement in timing margin compared to a 1-tap predictive decision feedback equalizer system.
{"title":"Design and analysis of a high-speed channel for Coded Differential signaling","authors":"W. Beyene, A. Amirkhany, K. Kaviani, A. Abbasfar","doi":"10.1109/EPEPS.2012.6457831","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457831","url":null,"abstract":"This paper introduces the design and analysis of a high-speed channel for a new signaling scheme called Coded Differential signaling. The coding scheme is designed in such a way that the parallel interface preserves many of the attractive properties of a differential link such as low supply noise generation and immunity to common-mode noise. In addition, the coding completely eliminates the first post-cursor intersymbol interference of the channel over the entire unit-interval at no loss in throughput. As a result, Coded Differential signaling leads to substantial increase in timing margin compared to a differential link with 1-tap post-cursor equalizer, consequently without the associated complexity. The design of the channel, however, requires an innovative approach to optimize the performance and cost of the system. The theory of Coded Differential signaling, the minimization of the timing skew in the channel, and the details of the implementation of a prototype system developed based on proposed scheme for graphics memory interfaces are described in this paper. On-scope measured eye diagrams indicate 30% improvement in timing margin compared to a 1-tap predictive decision feedback equalizer system.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130503368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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