Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457887
Norifumi Sasaoka, Takafumi Ochi, M. Oono, C. Ueda, Y. Akiyama, K. Otsuka
Recently, power integrity (PI) has been the most important technological issue in the field of electronic circuits and systems and has been addressed in important papers using several different approaches [1][2]. The latest concept of the best PI condition is a low impedance between the power and ground lines or planes that can be maintained regardless of the clock frequency, even in the GHz region. This concept was mentioned in a relatively old book [3] from the 1980s, so it is not the newest idea. However, this condition cannot be completely realized using several of the previously proposed approaches, including many involving the use of low-inductance capacitances. We are aware that the electromagnetic interference (EMI) problems of plane power/ground resonance are induced because of the resonance caused by eddy currents or multiple reflections of voltage fluctuations. A novel technology was used in our previous study in which a conductive layer of dispersed metal particles was used instead of a copper plane [4][5]. This structure improved the PI for any clock frequency, particularly in the GHz region, with an impedance of less than 1 Ω. In this study, we examine the electromagnetic wave transmission data in order to investigate the different physical phenomena, and we present some fundamental data on PI and signal integrity (SI). The results indicate that the use of a transmission line with a metal particle conductive layer can yield various changes in the electromagnetic wave transmission speed, such as an increase of 76% or a decrease of 21%. The Z11 values of the power/GND plane test coupon were from 1.8 to 3.0 Ω in the frequency region from 5 to 20 GHz. These results suggest that the metal particle conductive layer has useful characteristics for improving the PI and SI.
{"title":"Novel technology for power and signal integrity using a metal particle conductive layer","authors":"Norifumi Sasaoka, Takafumi Ochi, M. Oono, C. Ueda, Y. Akiyama, K. Otsuka","doi":"10.1109/EPEPS.2012.6457887","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457887","url":null,"abstract":"Recently, power integrity (PI) has been the most important technological issue in the field of electronic circuits and systems and has been addressed in important papers using several different approaches [1][2]. The latest concept of the best PI condition is a low impedance between the power and ground lines or planes that can be maintained regardless of the clock frequency, even in the GHz region. This concept was mentioned in a relatively old book [3] from the 1980s, so it is not the newest idea. However, this condition cannot be completely realized using several of the previously proposed approaches, including many involving the use of low-inductance capacitances. We are aware that the electromagnetic interference (EMI) problems of plane power/ground resonance are induced because of the resonance caused by eddy currents or multiple reflections of voltage fluctuations. A novel technology was used in our previous study in which a conductive layer of dispersed metal particles was used instead of a copper plane [4][5]. This structure improved the PI for any clock frequency, particularly in the GHz region, with an impedance of less than 1 Ω. In this study, we examine the electromagnetic wave transmission data in order to investigate the different physical phenomena, and we present some fundamental data on PI and signal integrity (SI). The results indicate that the use of a transmission line with a metal particle conductive layer can yield various changes in the electromagnetic wave transmission speed, such as an increase of 76% or a decrease of 21%. The Z11 values of the power/GND plane test coupon were from 1.8 to 3.0 Ω in the frequency region from 5 to 20 GHz. These results suggest that the metal particle conductive layer has useful characteristics for improving the PI and SI.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127796491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457847
Wei Yao, F. Shi, Lei He, Siming Pan, B. Achkir, Li Li
Through-silicon-via (TSV) enables vertical connectivity between stacked chips or interposer and is a key technology for three-dimensional (3D) ICs. In this paper, we study the signal integrity issues of TSV-based 3D IC with high-speed signaling based on 3D electromagnetic field solver and SPICE simulations. Unlike other existing works, our study focuses on an array of TSVs and includes power and bandwidth trade-off between different signaling and termination techniques, such as single-ended, differential and reduced-swing signaling. From our study, to achieve the best power efficiency, unterminated single-ended reduced-swing signaling should be applied, while terminated single-ended signaling can provide the maximum bandwidth. Beyond TSV, critical design challenges for the junction structure between TSVs and RDL traces are also revealed and analyzed. Result shows that at 20GHz, the fanout-like junction structure could cause more than 10dB return loss (S11) degradation when changing TSV pitch from 50μm to 200μm and even contribute more insertion loss (S21) than the TSV itself.
{"title":"Power-bandwidth trade-off on TSV array in 3D IC and TSV-RDL junction design challenges","authors":"Wei Yao, F. Shi, Lei He, Siming Pan, B. Achkir, Li Li","doi":"10.1109/EPEPS.2012.6457847","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457847","url":null,"abstract":"Through-silicon-via (TSV) enables vertical connectivity between stacked chips or interposer and is a key technology for three-dimensional (3D) ICs. In this paper, we study the signal integrity issues of TSV-based 3D IC with high-speed signaling based on 3D electromagnetic field solver and SPICE simulations. Unlike other existing works, our study focuses on an array of TSVs and includes power and bandwidth trade-off between different signaling and termination techniques, such as single-ended, differential and reduced-swing signaling. From our study, to achieve the best power efficiency, unterminated single-ended reduced-swing signaling should be applied, while terminated single-ended signaling can provide the maximum bandwidth. Beyond TSV, critical design challenges for the junction structure between TSVs and RDL traces are also revealed and analyzed. Result shows that at 20GHz, the fanout-like junction structure could cause more than 10dB return loss (S11) degradation when changing TSV pitch from 50μm to 200μm and even contribute more insertion loss (S21) than the TSV itself.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131066504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457848
G. Charles, P. Franzon
In this study, we estimate, compare and analyze the PDN effects of four chip-stacking topologies. The chip-stacking topologies are: (1) F2B; (2) F2F; (3) B2F; and (4) B2B. The arrangement of various on-chip interconnect elements based on the chip-stacking topologies specific to the design of 3D IC-PDN, varies in impedance properties. To reduce the impedance effects NMOS decap unit cells are integrated into PDN system to suppress 3D-SSN. Conclusively, the results of the case study indicate B2F and F2B die stacking topologies results in lower impedance effects relative to F2F topology.
{"title":"Comparison of TSV-based PDN-design effects using various stacking topology methods","authors":"G. Charles, P. Franzon","doi":"10.1109/EPEPS.2012.6457848","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457848","url":null,"abstract":"In this study, we estimate, compare and analyze the PDN effects of four chip-stacking topologies. The chip-stacking topologies are: (1) F2B; (2) F2F; (3) B2F; and (4) B2B. The arrangement of various on-chip interconnect elements based on the chip-stacking topologies specific to the design of 3D IC-PDN, varies in impedance properties. To reduce the impedance effects NMOS decap unit cells are integrated into PDN system to suppress 3D-SSN. Conclusively, the results of the case study indicate B2F and F2B die stacking topologies results in lower impedance effects relative to F2F topology.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131306195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457868
Xin Chang, L. Tsang
In this paper, a new efficient methodology is used to model dense via arrays in 3D integrated circuit and package system, which also can include the layout of multiple vias sharing the same antipad. In order to accurately calculate all the effects of high order waveguide modes and azimuthal modes for complete signal integrity analysis of multiple closely spaced vias, we make use of transformation that converts the surface integration of magnetic surface currents into 1-dimensional line integration of surface charges on the vias and on the ground plane. We also use group T matrix to represent a group of vias to account for the scattering among different groups of vias. Numerical results illustrate physics that, after including high order mode effects using 1D line integration and group T matrix, the new method has great accuracy and efficiency for modeling multiple closely spaced vertical vias.
{"title":"A new efficient method for modeling dense via arrays with 1D discretization in 2D method of moment and group T matrix","authors":"Xin Chang, L. Tsang","doi":"10.1109/EPEPS.2012.6457868","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457868","url":null,"abstract":"In this paper, a new efficient methodology is used to model dense via arrays in 3D integrated circuit and package system, which also can include the layout of multiple vias sharing the same antipad. In order to accurately calculate all the effects of high order waveguide modes and azimuthal modes for complete signal integrity analysis of multiple closely spaced vias, we make use of transformation that converts the surface integration of magnetic surface currents into 1-dimensional line integration of surface charges on the vias and on the ground plane. We also use group T matrix to represent a group of vias to account for the scattering among different groups of vias. Numerical results illustrate physics that, after including high order mode effects using 1D line integration and group T matrix, the new method has great accuracy and efficiency for modeling multiple closely spaced vertical vias.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116139352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457901
Y. J. Tan, H. Heck, J. Kong, W. Tan
This paper presents an interleaved routing method for motherboard microstrip routing in Multi-Gbps interfaces. The proposed method yields improved channel performance in terms of Eye Height(mV) and Eye Width(ps) margins. Of note is the more prominent improvement in topologies with longer transmission lines. This method enables greater routing flexibility using full microstrip transmission lines with the benefit of improved channel margins at 20 mils inter-pair spacing. More importantly, it allows for the more tightly spaced 15 mils interpair spacing to be utilized without jeopardizing overall channel margins. Ultimately, this translates into a cost saving benefit in line with recent platforms' sleek and thin form factor.
{"title":"An implementation of interleaved microstrip motherboard routing in Multi-Gbps I/O channel margin improvement","authors":"Y. J. Tan, H. Heck, J. Kong, W. Tan","doi":"10.1109/EPEPS.2012.6457901","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457901","url":null,"abstract":"This paper presents an interleaved routing method for motherboard microstrip routing in Multi-Gbps interfaces. The proposed method yields improved channel performance in terms of Eye Height(mV) and Eye Width(ps) margins. Of note is the more prominent improvement in topologies with longer transmission lines. This method enables greater routing flexibility using full microstrip transmission lines with the benefit of improved channel margins at 20 mils inter-pair spacing. More importantly, it allows for the more tightly spaced 15 mils interpair spacing to be utilized without jeopardizing overall channel margins. Ultimately, this translates into a cost saving benefit in line with recent platforms' sleek and thin form factor.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"82 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120942761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457830
J. Aberle, B. Bensalem
A new memory bus concept that has the potential to dramatically improve double data rate (DDR) memory speed is presented. The memory signal is modulated onto an RF carrier which is routed using substrate integrated waveguide (SIW) interconnect technology. The channel is divided into multi-carrier bands where each symbol is modulated onto one carrier using 64-QAM format. The conventional DDR bus is entirely mapped into the proposed multi-carrier memory channel architecture (MCMCA). At the receiver the signal is demodulated and then delivered to SDRAM devices. Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 30 Gbps data transfer with error vector magnitude (EVM) not exceeding 2.26% and phase error of 1.07 degree or less.
{"title":"Ultra-high speed memory bus using microwave interconnects","authors":"J. Aberle, B. Bensalem","doi":"10.1109/EPEPS.2012.6457830","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457830","url":null,"abstract":"A new memory bus concept that has the potential to dramatically improve double data rate (DDR) memory speed is presented. The memory signal is modulated onto an RF carrier which is routed using substrate integrated waveguide (SIW) interconnect technology. The channel is divided into multi-carrier bands where each symbol is modulated onto one carrier using 64-QAM format. The conventional DDR bus is entirely mapped into the proposed multi-carrier memory channel architecture (MCMCA). At the receiver the signal is demodulated and then delivered to SDRAM devices. Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 30 Gbps data transfer with error vector magnitude (EVM) not exceeding 2.26% and phase error of 1.07 degree or less.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130410196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457886
S. Olivadese, Stefano Grivet-Talocia
This paper presents a technique for the numerical simulation of coupled high-speed channels terminated by arbitrary nonlinear drivers and receivers. The method builds on a number of existing techniques. A Delayed-Rational Macromodel is used to describe the channel in compact form, and a general Waveform Relaxation framework is used to cast the solution as an iterative process that refines initial estimates of transient scattering waves at the channel ports. Since a plain Waveform Relaxation approach is not able to guarantee convergence, we turn to a more general class of nonlinear algebraic solvers based on a combination of the Newton method with a Generalized Minimal Residual iteration, where the Waveform Relaxation equations act as a preconditioner. The convergence of this scheme can be proved in the general case. Numerical examples show that very few iterations are indeed required even for strongly nonlinear terminations.
{"title":"Transient analysis of high-speed channels via Newton-GMRES Waveform Relaxation","authors":"S. Olivadese, Stefano Grivet-Talocia","doi":"10.1109/EPEPS.2012.6457886","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457886","url":null,"abstract":"This paper presents a technique for the numerical simulation of coupled high-speed channels terminated by arbitrary nonlinear drivers and receivers. The method builds on a number of existing techniques. A Delayed-Rational Macromodel is used to describe the channel in compact form, and a general Waveform Relaxation framework is used to cast the solution as an iterative process that refines initial estimates of transient scattering waves at the channel ports. Since a plain Waveform Relaxation approach is not able to guarantee convergence, we turn to a more general class of nonlinear algebraic solvers based on a combination of the Newton method with a Generalized Minimal Residual iteration, where the Waveform Relaxation equations act as a preconditioner. The convergence of this scheme can be proved in the general case. Numerical examples show that very few iterations are indeed required even for strongly nonlinear terminations.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125994953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457869
L. Li, A. Ruehli, J. Fan
The computation of the power-plane inductance for multiple ports is an important part of the PDN design. In this paper, we present an efficient approach for the inductance computation. Since this PEEC approach is based on partial inductance computations, vias and other discontinuities can accurately be taken into account. Speed-up techniques are employed like the faster decay of the coupling due to the symmetry, sparsification and simplification of the partial mutual inductance evaluation. Also, an approximate rectangular mesh reduction method is introduced which allows a local increase in mesh density.
{"title":"Accurate and efficient computation of power plane pair inductance","authors":"L. Li, A. Ruehli, J. Fan","doi":"10.1109/EPEPS.2012.6457869","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457869","url":null,"abstract":"The computation of the power-plane inductance for multiple ports is an important part of the PDN design. In this paper, we present an efficient approach for the inductance computation. Since this PEEC approach is based on partial inductance computations, vias and other discontinuities can accurately be taken into account. Speed-up techniques are employed like the faster decay of the coupling due to the symmetry, sparsification and simplification of the partial mutual inductance evaluation. Also, an approximate rectangular mesh reduction method is introduced which allows a local increase in mesh density.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116847850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：