Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457875
A. Chinea, S. Grivet-Talocia, G. Calafiore
This paper introduces a new algorithm for passivity enforcement of linear lumped macromodels in scattering form. As typical in most state of the art passivity enforcement methods, we start with an initial non-passive macromodel obtained by a Vector Fitting process, and we perturb its parameters to make it passive. The proposed scheme is based on a convex formulation of both passivity constraints and objective function for accuracy preservation, thus allowing a formal proof of convergence to the unique optimal passive macromodel. This is a distinctive feature that differentiates the new scheme with respect to most state of the art methods, which either do not guarantee convergence or are not able to provide the most accurate solution. The presented algorithm can thus be safely used for those cases for which existing techniques fail. We illustrate the advantages of proposed method on a few benchmarks.
{"title":"Convex passivity enforcement of linear macromodels via alternate subgradient iterations","authors":"A. Chinea, S. Grivet-Talocia, G. Calafiore","doi":"10.1109/EPEPS.2012.6457875","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457875","url":null,"abstract":"This paper introduces a new algorithm for passivity enforcement of linear lumped macromodels in scattering form. As typical in most state of the art passivity enforcement methods, we start with an initial non-passive macromodel obtained by a Vector Fitting process, and we perturb its parameters to make it passive. The proposed scheme is based on a convex formulation of both passivity constraints and objective function for accuracy preservation, thus allowing a formal proof of convergence to the unique optimal passive macromodel. This is a distinctive feature that differentiates the new scheme with respect to most state of the art methods, which either do not guarantee convergence or are not able to provide the most accurate solution. The presented algorithm can thus be safely used for those cases for which existing techniques fail. We illustrate the advantages of proposed method on a few benchmarks.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122124510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457849
D. C. Zhang, M. Swaminathan, S. Huh
Simultaneous switching noise is a detrimental issue in high speed digital systems. In this paper, we utilize power transmission line based design and current steering to minimize power supply noise, eye height and jitter penalties.
{"title":"New power delivery scheme for 3D ICs to minimize simultaneous switching noise for high speed I/Os","authors":"D. C. Zhang, M. Swaminathan, S. Huh","doi":"10.1109/EPEPS.2012.6457849","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457849","url":null,"abstract":"Simultaneous switching noise is a detrimental issue in high speed digital systems. In this paper, we utilize power transmission line based design and current steering to minimize power supply noise, eye height and jitter penalties.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116596208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457874
S. Lalgudi, S. Asgari, M. Tsuk
Tabulated S-parameters are often tested for causality to ensure successful transient simulation. Existing approaches for this test either are not robust or have limited resolution in detecting noncausality. In this paper, a new approach for this test is proposed. The proposed approach is more robust and has better resolution than existing approaches.
{"title":"Improved procedure to test causality of tabulated S-parameters","authors":"S. Lalgudi, S. Asgari, M. Tsuk","doi":"10.1109/EPEPS.2012.6457874","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457874","url":null,"abstract":"Tabulated S-parameters are often tested for causality to ensure successful transient simulation. Existing approaches for this test either are not robust or have limited resolution in detecting noncausality. In this paper, a new approach for this test is proposed. The proposed approach is more robust and has better resolution than existing approaches.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115650916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457911
A. Chada, Songping Wu, J. Fan, J. Drewniak, B. Mutnury, D. de Araujo
Increases in printed circuit board (PCB) cost is leading to denser routing of high speed signal traces and this, in turn, is increasing the crosstalk among the traces. The crosstalk between the broadside coupled traces in adjacent layers is becoming an important factor to account for as the signal speeds increase. The coupling between parallel broadside coupled traces can be modeled using multi-conductor transmission line theory based on telegrapher equations using equivalent per-unit-length (Eq PUL) resistance, inductance, capacitance, and conductance (RLCG) matrices. The same approach is not applicable for the traces crossing at an arbitrary angle. A fast methodology to develop Eq PUL RLGC models that captures the coupling physics of broadside coupled traces crossing at an angle based on geometrical parameters of the stackup, and the dielectric material properties is proposed based on the idea presented in [1]. In this paper, validation of these equivalent models is done by estimating the crosstalk impact on eye opening at a specified bit error rate (BER) at different signal speeds and results are compared against full wave models.
印刷电路板(PCB)成本的增加导致高速信号走线的布线更加密集，这反过来又增加了走线之间的串扰。随着信号速度的增加，相邻层中宽侧耦合走线之间的串扰成为一个重要的考虑因素。并联宽侧耦合走线之间的耦合可以使用基于等效单位长度(Eq PUL)电阻、电感、电容和电导(RLCG)矩阵的电报器方程的多导体传输线理论来建模。同样的方法不适用于以任意角度相交的迹线。基于[1]中提出的思想，提出了一种快速开发Eq PUL RLGC模型的方法，该方法可以捕获基于堆叠几何参数以一定角度交叉的宽侧耦合走线的耦合物理特性和介电材料特性。在本文中，通过在不同信号速度下估计特定误码率(BER)下串扰对睁眼的影响来验证这些等效模型，并将结果与全波模型进行比较。
{"title":"Modeling broadside coupled traces using equivalent per unit length (Eq PUL) RLGC model","authors":"A. Chada, Songping Wu, J. Fan, J. Drewniak, B. Mutnury, D. de Araujo","doi":"10.1109/EPEPS.2012.6457911","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457911","url":null,"abstract":"Increases in printed circuit board (PCB) cost is leading to denser routing of high speed signal traces and this, in turn, is increasing the crosstalk among the traces. The crosstalk between the broadside coupled traces in adjacent layers is becoming an important factor to account for as the signal speeds increase. The coupling between parallel broadside coupled traces can be modeled using multi-conductor transmission line theory based on telegrapher equations using equivalent per-unit-length (Eq PUL) resistance, inductance, capacitance, and conductance (RLCG) matrices. The same approach is not applicable for the traces crossing at an arbitrary angle. A fast methodology to develop Eq PUL RLGC models that captures the coupling physics of broadside coupled traces crossing at an angle based on geometrical parameters of the stackup, and the dielectric material properties is proposed based on the idea presented in [1]. In this paper, validation of these equivalent models is done by estimating the crosstalk impact on eye opening at a specified bit error rate (BER) at different signal speeds and results are compared against full wave models.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123385712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457902
F. Baez, M. Cranmer, M. Shapiro, J. Audet, D. Berger, E. Sprogis, C. Collins, S. Iyer
A multichip module package has been designed in IBM's silicon technology. The module consists of two chips of same size and type communicating horizontally through a silicon interposer to a large ASIC chip. The chip to chip links operate at 8 Gbps with a loss of 0.5 dB/mm and reflections <; 20 dB. All links are skew matched to within 2 ps. Model to hardware correlation was performed and trace loss is within 0.1 dB of modeling data. The input to the module consists of a high speed RF signal and the module was optimized for board to package transition. Outputs of the module are 15Gbps high speed links. Both input and output signals go up or down a through silicon via (TSV) in the silicon interposer as part of their electrical paths. TSV parameters do not limit the electrical performance of the module.
{"title":"Electrical design and performance of a multichip module on a silicon interposer","authors":"F. Baez, M. Cranmer, M. Shapiro, J. Audet, D. Berger, E. Sprogis, C. Collins, S. Iyer","doi":"10.1109/EPEPS.2012.6457902","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457902","url":null,"abstract":"A multichip module package has been designed in IBM's silicon technology. The module consists of two chips of same size and type communicating horizontally through a silicon interposer to a large ASIC chip. The chip to chip links operate at 8 Gbps with a loss of 0.5 dB/mm and reflections <; 20 dB. All links are skew matched to within 2 ps. Model to hardware correlation was performed and trace loss is within 0.1 dB of modeling data. The input to the module consists of a high speed RF signal and the module was optimized for board to package transition. Outputs of the module are 15Gbps high speed links. Both input and output signals go up or down a through silicon via (TSV) in the silicon interposer as part of their electrical paths. TSV parameters do not limit the electrical performance of the module.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129932407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457857
Jayong Koo, M. R. Quddus, B. Silva, A. Norman
The simultaneous switching noise (SSN) from single-ended signaling I/O interfaces is significant when there are multiple channels transmitting data in parallel. The memory interfaces use the single-ended signaling scheme where the power delivery noise spectrum may coincide with some critical radio bands or resonance frequencies within the platform depending on the bit pattern being transmitted from the driver buffers. This will adversely affect the timing margin and can be one of the electromagnetic interference (EMI) sources as well. While it is good to use transistor buffer models in SSN estimation, it may significantly increase the complexity resulting in too long simulation time or convergence problems. The suggested method takes the transient supply currents when the transistor buffer transits its state from 0 to 1 and from 1 to 0, and synthesizes the full supply current for an arbitrary bit-pattern and data rate. This allows high accuracy in the supply current profiles while minimizing the power integrity simulation complexity. The method is extendable to tri-state buffers and different channel termination schemes.
{"title":"I/O supply current synthesis for power integrity analysis of single-ended signaling scheme","authors":"Jayong Koo, M. R. Quddus, B. Silva, A. Norman","doi":"10.1109/EPEPS.2012.6457857","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457857","url":null,"abstract":"The simultaneous switching noise (SSN) from single-ended signaling I/O interfaces is significant when there are multiple channels transmitting data in parallel. The memory interfaces use the single-ended signaling scheme where the power delivery noise spectrum may coincide with some critical radio bands or resonance frequencies within the platform depending on the bit pattern being transmitted from the driver buffers. This will adversely affect the timing margin and can be one of the electromagnetic interference (EMI) sources as well. While it is good to use transistor buffer models in SSN estimation, it may significantly increase the complexity resulting in too long simulation time or convergence problems. The suggested method takes the transient supply currents when the transistor buffer transits its state from 0 to 1 and from 1 to 0, and synthesizes the full supply current for an arbitrary bit-pattern and data rate. This allows high accuracy in the supply current profiles while minimizing the power integrity simulation complexity. The method is extendable to tri-state buffers and different channel termination schemes.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128998090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457834
T. Winkel, H. Harrer, T. Strach, R. Rímolo-Donadío, Y. Kwark, X. Duan, C. Schuster
Considerations for comprehensive simulation and analysis of high-speed links in complex server systems are discussed in this work. A framework that considers the interactions between multiple signals and the power distribution network is described. In the last section, the nature of the interactions between power and signal domains is analyzed by means of a simplified scenario at board level.
{"title":"Framework for co-simulation of signal and power integrity in server systems","authors":"T. Winkel, H. Harrer, T. Strach, R. Rímolo-Donadío, Y. Kwark, X. Duan, C. Schuster","doi":"10.1109/EPEPS.2012.6457834","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457834","url":null,"abstract":"Considerations for comprehensive simulation and analysis of high-speed links in complex server systems are discussed in this work. A framework that considers the interactions between multiple signals and the power distribution network is described. In the last section, the nature of the interactions between power and signal domains is analyzed by means of a simplified scenario at board level.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125870013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457850
Y. Tanaka, H. Takatani, H. Fujita, Y. Oizono, Y. Nabeshima, T. Sudo, A. Sakai, S. Uchiyama, H. Ikeda
Simultaneous switching output buffer (SSO) noise and impedance of power distribution network (PDN) for a 3D systemin package (SiP) with 4k-IO widebus structure has been investigated. The 3D SiP consisted of 3 stacked chips and an organic interposer. These three chips were a memory chip on the top, a silicon interposer in the middle, and a logic chip on the bottom. The size of each chip was the same, and 9.93 mm by 9.93 mm. More than 4096 of through silicon vias (TSV's) were formed to the silicon interposer. Next, these 3 stacked chips were assembled on the organic interposer, whose size was 26 mm by 26mm. SSO noise is one of critical issues for the 3D SiP with 4k-IO widebus structure. So, the SSO noise was measured in the miniIO power supply system in an evaluation board. Furthermore the PDN impedance for each chip was measured by direct contact method. Then, the total PDN impedance was synthesized to confirm the anti-resonance peak of it.
研究了具有4k-IO宽总线结构的3D系统封装(SiP)的同步交换输出缓冲器(SSO)噪声和配电网络(PDN)阻抗。3D SiP由3个堆叠芯片和一个有机中间体组成。这三块芯片是上面的存储芯片，中间的硅中间层，下面的逻辑芯片。每个芯片的尺寸相同，都是9.93 mm × 9.93 mm。在硅中间体上形成了4096个硅通孔(TSV)。然后，将这3个堆叠芯片组装在26mm × 26mm的有机中间层上。单点登录噪声是4k-IO宽总线结构的3D SiP的关键问题之一。为此，在评估板上对微型供电系统的单点同步噪声进行了测量。采用直接接触法测量各芯片的PDN阻抗。然后合成PDN总阻抗，确定其抗谐振峰值。
{"title":"Measurement of SSO noise and PDN impedance of 3D SiP with 4k-IO widebus structure","authors":"Y. Tanaka, H. Takatani, H. Fujita, Y. Oizono, Y. Nabeshima, T. Sudo, A. Sakai, S. Uchiyama, H. Ikeda","doi":"10.1109/EPEPS.2012.6457850","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457850","url":null,"abstract":"Simultaneous switching output buffer (SSO) noise and impedance of power distribution network (PDN) for a 3D systemin package (SiP) with 4k-IO widebus structure has been investigated. The 3D SiP consisted of 3 stacked chips and an organic interposer. These three chips were a memory chip on the top, a silicon interposer in the middle, and a logic chip on the bottom. The size of each chip was the same, and 9.93 mm by 9.93 mm. More than 4096 of through silicon vias (TSV's) were formed to the silicon interposer. Next, these 3 stacked chips were assembled on the organic interposer, whose size was 26 mm by 26mm. SSO noise is one of critical issues for the 3D SiP with 4k-IO widebus structure. So, the SSO noise was measured in the miniIO power supply system in an evaluation board. Furthermore the PDN impedance for each chip was measured by direct contact method. Then, the total PDN impedance was synthesized to confirm the anti-resonance peak of it.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133219610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457866
J. J. Kim, Heegon Kim, Sunkyu Kong, D. Jung, Joungho Kim, Jiseong Kim, Hajin Sung
The importance of current detection has been highlighted with the introduction of 3D-IC, in order to ensure the safe and reliable operation of analog circuits in mixed-signal systems. In this paper, we propose toroidal current probe embedded in multi-layer printed circuit boards (PCBs) for current detection. Current is magnetically coupled to the proposed current probe and the transfer impedance between the port of injected current and the proposed current probe is used for the analysis of current coupling and current reconstruction. Through time- and frequency-domain experimental measurements with test vehicles on multilayer PCBs, we verified that the proposed current probe can accurately detect current signals. The proposed current probe does not influence the original current path, yet achieves high accuracy with a compact size by using a toroidal array of vias that surrounds the current path.
{"title":"Embedded toroidal magnetic coupling probe in multi-layer PCBs for current measurement","authors":"J. J. Kim, Heegon Kim, Sunkyu Kong, D. Jung, Joungho Kim, Jiseong Kim, Hajin Sung","doi":"10.1109/EPEPS.2012.6457866","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457866","url":null,"abstract":"The importance of current detection has been highlighted with the introduction of 3D-IC, in order to ensure the safe and reliable operation of analog circuits in mixed-signal systems. In this paper, we propose toroidal current probe embedded in multi-layer printed circuit boards (PCBs) for current detection. Current is magnetically coupled to the proposed current probe and the transfer impedance between the port of injected current and the proposed current probe is used for the analysis of current coupling and current reconstruction. Through time- and frequency-domain experimental measurements with test vehicles on multilayer PCBs, we verified that the proposed current probe can accurately detect current signals. The proposed current probe does not influence the original current path, yet achieves high accuracy with a compact size by using a toroidal array of vias that surrounds the current path.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130607027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457897
T. Sekine, H. Asai
This paper describes a fast transient simulation technique based on a block-type leapfrog scheme for general nonlinear circuits. In existing leapfrog-based techniques, there is a restriction on dealing with nonlinear elements in the circuit. On the other hand, the block-type leapfrog scheme is suitable for the simulation of tightly coupled networks such as the equivalent circuit of multiconductor transmission lines (MTLs). In this work, we extend the block-type leapfrog scheme to incorporate generalized nonlinear elements, which have two or more terminals such as MOSFETs. The proposed method partitions the circuit into some kinds of local blocks, and locally dense and nonlinear calculations are effectively confined within each relatively-small block. Example simulations of MTLs with nonlinear drivers and terminations show that the leapfrog-based nonlinear solver is much more efficient than HSPICE.
{"title":"Nonlinear block-type leapfrog scheme for the fast simulation of multiconductor transmission lines with nonlinear drivers and terminations","authors":"T. Sekine, H. Asai","doi":"10.1109/EPEPS.2012.6457897","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457897","url":null,"abstract":"This paper describes a fast transient simulation technique based on a block-type leapfrog scheme for general nonlinear circuits. In existing leapfrog-based techniques, there is a restriction on dealing with nonlinear elements in the circuit. On the other hand, the block-type leapfrog scheme is suitable for the simulation of tightly coupled networks such as the equivalent circuit of multiconductor transmission lines (MTLs). In this work, we extend the block-type leapfrog scheme to incorporate generalized nonlinear elements, which have two or more terminals such as MOSFETs. The proposed method partitions the circuit into some kinds of local blocks, and locally dense and nonlinear calculations are effectively confined within each relatively-small block. Example simulations of MTLs with nonlinear drivers and terminations show that the leapfrog-based nonlinear solver is much more efficient than HSPICE.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114078276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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