Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457889
S. Roy, A. Dounavis
Modeling of power distribution networks in electronic packages requires the two dimensional discretization of the distributed power/ground planes which can be computationally expensive. Recently, the waveform relaxation algorithm has been proposed for fast transient simulation of power/ground planes. However, due to the strong coupling of each node in a two dimensional (2D) physical space, the relaxation iterations exhibit slow convergence and special techniques need to be adopted to ensure efficient convergence. In this work, a novel waveform relaxation algorithm based on physically partitioning the power/ground plane into smaller overlapping subcircuits is presented. The overlap between the subcircuits provides greater exchange of information per iteration leading to accelerated convergence of the waveform relaxation algorithm. A numerical example has been provided to illustrate the validity of the proposed algorithm over full SPICE simulations.
{"title":"Waveform relaxation with overlapping based partitioning for fast transient simulation of package/board power distribution networks","authors":"S. Roy, A. Dounavis","doi":"10.1109/EPEPS.2012.6457889","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457889","url":null,"abstract":"Modeling of power distribution networks in electronic packages requires the two dimensional discretization of the distributed power/ground planes which can be computationally expensive. Recently, the waveform relaxation algorithm has been proposed for fast transient simulation of power/ground planes. However, due to the strong coupling of each node in a two dimensional (2D) physical space, the relaxation iterations exhibit slow convergence and special techniques need to be adopted to ensure efficient convergence. In this work, a novel waveform relaxation algorithm based on physically partitioning the power/ground plane into smaller overlapping subcircuits is presented. The overlap between the subcircuits provides greater exchange of information per iteration leading to accelerated convergence of the waveform relaxation algorithm. A numerical example has been provided to illustrate the validity of the proposed algorithm over full SPICE simulations.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122283778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457833
Hao Liu, Chung-Kuan Cheng
A global link architecture is proposed for high-speed, ultra-low-energy communication. A high-resolution comparator at receiver is used to reduce the voltage requirement. At the driver, we adopt a continuous-time linear equalizer (CTLE) with low-voltage differential signaling (LVDS) to save power. Compared with the state-of-art on-chip interconnect driver-receiver co-design, over 75% reduction is observed in energy-per-bit. With dual driver supply of 1.1V and 0.8V, the interconnect runs at 10.0 Gpbs signaling. For top layer wires at 10mm distance using 2.2 μm pitch, we use ground shield on three sides. The communication achieves 21.5ps/mm latency and consumes 0.053pJ/b. For intermediate layer wires at 2.5 mm distance using 0.6 μm pitch, we use ground shield on 4 sides. The communication achieves 55.2 ps/mm latency and 0.048pJ/b energy using the predictive 45nm CMOS model.
{"title":"Ultra-low power on-chip differential interconnects using high-resolution comparator","authors":"Hao Liu, Chung-Kuan Cheng","doi":"10.1109/EPEPS.2012.6457833","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457833","url":null,"abstract":"A global link architecture is proposed for high-speed, ultra-low-energy communication. A high-resolution comparator at receiver is used to reduce the voltage requirement. At the driver, we adopt a continuous-time linear equalizer (CTLE) with low-voltage differential signaling (LVDS) to save power. Compared with the state-of-art on-chip interconnect driver-receiver co-design, over 75% reduction is observed in energy-per-bit. With dual driver supply of 1.1V and 0.8V, the interconnect runs at 10.0 Gpbs signaling. For top layer wires at 10mm distance using 2.2 μm pitch, we use ground shield on three sides. The communication achieves 21.5ps/mm latency and consumes 0.053pJ/b. For intermediate layer wires at 2.5 mm distance using 0.6 μm pitch, we use ground shield on 4 sides. The communication achieves 55.2 ps/mm latency and 0.048pJ/b energy using the predictive 45nm CMOS model.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129847675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457870
Y. Shlepnev
Governing partial differential equations are derived for multiple parallel plane structure in frequency-domain. The equations can be considered as an extension of broadband equations derived earlier for one pair of planes and as an extension of well-known 2D Telegrapher's equations originally derived for analysis of narrow-band microwave planar circuits. The broadband equations have appropriate high and low frequency asymptotes and are suitable for analysis of power delivery networks (PDN) with multiple parallel planes at frequencies from DC to multi-gigahertz frequency range. Derived equations are validated with results of 3D electromagnetic analysis and with published measured data.
{"title":"Coupled 2D Telegrapher's equations for PDN analysis","authors":"Y. Shlepnev","doi":"10.1109/EPEPS.2012.6457870","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457870","url":null,"abstract":"Governing partial differential equations are derived for multiple parallel plane structure in frequency-domain. The equations can be considered as an extension of broadband equations derived earlier for one pair of planes and as an extension of well-known 2D Telegrapher's equations originally derived for analysis of narrow-band microwave planar circuits. The broadband equations have appropriate high and low frequency asymptotes and are suitable for analysis of power delivery networks (PDN) with multiple parallel planes at frequencies from DC to multi-gigahertz frequency range. Derived equations are validated with results of 3D electromagnetic analysis and with published measured data.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116263119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457854
D. Becerra-Perez, J. Rayas-Sánchez
Crosstalk is a signal integrity effect that negatively impacts high-speed digital designs, especially those with dense routing. Several techniques have been proposed to reduce crosstalk. One of them consists of using innovative microstrip structures, such as the stub-alternated and the serpentine structures, which are intended to reduce far-end crosstalk. However, these structures also present a negative effect on return loss and near-end crosstalk. In this paper, these two structures are optimized for far-end crosstalk reduction while minimizing their negative impact on reflections and near-end crosstalk. A genetic algorithm complemented with the Nelder-Mead method is employed for direct optimization, using highly accurate EM simulations in Sonnet driven from Python.
{"title":"Optimization of the stub-alternated and serpentine microstrip structures to minimize far-end crosstalk","authors":"D. Becerra-Perez, J. Rayas-Sánchez","doi":"10.1109/EPEPS.2012.6457854","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457854","url":null,"abstract":"Crosstalk is a signal integrity effect that negatively impacts high-speed digital designs, especially those with dense routing. Several techniques have been proposed to reduce crosstalk. One of them consists of using innovative microstrip structures, such as the stub-alternated and the serpentine structures, which are intended to reduce far-end crosstalk. However, these structures also present a negative effect on return loss and near-end crosstalk. In this paper, these two structures are optimized for far-end crosstalk reduction while minimizing their negative impact on reflections and near-end crosstalk. A genetic algorithm complemented with the Nelder-Mead method is employed for direct optimization, using highly accurate EM simulations in Sonnet driven from Python.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133448166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457892
Y. Uematsu, M. Yagyu, H. Osaka
This report proposes low power supply noise interposers with two types of structures based on embedding technologies. These structures reduce (i) self-noise and (ii) transfer-noise. We designed and developed these two structures and evaluated them experimentally. Using small chip components (0402) permitted interposer heights of less than 0.6 mm. The measurement results indicate the following: (i) reductions of on-chip power supply noise on the order of several hundreds of MHz; (ii) S21 less than -60dB achieved from 10 MHz to a few GHz.
{"title":"Interposers for power supply voltage noise reduction","authors":"Y. Uematsu, M. Yagyu, H. Osaka","doi":"10.1109/EPEPS.2012.6457892","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457892","url":null,"abstract":"This report proposes low power supply noise interposers with two types of structures based on embedding technologies. These structures reduce (i) self-noise and (ii) transfer-noise. We designed and developed these two structures and evaluated them experimentally. Using small chip components (0402) permitted interposer heights of less than 0.6 mm. The measurement results indicate the following: (i) reductions of on-chip power supply noise on the order of several hundreds of MHz; (ii) S21 less than -60dB achieved from 10 MHz to a few GHz.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126189103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457876
W. Cui, A. Sathanur, V. Jandhyala
Full-wave simulation and design of interconnect systems is becoming increasingly important in view of the continuing trend towards miniaturization and dense integration of components in electronic systems. While full-wave simulation methods have advanced rapidly over the last decade, there is a growing need for superior automated design tools. In this paper we first motivate the need for better design space exploration in high dimensions and outline the key ingredients that are imperative for the development of a successful simulation-based automated design tool. In this direction we describe the application of Orthogonal Arrays as an efficient sampling scheme and the Gaussian Process Regression as a promising model generation scheme for high dimensional design space exploration. We also describe an adaptive strategy for the model refinement and illustrate the same with a full-wave multi-conductor transmission line example. Finally we conclude by outlining the open problems and research challenges in this direction.
{"title":"Simulation-based design of high dimensional electromagnetic systems","authors":"W. Cui, A. Sathanur, V. Jandhyala","doi":"10.1109/EPEPS.2012.6457876","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457876","url":null,"abstract":"Full-wave simulation and design of interconnect systems is becoming increasingly important in view of the continuing trend towards miniaturization and dense integration of components in electronic systems. While full-wave simulation methods have advanced rapidly over the last decade, there is a growing need for superior automated design tools. In this paper we first motivate the need for better design space exploration in high dimensions and outline the key ingredients that are imperative for the development of a successful simulation-based automated design tool. In this direction we describe the application of Orthogonal Arrays as an efficient sampling scheme and the Gaussian Process Regression as a promising model generation scheme for high dimensional design space exploration. We also describe an adaptive strategy for the model refinement and illustrate the same with a full-wave multi-conductor transmission line example. Finally we conclude by outlining the open problems and research challenges in this direction.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127719176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457909
D. Jung, Joohee Kim, Heegon Kim, J. J. Kim, Joungho Kim, J. Pak, J. Yook, J. C. Kim
As a solution to limitlessly growing demand on miniaturization of electronic devices, through silicon via (TSV) based 3-dimensional integrated circuits (3D-IC) have brought another era of technology evolution. However, one of the remaining challenges to overcome is to increase the reliability of the products. Due to the instability of TSV fabrication process, different types of failure may be caused, affecting the performance of 3D-IC. TSV test method is essential for TSV based 3D-IC to be integrated in the products. One of the main failure types is disconnection failure in the channel. The point of defect not only has to be detected, but also has to be localized, so that appropriate channel is chosen to go through the recovery process. By measuring the fabricated test vehicles in frequency and time domain, the location of disconnection along the channel can be detected. S11 and S22 magnitudes are measured for frequency domain analysis. The degrees of decrease in two plots are compared to test how far the signals from each port travel before detecting the disconnection. Applying the similar idea, time domain measurement is analyzed with time-domain reflectometry (TDR) waveforms. The TDR waveforms from port 1 and port 2 are compared by their rising times, which depend on parasitic shunt capacitances within the channel. The values may be quantified for more precise TSV testing.
{"title":"Frequency and time domain measurement of through-silicon via (TSV) failure","authors":"D. Jung, Joohee Kim, Heegon Kim, J. J. Kim, Joungho Kim, J. Pak, J. Yook, J. C. Kim","doi":"10.1109/EPEPS.2012.6457909","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457909","url":null,"abstract":"As a solution to limitlessly growing demand on miniaturization of electronic devices, through silicon via (TSV) based 3-dimensional integrated circuits (3D-IC) have brought another era of technology evolution. However, one of the remaining challenges to overcome is to increase the reliability of the products. Due to the instability of TSV fabrication process, different types of failure may be caused, affecting the performance of 3D-IC. TSV test method is essential for TSV based 3D-IC to be integrated in the products. One of the main failure types is disconnection failure in the channel. The point of defect not only has to be detected, but also has to be localized, so that appropriate channel is chosen to go through the recovery process. By measuring the fabricated test vehicles in frequency and time domain, the location of disconnection along the channel can be detected. S11 and S22 magnitudes are measured for frequency domain analysis. The degrees of decrease in two plots are compared to test how far the signals from each port travel before detecting the disconnection. Applying the similar idea, time domain measurement is analyzed with time-domain reflectometry (TDR) waveforms. The TDR waveforms from port 1 and port 2 are compared by their rising times, which depend on parasitic shunt capacitances within the channel. The values may be quantified for more precise TSV testing.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124504982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/epeps.2012.6457835
Taigon Song, N. Sturcken, K. Athikulwongse, K. Shepard, S. Lim
Integrated voltage regulators (IVRs) promise to improve performance-per-watt for microprocessors and systems-on-chip by reducing supply voltage margins, resistive losses in the power distribution network, and by enabling power management with greater temporal resolution. However, the thermal impact of IVRs has not been well studied, and the methodologies for thermal analysis of analog/digital mixed-signal designs, such as voltage regulators on chip, have not yet been developed. In this paper, we present a thermal analysis methodology for 2.5-D IVR. Our results show that (1) the integrated power inductor is the hottest component in the IVR, and (2) the temperature of the IVR rises rapidly when the power inductor and the circuitries of the IVR chip overlap. In order to address these issues, we propose two design optimization techniques: design block relocation and inductor spreading. Related experiments show the effectiveness of these methods.
集成电压调节器(ivr)有望通过降低供电电压余量、配电网络中的电阻损耗以及实现更高时间分辨率的电源管理来提高微处理器和片上系统的每瓦性能。然而，ivr的热影响尚未得到很好的研究，并且模拟/数字混合信号设计(如芯片上的电压调节器)的热分析方法尚未开发。在本文中，我们提出了一种2.5 d IVR的热分析方法。我们的研究结果表明:(1)集成的功率电感是IVR中最热的部件，(2)当功率电感与IVR芯片的电路重叠时，IVR的温度会迅速上升。为了解决这些问题，我们提出了两种设计优化技术:设计块重新定位和电感扩展。相关实验证明了这些方法的有效性。
{"title":"Thermal analysis and optimization of 2.5-D integrated voltage regulator","authors":"Taigon Song, N. Sturcken, K. Athikulwongse, K. Shepard, S. Lim","doi":"10.1109/epeps.2012.6457835","DOIUrl":"https://doi.org/10.1109/epeps.2012.6457835","url":null,"abstract":"Integrated voltage regulators (IVRs) promise to improve performance-per-watt for microprocessors and systems-on-chip by reducing supply voltage margins, resistive losses in the power distribution network, and by enabling power management with greater temporal resolution. However, the thermal impact of IVRs has not been well studied, and the methodologies for thermal analysis of analog/digital mixed-signal designs, such as voltage regulators on chip, have not yet been developed. In this paper, we present a thermal analysis methodology for 2.5-D IVR. Our results show that (1) the integrated power inductor is the hottest component in the IVR, and (2) the temperature of the IVR rises rapidly when the power inductor and the circuitries of the IVR chip overlap. In order to address these issues, we propose two design optimization techniques: design block relocation and inductor spreading. Related experiments show the effectiveness of these methods.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"2020 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130822330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457878
A. Hardock, S. Muller, X. Duan, H. Bruns, C. Schuster
A fast approach for the calculation of ground via return currents using the contour integral method is presented. From the analysis of the displacement currents design rules for optimized vias in multilayered boards are derived.
{"title":"Minimizing displacement return currents in multilayer via structures","authors":"A. Hardock, S. Muller, X. Duan, H. Bruns, C. Schuster","doi":"10.1109/EPEPS.2012.6457878","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457878","url":null,"abstract":"A fast approach for the calculation of ground via return currents using the contour integral method is presented. From the analysis of the displacement currents design rules for optimized vias in multilayered boards are derived.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131028547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457846
X. Gu, J. Silberman, Yong Liu, X. Duan
Substrate noise coupling induced by Through Silicon Vias in SOI substrates is modeled and analyzed in frequency- and time-domain. In addition to a buried oxide layer, a highly doped N+ epi layer used for deep trench devices is taken into account in full-wave electromagnetic simulations. Equivalent circuit models are extracted to assess the impact of noise coupling on active circuit performance. A noise mitigation technique of using CMOS process compatible buried interface contacts is proposed and studied. Simulation results demonstrate that a low impedance ground return path can be readily created for effective substrate noise reduction in 3D IC design.
{"title":"Mitigating TSV-induced substrate noise coupling in 3-D IC using buried interface contacts","authors":"X. Gu, J. Silberman, Yong Liu, X. Duan","doi":"10.1109/EPEPS.2012.6457846","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457846","url":null,"abstract":"Substrate noise coupling induced by Through Silicon Vias in SOI substrates is modeled and analyzed in frequency- and time-domain. In addition to a buried oxide layer, a highly doped N+ epi layer used for deep trench devices is taken into account in full-wave electromagnetic simulations. Equivalent circuit models are extracted to assess the impact of noise coupling on active circuit performance. A noise mitigation technique of using CMOS process compatible buried interface contacts is proposed and studied. Simulation results demonstrate that a low impedance ground return path can be readily created for effective substrate noise reduction in 3D IC design.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121460834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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