Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457841
F. Rao, S. Hindi
Clock channel jitter amplification factor in terms of transfer function or S-parameters is derived. Amplification is shown to arise from smaller attenuation in jitter lower sideband than in the fundamental. Amplification scaling with loss is obtained analytically.
{"title":"Frequency domain analysis of jitter amplification in clock channels","authors":"F. Rao, S. Hindi","doi":"10.1109/EPEPS.2012.6457841","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457841","url":null,"abstract":"Clock channel jitter amplification factor in terms of transfer function or S-parameters is derived. Amplification is shown to arise from smaller attenuation in jitter lower sideband than in the fundamental. Amplification scaling with loss is obtained analytically.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123199676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457899
Lisha Zhang, A. Abbaspour-Tamijani, G. Pan, H. Pan
We present design and implementation of the aperture coupling based compact system of lens enhanced phased array (LEPA) for 60 GHz band high-speed internet, data and voice channels. The LEPA is a high-directivity steerable integrated system without putting penalties on the chip size and DC power consumption. The core of a LEPA is composed of the antenna-filter-antenna (AFA) structures consisting of two layers of 15 mil-thick low-loss microwave laminates and three 18um-thick copper layers. An incident wave with proper polarization is received by the top slot in the input side, passes through a half-wave stripline resonator, and then reradiates from the bottom slot on the output side with orthogonal polarization. Vias surrounding AFA elements guarantee that no parallel plate modes are excited between the two grounds, while any surface wave modes formed on the reactive surface of the array may still contribute to the occurrence of blind scan angles and need to be suppressed.
{"title":"On aperture coupling based compact system of lens enhanced phased array","authors":"Lisha Zhang, A. Abbaspour-Tamijani, G. Pan, H. Pan","doi":"10.1109/EPEPS.2012.6457899","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457899","url":null,"abstract":"We present design and implementation of the aperture coupling based compact system of lens enhanced phased array (LEPA) for 60 GHz band high-speed internet, data and voice channels. The LEPA is a high-directivity steerable integrated system without putting penalties on the chip size and DC power consumption. The core of a LEPA is composed of the antenna-filter-antenna (AFA) structures consisting of two layers of 15 mil-thick low-loss microwave laminates and three 18um-thick copper layers. An incident wave with proper polarization is received by the top slot in the input side, passes through a half-wave stripline resonator, and then reradiates from the bottom slot on the output side with orthogonal polarization. Vias surrounding AFA elements guarantee that no parallel plate modes are excited between the two grounds, while any surface wave modes formed on the reactive surface of the array may still contribute to the occurrence of blind scan angles and need to be suppressed.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128123334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457882
W. Dghais, T. Cunha, J. Pedro
The paper presents a novel extraction procedure based on the frequency domain formulation of the current-charge (I-Q) behavioral model for digital I/O buffers/drivers output admittance followed by a time domain extraction of the predriver's nonlinear dynamic functions. The large signal model's functions of the drivers' output admittance are derived from the bias-dependent scattering, or S-parameters, measurements. This easy and fast extraction method allows the accurate generation of the data-based model from automated and straightforward measurements. The extracted model's functions are implemented as lookup tables (LUTs) and the behavioral model is validated in typical SI scenario.
{"title":"A mixed-domain behavioral model's extraction for digital I/O buffers","authors":"W. Dghais, T. Cunha, J. Pedro","doi":"10.1109/EPEPS.2012.6457882","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457882","url":null,"abstract":"The paper presents a novel extraction procedure based on the frequency domain formulation of the current-charge (I-Q) behavioral model for digital I/O buffers/drivers output admittance followed by a time domain extraction of the predriver's nonlinear dynamic functions. The large signal model's functions of the drivers' output admittance are derived from the bias-dependent scattering, or S-parameters, measurements. This easy and fast extraction method allows the accurate generation of the data-based model from automated and straightforward measurements. The extracted model's functions are implemented as lookup tables (LUTs) and the behavioral model is validated in typical SI scenario.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134560882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457903
Hongsheng Xu, Jiming Song, T. Kamgaing
A novel volume integral equation for the current distribution over interconnects with arbitrary cross-sectional geometry is presented based on the free space Green's function without approximation. For very low frequency, it can be reduced to the widely-used quasi-static approximation. The quasi-static volume integral equation is not accurate enough for the calculation of current distribution. A comparison is made with the different methods known in literature to calculate the per unit length internal impedance. Detailed discussion is given for the different current distributions and the definitions with their effects to the internal impedance, either for a high frequency range or a low frequency range.
{"title":"Current distribution and internal impedance of interconnect","authors":"Hongsheng Xu, Jiming Song, T. Kamgaing","doi":"10.1109/EPEPS.2012.6457903","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457903","url":null,"abstract":"A novel volume integral equation for the current distribution over interconnects with arbitrary cross-sectional geometry is presented based on the free space Green's function without approximation. For very low frequency, it can be reduced to the widely-used quasi-static approximation. The quasi-static volume integral equation is not accurate enough for the calculation of current distribution. A comparison is made with the different methods known in literature to calculate the per unit length internal impedance. Detailed discussion is given for the different current distributions and the definitions with their effects to the internal impedance, either for a high frequency range or a low frequency range.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131017168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457851
Heegon Kim, Jonghyun Cho, Joohee Kim, Kiyeong Kim, Sumin Choi, Joungho Kim, J. Pak
In this paper, a new compact on-interposer passive equalizer was proposed for chip-to-chip high-speed data transmission on the silicon-based on-interposer channel. The proposed equalizer uses the parasitic resistance and inductance of the coil-shaped on-interposer shunt metal line structure to produce the high-pass filter for loss compensation. This results in wide-band channel equalization and low power-consumption. Moreover, the compact coil-shaped structure of the proposed equalizer allows for wide I/O and high adjustability. The remarkable performance of the proposed compact on-interposer passive equalizer is successfully demonstrated by a frequency-and time-domain simulation of up to 10 Gbps.
{"title":"A compact on-interposer passive equalizer for chip-to-chip high-speed data transmission","authors":"Heegon Kim, Jonghyun Cho, Joohee Kim, Kiyeong Kim, Sumin Choi, Joungho Kim, J. Pak","doi":"10.1109/EPEPS.2012.6457851","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457851","url":null,"abstract":"In this paper, a new compact on-interposer passive equalizer was proposed for chip-to-chip high-speed data transmission on the silicon-based on-interposer channel. The proposed equalizer uses the parasitic resistance and inductance of the coil-shaped on-interposer shunt metal line structure to produce the high-pass filter for loss compensation. This results in wide-band channel equalization and low power-consumption. Moreover, the compact coil-shaped structure of the proposed equalizer allows for wide I/O and high adjustability. The remarkable performance of the proposed compact on-interposer passive equalizer is successfully demonstrated by a frequency-and time-domain simulation of up to 10 Gbps.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125140321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457842
R. Rímolo-Donadío, C. Baks, B. Lee, J. H. Song, X. Gu, Y. Kwark, D. Kuchta, A. Rylyakov, C. Schow
This paper discusses the requirements and challenges associated with the design of electrical interconnects to support the test and evaluation of high-speed transceivers working up to 40 Gb/s. It will be shown that relatively low cost technologies such as FR-4 boards, push-on connectors, and wire bonding can effectively achieve this goal. A specific platform and its application for testing of a 40-Gb/s VCSEL-based optoelectronic link are presented.
{"title":"Electrical interconnect design for testing of high-speed IC transceivers","authors":"R. Rímolo-Donadío, C. Baks, B. Lee, J. H. Song, X. Gu, Y. Kwark, D. Kuchta, A. Rylyakov, C. Schow","doi":"10.1109/EPEPS.2012.6457842","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457842","url":null,"abstract":"This paper discusses the requirements and challenges associated with the design of electrical interconnects to support the test and evaluation of high-speed transceivers working up to 40 Gb/s. It will be shown that relatively low cost technologies such as FR-4 boards, push-on connectors, and wire bonding can effectively achieve this goal. A specific platform and its application for testing of a 40-Gb/s VCSEL-based optoelectronic link are presented.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125220201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457873
M. Kabir, R. Khazaka, R. Achar, M. Nakhla
In this paper, a new Loewner-Matrix based efficient algorithm for fast frequency sweep of S or Y parameters of highspeed modules is proposed. The new method adaptively minimizes the number of frequency point solutions leading to significant speed-up over conventional methods. The proposed method is identically applicable regardless of the solution methodology of the original simulator.
{"title":"Loewner-Matrix based efficient algorithm for frequency sweep of high-speed modules","authors":"M. Kabir, R. Khazaka, R. Achar, M. Nakhla","doi":"10.1109/EPEPS.2012.6457873","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457873","url":null,"abstract":"In this paper, a new Loewner-Matrix based efficient algorithm for fast frequency sweep of S or Y parameters of highspeed modules is proposed. The new method adaptively minimizes the number of frequency point solutions leading to significant speed-up over conventional methods. The proposed method is identically applicable regardless of the solution methodology of the original simulator.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121186028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457884
Yu-Jen Chang, Hao-Hsiang Chuang, Yi-Chang Lu, Y. Chiou, Tzong-Lin Wu, P. Chen, Shih-Hsien Wu, T. Kuo, C. Zhan, W. Lo
An equivalent circuit model to characterize the crosstalk strength in multiple TSVs is newly proposed. In this model, all the values of lumped elements in the model are given in closed-form formulas. Therefore, the computation effort for constructing the model of multiple TSVs is much lower than other previous works. The accuracy is verified by the measurement for a nine stacked silicon chips and the full-wave simulation results. The proposed model is then utilized to the design for crosstalk mitigation. With the advantages of smaller occupied area (lower cost), a rhombus-grounded Faraday cage design is recommended with lower cost and similar performance compared to conventional Faraday cage concept.
{"title":"Novel crosstalk modeling for multiple through-silicon-vias (TSV) on 3-D IC: Experimental validation and application to Faraday cage design","authors":"Yu-Jen Chang, Hao-Hsiang Chuang, Yi-Chang Lu, Y. Chiou, Tzong-Lin Wu, P. Chen, Shih-Hsien Wu, T. Kuo, C. Zhan, W. Lo","doi":"10.1109/EPEPS.2012.6457884","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457884","url":null,"abstract":"An equivalent circuit model to characterize the crosstalk strength in multiple TSVs is newly proposed. In this model, all the values of lumped elements in the model are given in closed-form formulas. Therefore, the computation effort for constructing the model of multiple TSVs is much lower than other previous works. The accuracy is verified by the measurement for a nine stacked silicon chips and the full-wave simulation results. The proposed model is then utilized to the design for crosstalk mitigation. With the advantages of smaller occupied area (lower cost), a rhombus-grounded Faraday cage design is recommended with lower cost and similar performance compared to conventional Faraday cage concept.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126067778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457840
Sung Joo Park, J. Choi, Madhavan Swaminathan
Single-ended (SE) signaling is preferable than differential signaling in high-speed memory interface designs, mainly because of less power and pin-count requirements. However, SE signaling is vulnerable to simultaneous switching noise (SSN) which is a major performance limiter. SSN is a function of the inductance of power and ground planes, which are the return paths for data signal lines. In recent literature, an assertion was posed that the impact of plane bounce on the SE signaling is not significant due to the compensation of noise by the voltage reference rail. In this paper, we set forth a counter-argument by presenting the noise analyses focusing on the impact of various voltage reference designs. In addition, we also show the decoupling method for a system using multiple voltages.
{"title":"Simultaneous switching noise analysis of reference voltage rails for pseudo differential interfaces","authors":"Sung Joo Park, J. Choi, Madhavan Swaminathan","doi":"10.1109/EPEPS.2012.6457840","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457840","url":null,"abstract":"Single-ended (SE) signaling is preferable than differential signaling in high-speed memory interface designs, mainly because of less power and pin-count requirements. However, SE signaling is vulnerable to simultaneous switching noise (SSN) which is a major performance limiter. SSN is a function of the inductance of power and ground planes, which are the return paths for data signal lines. In recent literature, an assertion was posed that the impact of plane bounce on the SE signaling is not significant due to the compensation of noise by the voltage reference rail. In this paper, we set forth a counter-argument by presenting the noise analyses focusing on the impact of various voltage reference designs. In addition, we also show the decoupling method for a system using multiple voltages.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114648940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Algorithms featuring fast and accurate estimation of worst-case eye diagram have been proposed to replace the time-consuming random bit simulation in channel design. However, when the interaction between nonlinear I/O circuits and power distribution network (PDN) noise is included, most of those approaches fail to maintain accuracy. Based on the superposition of multiple bit pattern responses (SMBP) concept, Ren and Oh [1] developed an algorithm to fast predict the eye diagram that theoretically captures any nonlinearity in the circuit. In this paper, a test circuit with PDN was constructed to examine the performance of this algorithm. The experiment results show good agreement with the results simulated by long PRBS in HSPICE.
为了取代信道设计中耗时的随机比特模拟，提出了快速准确估计最坏情况眼图的算法。然而，当考虑到非线性I/O电路和配电网络(PDN)噪声之间的相互作用时，大多数方法都无法保持精度。基于SMBP (superposition of multiple bit pattern responses)的概念，Ren和Oh[1]开发了一种快速预测眼图的算法，理论上可以捕捉电路中的任何非线性。本文构造了一个带有PDN的测试电路来检验该算法的性能。实验结果与HSPICE长PRBS模拟结果吻合较好。
{"title":"Eye prediction of digital driver with power distribution network noise","authors":"Chiu-Chih Chou, Hao-Hsiang Chuang, Tzong-Lin Wu, Shih-Hung Weng, Chung-Kuan Cheng","doi":"10.1109/EPEPS.2012.6457859","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457859","url":null,"abstract":"Algorithms featuring fast and accurate estimation of worst-case eye diagram have been proposed to replace the time-consuming random bit simulation in channel design. However, when the interaction between nonlinear I/O circuits and power distribution network (PDN) noise is included, most of those approaches fail to maintain accuracy. Based on the superposition of multiple bit pattern responses (SMBP) concept, Ren and Oh [1] developed an algorithm to fast predict the eye diagram that theoretically captures any nonlinearity in the circuit. In this paper, a test circuit with PDN was constructed to examine the performance of this algorithm. The experiment results show good agreement with the results simulated by long PRBS in HSPICE.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129746718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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