Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457897
T. Sekine, H. Asai
This paper describes a fast transient simulation technique based on a block-type leapfrog scheme for general nonlinear circuits. In existing leapfrog-based techniques, there is a restriction on dealing with nonlinear elements in the circuit. On the other hand, the block-type leapfrog scheme is suitable for the simulation of tightly coupled networks such as the equivalent circuit of multiconductor transmission lines (MTLs). In this work, we extend the block-type leapfrog scheme to incorporate generalized nonlinear elements, which have two or more terminals such as MOSFETs. The proposed method partitions the circuit into some kinds of local blocks, and locally dense and nonlinear calculations are effectively confined within each relatively-small block. Example simulations of MTLs with nonlinear drivers and terminations show that the leapfrog-based nonlinear solver is much more efficient than HSPICE.
{"title":"Nonlinear block-type leapfrog scheme for the fast simulation of multiconductor transmission lines with nonlinear drivers and terminations","authors":"T. Sekine, H. Asai","doi":"10.1109/EPEPS.2012.6457897","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457897","url":null,"abstract":"This paper describes a fast transient simulation technique based on a block-type leapfrog scheme for general nonlinear circuits. In existing leapfrog-based techniques, there is a restriction on dealing with nonlinear elements in the circuit. On the other hand, the block-type leapfrog scheme is suitable for the simulation of tightly coupled networks such as the equivalent circuit of multiconductor transmission lines (MTLs). In this work, we extend the block-type leapfrog scheme to incorporate generalized nonlinear elements, which have two or more terminals such as MOSFETs. The proposed method partitions the circuit into some kinds of local blocks, and locally dense and nonlinear calculations are effectively confined within each relatively-small block. Example simulations of MTLs with nonlinear drivers and terminations show that the leapfrog-based nonlinear solver is much more efficient than HSPICE.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114078276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457882
W. Dghais, T. Cunha, J. Pedro
The paper presents a novel extraction procedure based on the frequency domain formulation of the current-charge (I-Q) behavioral model for digital I/O buffers/drivers output admittance followed by a time domain extraction of the predriver's nonlinear dynamic functions. The large signal model's functions of the drivers' output admittance are derived from the bias-dependent scattering, or S-parameters, measurements. This easy and fast extraction method allows the accurate generation of the data-based model from automated and straightforward measurements. The extracted model's functions are implemented as lookup tables (LUTs) and the behavioral model is validated in typical SI scenario.
{"title":"A mixed-domain behavioral model's extraction for digital I/O buffers","authors":"W. Dghais, T. Cunha, J. Pedro","doi":"10.1109/EPEPS.2012.6457882","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457882","url":null,"abstract":"The paper presents a novel extraction procedure based on the frequency domain formulation of the current-charge (I-Q) behavioral model for digital I/O buffers/drivers output admittance followed by a time domain extraction of the predriver's nonlinear dynamic functions. The large signal model's functions of the drivers' output admittance are derived from the bias-dependent scattering, or S-parameters, measurements. This easy and fast extraction method allows the accurate generation of the data-based model from automated and straightforward measurements. The extracted model's functions are implemented as lookup tables (LUTs) and the behavioral model is validated in typical SI scenario.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134560882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457903
Hongsheng Xu, Jiming Song, T. Kamgaing
A novel volume integral equation for the current distribution over interconnects with arbitrary cross-sectional geometry is presented based on the free space Green's function without approximation. For very low frequency, it can be reduced to the widely-used quasi-static approximation. The quasi-static volume integral equation is not accurate enough for the calculation of current distribution. A comparison is made with the different methods known in literature to calculate the per unit length internal impedance. Detailed discussion is given for the different current distributions and the definitions with their effects to the internal impedance, either for a high frequency range or a low frequency range.
{"title":"Current distribution and internal impedance of interconnect","authors":"Hongsheng Xu, Jiming Song, T. Kamgaing","doi":"10.1109/EPEPS.2012.6457903","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457903","url":null,"abstract":"A novel volume integral equation for the current distribution over interconnects with arbitrary cross-sectional geometry is presented based on the free space Green's function without approximation. For very low frequency, it can be reduced to the widely-used quasi-static approximation. The quasi-static volume integral equation is not accurate enough for the calculation of current distribution. A comparison is made with the different methods known in literature to calculate the per unit length internal impedance. Detailed discussion is given for the different current distributions and the definitions with their effects to the internal impedance, either for a high frequency range or a low frequency range.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131017168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457899
Lisha Zhang, A. Abbaspour-Tamijani, G. Pan, H. Pan
We present design and implementation of the aperture coupling based compact system of lens enhanced phased array (LEPA) for 60 GHz band high-speed internet, data and voice channels. The LEPA is a high-directivity steerable integrated system without putting penalties on the chip size and DC power consumption. The core of a LEPA is composed of the antenna-filter-antenna (AFA) structures consisting of two layers of 15 mil-thick low-loss microwave laminates and three 18um-thick copper layers. An incident wave with proper polarization is received by the top slot in the input side, passes through a half-wave stripline resonator, and then reradiates from the bottom slot on the output side with orthogonal polarization. Vias surrounding AFA elements guarantee that no parallel plate modes are excited between the two grounds, while any surface wave modes formed on the reactive surface of the array may still contribute to the occurrence of blind scan angles and need to be suppressed.
{"title":"On aperture coupling based compact system of lens enhanced phased array","authors":"Lisha Zhang, A. Abbaspour-Tamijani, G. Pan, H. Pan","doi":"10.1109/EPEPS.2012.6457899","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457899","url":null,"abstract":"We present design and implementation of the aperture coupling based compact system of lens enhanced phased array (LEPA) for 60 GHz band high-speed internet, data and voice channels. The LEPA is a high-directivity steerable integrated system without putting penalties on the chip size and DC power consumption. The core of a LEPA is composed of the antenna-filter-antenna (AFA) structures consisting of two layers of 15 mil-thick low-loss microwave laminates and three 18um-thick copper layers. An incident wave with proper polarization is received by the top slot in the input side, passes through a half-wave stripline resonator, and then reradiates from the bottom slot on the output side with orthogonal polarization. Vias surrounding AFA elements guarantee that no parallel plate modes are excited between the two grounds, while any surface wave modes formed on the reactive surface of the array may still contribute to the occurrence of blind scan angles and need to be suppressed.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128123334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457873
M. Kabir, R. Khazaka, R. Achar, M. Nakhla
In this paper, a new Loewner-Matrix based efficient algorithm for fast frequency sweep of S or Y parameters of highspeed modules is proposed. The new method adaptively minimizes the number of frequency point solutions leading to significant speed-up over conventional methods. The proposed method is identically applicable regardless of the solution methodology of the original simulator.
{"title":"Loewner-Matrix based efficient algorithm for frequency sweep of high-speed modules","authors":"M. Kabir, R. Khazaka, R. Achar, M. Nakhla","doi":"10.1109/EPEPS.2012.6457873","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457873","url":null,"abstract":"In this paper, a new Loewner-Matrix based efficient algorithm for fast frequency sweep of S or Y parameters of highspeed modules is proposed. The new method adaptively minimizes the number of frequency point solutions leading to significant speed-up over conventional methods. The proposed method is identically applicable regardless of the solution methodology of the original simulator.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121186028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457836
Satyanarayana Telikepalli, Madhavan Swaminathan, D. Keezer
Signal and power integrity are crucial for ensuring high performance in high speed digital systems. As the operating frequency of digital systems increases, the power and ground bounce created by simultaneous switching noise (SSN) has become a limiting factor for the performance of these devices. SSN is caused by parasitic inductance that exists in the power delivery network (PDN), and voltage fluctuations on the power and ground rails can lead to reduced noise margins and can limit the maximum frequency of a digital device. A new PDN design has been suggested that achieves significantly reduced SSN [1] by replacing the power plane structure with a power transmission line (PTL). In this paper, a new power delivery scheme is shown to significantly reduce switching noise at lower power. This concept has been demonstrated through theory, simulation, and measurements.
{"title":"Minimizing simultaneous switching noise at reduced power with power transmission lines for high-speed signaling","authors":"Satyanarayana Telikepalli, Madhavan Swaminathan, D. Keezer","doi":"10.1109/EPEPS.2012.6457836","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457836","url":null,"abstract":"Signal and power integrity are crucial for ensuring high performance in high speed digital systems. As the operating frequency of digital systems increases, the power and ground bounce created by simultaneous switching noise (SSN) has become a limiting factor for the performance of these devices. SSN is caused by parasitic inductance that exists in the power delivery network (PDN), and voltage fluctuations on the power and ground rails can lead to reduced noise margins and can limit the maximum frequency of a digital device. A new PDN design has been suggested that achieves significantly reduced SSN [1] by replacing the power plane structure with a power transmission line (PTL). In this paper, a new power delivery scheme is shown to significantly reduce switching noise at lower power. This concept has been demonstrated through theory, simulation, and measurements.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129168319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457840
Sung Joo Park, J. Choi, Madhavan Swaminathan
Single-ended (SE) signaling is preferable than differential signaling in high-speed memory interface designs, mainly because of less power and pin-count requirements. However, SE signaling is vulnerable to simultaneous switching noise (SSN) which is a major performance limiter. SSN is a function of the inductance of power and ground planes, which are the return paths for data signal lines. In recent literature, an assertion was posed that the impact of plane bounce on the SE signaling is not significant due to the compensation of noise by the voltage reference rail. In this paper, we set forth a counter-argument by presenting the noise analyses focusing on the impact of various voltage reference designs. In addition, we also show the decoupling method for a system using multiple voltages.
{"title":"Simultaneous switching noise analysis of reference voltage rails for pseudo differential interfaces","authors":"Sung Joo Park, J. Choi, Madhavan Swaminathan","doi":"10.1109/EPEPS.2012.6457840","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457840","url":null,"abstract":"Single-ended (SE) signaling is preferable than differential signaling in high-speed memory interface designs, mainly because of less power and pin-count requirements. However, SE signaling is vulnerable to simultaneous switching noise (SSN) which is a major performance limiter. SSN is a function of the inductance of power and ground planes, which are the return paths for data signal lines. In recent literature, an assertion was posed that the impact of plane bounce on the SE signaling is not significant due to the compensation of noise by the voltage reference rail. In this paper, we set forth a counter-argument by presenting the noise analyses focusing on the impact of various voltage reference designs. In addition, we also show the decoupling method for a system using multiple voltages.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114648940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457910
S. Swarup, S. Tan, Zao Liu
This paper studies the thermal impact and characterization of Through Silicon Vias (TSVs) in stacked three dimensional (3D) integrated circuits (ICs) through finite-element based numerical analysis. Realistic 3D stacked ICs are built using a commercial finite-element based modeling and analysis tool, COMSOL. Thermal profiles along with thermal impact of TSVs are studied for two layer and three layer stacked IC structures under practical power inputs. Experimental results show that there is a significant temperature gradient across the stacked dies for both two layer and three layer structures. The cross-layer temperature is seen to grow rapidly from two layer structures to three layer structures with the same power and TSV densities. As a result, stacking of active layers will not be scalable as the maximum temperature can quickly reach the 105 degree Centigrade limit for CMOS technology. Elevated temperatures can make thermal-sensitive reliability issues a major challenge for 3D stacked ICs. Advanced cooling, low power design, better thermal management and new architecture techniques are hence required to keep the temperature in a safe range for stacking more layers onto the chip.
{"title":"Thermal characterization of TSV based 3D stacked ICs","authors":"S. Swarup, S. Tan, Zao Liu","doi":"10.1109/EPEPS.2012.6457910","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457910","url":null,"abstract":"This paper studies the thermal impact and characterization of Through Silicon Vias (TSVs) in stacked three dimensional (3D) integrated circuits (ICs) through finite-element based numerical analysis. Realistic 3D stacked ICs are built using a commercial finite-element based modeling and analysis tool, COMSOL. Thermal profiles along with thermal impact of TSVs are studied for two layer and three layer stacked IC structures under practical power inputs. Experimental results show that there is a significant temperature gradient across the stacked dies for both two layer and three layer structures. The cross-layer temperature is seen to grow rapidly from two layer structures to three layer structures with the same power and TSV densities. As a result, stacking of active layers will not be scalable as the maximum temperature can quickly reach the 105 degree Centigrade limit for CMOS technology. Elevated temperatures can make thermal-sensitive reliability issues a major challenge for 3D stacked ICs. Advanced cooling, low power design, better thermal management and new architecture techniques are hence required to keep the temperature in a safe range for stacking more layers onto the chip.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115168761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457842
R. Rímolo-Donadío, C. Baks, B. Lee, J. H. Song, X. Gu, Y. Kwark, D. Kuchta, A. Rylyakov, C. Schow
This paper discusses the requirements and challenges associated with the design of electrical interconnects to support the test and evaluation of high-speed transceivers working up to 40 Gb/s. It will be shown that relatively low cost technologies such as FR-4 boards, push-on connectors, and wire bonding can effectively achieve this goal. A specific platform and its application for testing of a 40-Gb/s VCSEL-based optoelectronic link are presented.
{"title":"Electrical interconnect design for testing of high-speed IC transceivers","authors":"R. Rímolo-Donadío, C. Baks, B. Lee, J. H. Song, X. Gu, Y. Kwark, D. Kuchta, A. Rylyakov, C. Schow","doi":"10.1109/EPEPS.2012.6457842","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457842","url":null,"abstract":"This paper discusses the requirements and challenges associated with the design of electrical interconnects to support the test and evaluation of high-speed transceivers working up to 40 Gb/s. It will be shown that relatively low cost technologies such as FR-4 boards, push-on connectors, and wire bonding can effectively achieve this goal. A specific platform and its application for testing of a 40-Gb/s VCSEL-based optoelectronic link are presented.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125220201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457877
Long Yang, J. Umaretiya
Crosstalk for the case that signals are separated by finite ground is intuitively explored using a set of very simple but effective models, based on the concept of transmission line theory. Both single-ended and differential cases are discussed with the principle of superposition.
{"title":"Crosstalk through finite ground","authors":"Long Yang, J. Umaretiya","doi":"10.1109/EPEPS.2012.6457877","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457877","url":null,"abstract":"Crosstalk for the case that signals are separated by finite ground is intuitively explored using a set of very simple but effective models, based on the concept of transmission line theory. Both single-ended and differential cases are discussed with the principle of superposition.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"203 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132497446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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