Pub Date : 2016-05-03DOI: 10.1109/HST.2016.7495551
Wei-Che Wang, Y. Yona, S. Diggavi, Puneet Gupta
Stability has always been one of the major limitations that constraints Physical Unclonable Function (PUF) from being put in widespread practical use. In this paper, we propose a weak PUF and a strong PUF that are both completely stable with 0% intra-distance. These PUFs are called Locally Enhanced Defectivity Physical Unclonable Function (LEDPUF). A LEDPUF is a pure functional PUF which eliminates the instability of conventional parametric PUFs, therefore no helper data, fuzzy comparator, or any kinds of correction schemes are required. The source of randomness is extracted from Directed Self Assembly (DSA) process, and connections that are permanently closed or opened are formed randomly. The weak LEDPUF is constructed by forming arrays of DSA random connections, and the strong LEDPUF is implemented by using the weak LEDPUF as the key of a keyed-hash message authentication code (HMAC). Our simulation and statistical results show that the entropy of the weak LEDPUF bits is close to ideal, and the inter-distances of both weak and strong LEDPUFs are about 50%, which means that these LEDPUFs are not only stable but also unique.
{"title":"LEDPUF: Stability-guaranteed physical unclonable functions through locally enhanced defectivity","authors":"Wei-Che Wang, Y. Yona, S. Diggavi, Puneet Gupta","doi":"10.1109/HST.2016.7495551","DOIUrl":"https://doi.org/10.1109/HST.2016.7495551","url":null,"abstract":"Stability has always been one of the major limitations that constraints Physical Unclonable Function (PUF) from being put in widespread practical use. In this paper, we propose a weak PUF and a strong PUF that are both completely stable with 0% intra-distance. These PUFs are called Locally Enhanced Defectivity Physical Unclonable Function (LEDPUF). A LEDPUF is a pure functional PUF which eliminates the instability of conventional parametric PUFs, therefore no helper data, fuzzy comparator, or any kinds of correction schemes are required. The source of randomness is extracted from Directed Self Assembly (DSA) process, and connections that are permanently closed or opened are formed randomly. The weak LEDPUF is constructed by forming arrays of DSA random connections, and the strong LEDPUF is implemented by using the weak LEDPUF as the key of a keyed-hash message authentication code (HMAC). Our simulation and statistical results show that the entropy of the weak LEDPUF bits is close to ideal, and the inter-distances of both weak and strong LEDPUFs are about 50%, which means that these LEDPUFs are not only stable but also unique.","PeriodicalId":194799,"journal":{"name":"2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133125367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-03DOI: 10.1109/HST.2016.7495582
Bradley D. Hopkins, J. Shield, Chris J. North
The trustworthiness of electronic components procured and deployed in critical infrastructure can not be guaranteed. These components may contain Hardware Trojans. Understanding the threat characteristics of these Hardware Trojans is critical to the development of future security risk mitigations. One key threat is posed by Hardware Trojans located in System Memory chips, such as those found in DIMM memory. We present a physical prototype of a Memory Hardware Trojan that only requires 230 slices, performs physical page address redirection, operates in standard systems, and can be leveraged by an unprivileged software process to bypass memory protection. We demonstrate the effectiveness of our trojan with privilege escalation and virtual machine breakout use cases. Based on our designs and experimental findings, we identify insights and discuss mitigation strategies.
{"title":"Redirecting DRAM memory pages: Examining the threat of system memory Hardware Trojans","authors":"Bradley D. Hopkins, J. Shield, Chris J. North","doi":"10.1109/HST.2016.7495582","DOIUrl":"https://doi.org/10.1109/HST.2016.7495582","url":null,"abstract":"The trustworthiness of electronic components procured and deployed in critical infrastructure can not be guaranteed. These components may contain Hardware Trojans. Understanding the threat characteristics of these Hardware Trojans is critical to the development of future security risk mitigations. One key threat is posed by Hardware Trojans located in System Memory chips, such as those found in DIMM memory. We present a physical prototype of a Memory Hardware Trojan that only requires 230 slices, performs physical page address redirection, operates in standard systems, and can be leveraged by an unprivileged software process to bypass memory protection. We demonstrate the effectiveness of our trojan with privilege escalation and virtual machine breakout use cases. Based on our designs and experimental findings, we identify insights and discuss mitigation strategies.","PeriodicalId":194799,"journal":{"name":"2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128706017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-03DOI: 10.1109/HST.2016.7495577
Liwei Zhou, Y. Makris
We introduce a hardware-based methodology for performing workload execution forensics in microprocessors. More specifically, we discuss the on-chip instrumentation required for capturing the operational profile of the Translation Lookaside Buffer (TLB), as well as an off-line machine learning approach which uses this information to identify the executed processes and reconstruct the workload. Unlike workload forensics methods implemented at the operating system (OS) and/or hypervisor level, whose data logging and monitoring mechanisms may be compromised through software attacks, this approach is implemented directly in hardware and is, therefore, immune to such attacks. The proposed method is demonstrated on an experimentation platform which consists of a 32-bit x86 architecture running Linux operating system, implemented in the Simics simulation environment. Experimental results using the Mibench workload benchmark suite reveal an overall workload identification accuracy of 96.97% at an estimated logging rate of only 5.17 KB/sec.
{"title":"Hardware-based workload forensics: Process reconstruction via TLB monitoring","authors":"Liwei Zhou, Y. Makris","doi":"10.1109/HST.2016.7495577","DOIUrl":"https://doi.org/10.1109/HST.2016.7495577","url":null,"abstract":"We introduce a hardware-based methodology for performing workload execution forensics in microprocessors. More specifically, we discuss the on-chip instrumentation required for capturing the operational profile of the Translation Lookaside Buffer (TLB), as well as an off-line machine learning approach which uses this information to identify the executed processes and reconstruct the workload. Unlike workload forensics methods implemented at the operating system (OS) and/or hypervisor level, whose data logging and monitoring mechanisms may be compromised through software attacks, this approach is implemented directly in hardware and is, therefore, immune to such attacks. The proposed method is demonstrated on an experimentation platform which consists of a 32-bit x86 architecture running Linux operating system, implemented in the Simics simulation environment. Experimental results using the Mibench workload benchmark suite reveal an overall workload identification accuracy of 96.97% at an estimated logging rate of only 5.17 KB/sec.","PeriodicalId":194799,"journal":{"name":"2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"231 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122194716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-03DOI: 10.1109/HST.2016.7495586
Luis Ramirez Rivera, Xiaofang Wang, D. Chasaki
State-of-the-art FPGAs are quickly evolving into a complete system-on-chip (SoC) platform with aggressive integration of high-performance hard processor cores, gigabytes of dedicated memory blocks, and many commonly used peripherals. As FPGAs increasingly find their way into many critical and sensitive applications, including speeding cryptographic algorithms, security concerns about themselves start mounting. Current countermeasures mostly target hardware trojans, cloning, side-channel attacks, and reverse engineering. Little attention has been devoted to securing dedicated on-chip memory blocks. Moreover, the dynamic reconfigurability nature of FPGAs makes static-only approaches less effective and less efficient. In this paper, we present the design and implementation of a runtime protection scheme for FPGA on-chip memory blocks. To secure on-chip memory inside FPGAs, careful design choices must be taken because of their very low latency and simple flat memory model. A series of rules, called security policies are made. These policies are enforced by a reference monitor who mediates the communications between the intellectual properties (IP) or modules that requires the memory, and the memory itself. The memory security scheme is an implementation of a security kernel, enforced by a series of security policies, with a specific policy algorithm which tells four security monitors to control the memory accesses between IPs and the on-chip memory inside the FPGA used. The results on a Xilinx Virtex-6 FPGA board show that the security monitors themselves are successful in preventing unauthorized accesses from IPs that are marked as “untrusted” while allowing full access from other IPs that are marked as “trusted”, without incurring on a serious area or latency penalty. Also, by preventing the access from “untrusted” IPs and marking connections as “not traversable”, the connections between the untrusted IPs and the memory that it has to share with “trusted” IPs are secured.
{"title":"A separation and protection scheme for on-chip memory blocks in FPGAs","authors":"Luis Ramirez Rivera, Xiaofang Wang, D. Chasaki","doi":"10.1109/HST.2016.7495586","DOIUrl":"https://doi.org/10.1109/HST.2016.7495586","url":null,"abstract":"State-of-the-art FPGAs are quickly evolving into a complete system-on-chip (SoC) platform with aggressive integration of high-performance hard processor cores, gigabytes of dedicated memory blocks, and many commonly used peripherals. As FPGAs increasingly find their way into many critical and sensitive applications, including speeding cryptographic algorithms, security concerns about themselves start mounting. Current countermeasures mostly target hardware trojans, cloning, side-channel attacks, and reverse engineering. Little attention has been devoted to securing dedicated on-chip memory blocks. Moreover, the dynamic reconfigurability nature of FPGAs makes static-only approaches less effective and less efficient. In this paper, we present the design and implementation of a runtime protection scheme for FPGA on-chip memory blocks. To secure on-chip memory inside FPGAs, careful design choices must be taken because of their very low latency and simple flat memory model. A series of rules, called security policies are made. These policies are enforced by a reference monitor who mediates the communications between the intellectual properties (IP) or modules that requires the memory, and the memory itself. The memory security scheme is an implementation of a security kernel, enforced by a series of security policies, with a specific policy algorithm which tells four security monitors to control the memory accesses between IPs and the on-chip memory inside the FPGA used. The results on a Xilinx Virtex-6 FPGA board show that the security monitors themselves are successful in preventing unauthorized accesses from IPs that are marked as “untrusted” while allowing full access from other IPs that are marked as “trusted”, without incurring on a serious area or latency penalty. Also, by preventing the access from “untrusted” IPs and marking connections as “not traversable”, the connections between the untrusted IPs and the memory that it has to share with “trusted” IPs are secured.","PeriodicalId":194799,"journal":{"name":"2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"467 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123050940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-03DOI: 10.1109/HST.2016.7495557
J. McDonald, Yong C. Kim, T. Andel, M. A. Forbes, J. McVicar
Polymorphic gates and circuits have been used in the past to design evolutionary components that can sense the environment. In general, polymorphic gates can change their function based on environmental properties such as temperature and power. In the modern digital logic threat landscape, adversarial reverse engineering and illegal cloning pose two risks for hardware-based applications with embedded intellectual property (IP). In this paper, we implement the concept of functional polymorphism at the design level using realized polygates and consider its application for IP protection in specific digital supply chain settings. We introduce a transformation algorithm for general circuits that utilize polygates to produce variants of a target circuit or component. We provide results of a case study analysis on traditional combinational benchmark circuits and components that illustrates efficacy of the approach for circuit watermarking and the ability to defeat adversarial reverse engineering as part of the supply chain lifecycle.
{"title":"Functional polymorphism for intellectual property protection","authors":"J. McDonald, Yong C. Kim, T. Andel, M. A. Forbes, J. McVicar","doi":"10.1109/HST.2016.7495557","DOIUrl":"https://doi.org/10.1109/HST.2016.7495557","url":null,"abstract":"Polymorphic gates and circuits have been used in the past to design evolutionary components that can sense the environment. In general, polymorphic gates can change their function based on environmental properties such as temperature and power. In the modern digital logic threat landscape, adversarial reverse engineering and illegal cloning pose two risks for hardware-based applications with embedded intellectual property (IP). In this paper, we implement the concept of functional polymorphism at the design level using realized polygates and consider its application for IP protection in specific digital supply chain settings. We introduce a transformation algorithm for general circuits that utilize polygates to produce variants of a target circuit or component. We provide results of a case study analysis on traditional combinational benchmark circuits and components that illustrates efficacy of the approach for circuit watermarking and the ability to defeat adversarial reverse engineering as part of the supply chain lifecycle.","PeriodicalId":194799,"journal":{"name":"2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121384396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-03DOI: 10.1109/HST.2016.7495579
Brent Sherman, David M. Wheeler
The security demands on development teams are growing in direct proportion to the security incidents discovered and leveraged in computer crime and cyber warfare every day. There is ongoing research to increase the effectiveness of security defect detection and penetration testing of products, but where the literature is thin, is in actual case studies that apply security assurance processes in a large-scale hardware-centric environment. This paper adds to the literature by providing an actual case study of hardware security assurance practices using a sample size of 151 projects. Furthermore, it documents and analyzes the efficacy of deploying selective automation using quantitative weighted risk ratings of the Security Development Lifecycle (SDL) to hardware projects, including strategic reuse of existing SDL collaterals for derivative projects. The evaluated methodology provided acceptable accuracy and labor savings, but the results indicate that automation focusing on assignment of a quantitative risk scoring introduces a dilution of real security concerns; instead, an approach using qualitative analysis and assignment of security assurance tasks is more beneficial.
{"title":"Hardware security risk assessment: A case study","authors":"Brent Sherman, David M. Wheeler","doi":"10.1109/HST.2016.7495579","DOIUrl":"https://doi.org/10.1109/HST.2016.7495579","url":null,"abstract":"The security demands on development teams are growing in direct proportion to the security incidents discovered and leveraged in computer crime and cyber warfare every day. There is ongoing research to increase the effectiveness of security defect detection and penetration testing of products, but where the literature is thin, is in actual case studies that apply security assurance processes in a large-scale hardware-centric environment. This paper adds to the literature by providing an actual case study of hardware security assurance practices using a sample size of 151 projects. Furthermore, it documents and analyzes the efficacy of deploying selective automation using quantitative weighted risk ratings of the Security Development Lifecycle (SDL) to hardware projects, including strategic reuse of existing SDL collaterals for derivative projects. The evaluated methodology provided acceptable accuracy and labor savings, but the results indicate that automation focusing on assignment of a quantitative risk scoring introduces a dilution of real security concerns; instead, an approach using qualitative analysis and assignment of security assurance tasks is more beneficial.","PeriodicalId":194799,"journal":{"name":"2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115631729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-03DOI: 10.1109/HST.2016.7495580
Fathi H. Amsaad, Atul Prasad Deb Nath, C. Roychaudhuri, M. Niamat
Silicon Physically Unclonable Functions (SPUFs) are delay based PUFs that exploit stochastic manufacturing process variations of Integrated Circuits (ICs) on silicon chips to construct unclonable cryptographic secret keys which are unique for each chip. One variant of SPUFs, named Ring Oscillator (RO) PUFs, is typically used for the authentication of silicon technology devices including FPGA chips. Prior research on the area of ROPUF shows that RO frequencies are affected by spatial systematic process variations and hence the generated responses are not statistically random. In addition to the negative effects of systematic variations on overall ROPUF performance, reduced randomness in the generated responses can lead to major hardware security threats. In this paper, Logarithmic and absolute Diverseness Technique (LDT), a novel security technique based on base-10 logarithm and square root of RO deviations from the global RO mean, is proposed to nullify the effects of spatial systematic variation on the response bits of a unique reconfigurable ROPUF design (r-ROPUF) and improve the reliability of the structure. The proposed technique is implemented on the data obtained from 30 Spartan 3E FPGA chips. IBM-SPSS statistical software is used to demonstrate the transformation of RO frequencies to statistically normal frequencies with high reliability through the implementation of the proposed technique. Additionally, it is shown via MATLAB simulation that the technique nullifies the effects of spatial systematic variation on the average RO frequencies extracted from four different r-ROPUF structures. Finally, the response bits generated from each r-ROPUF structure successfully passed the entire National Institute of Standards and Technology (NIST) statistical tests for randomness and exhibited true randomness and higher reliability comped to earlier techniques.
硅物理不可克隆函数是一种基于延迟的物理不可克隆函数，它利用硅芯片上集成电路(ic)的随机制造工艺变化来构造每个芯片唯一的不可克隆加密密钥。spuf的一种变体，称为环形振荡器(RO) puf，通常用于包括FPGA芯片在内的硅技术设备的认证。先前对ROPUF面积的研究表明，RO频率受空间系统过程变化的影响，因此产生的响应不是统计随机的。除了系统变化对整体ROPUF性能的负面影响外，生成响应中的随机性降低还可能导致主要的硬件安全威胁。为了消除空间系统变化对可重构ROPUF (r-ROPUF)响应位的影响，提高结构的可靠性，提出了一种基于以10为基数的RO偏离全局均值的对数和平方根的对数绝对分散技术(LDT)。该技术在30个Spartan 3E FPGA芯片上获得的数据上实现。利用IBM-SPSS统计软件演示了通过实施所提出的技术将RO频率转换为具有高可靠性的统计正态频率。此外，通过MATLAB仿真表明，该技术消除了空间系统变化对从四种不同r-ROPUF结构中提取的平均RO频率的影响。最后，每个r-ROPUF结构生成的响应位成功地通过了整个美国国家标准与技术研究所(NIST)的随机性统计测试，与早期的技术相比，显示出真正的随机性和更高的可靠性。
{"title":"A novel security technique to generate truly random and highly reliable reconfigurable ROPUF-based cryptographic keys","authors":"Fathi H. Amsaad, Atul Prasad Deb Nath, C. Roychaudhuri, M. Niamat","doi":"10.1109/HST.2016.7495580","DOIUrl":"https://doi.org/10.1109/HST.2016.7495580","url":null,"abstract":"Silicon Physically Unclonable Functions (SPUFs) are delay based PUFs that exploit stochastic manufacturing process variations of Integrated Circuits (ICs) on silicon chips to construct unclonable cryptographic secret keys which are unique for each chip. One variant of SPUFs, named Ring Oscillator (RO) PUFs, is typically used for the authentication of silicon technology devices including FPGA chips. Prior research on the area of ROPUF shows that RO frequencies are affected by spatial systematic process variations and hence the generated responses are not statistically random. In addition to the negative effects of systematic variations on overall ROPUF performance, reduced randomness in the generated responses can lead to major hardware security threats. In this paper, Logarithmic and absolute Diverseness Technique (LDT), a novel security technique based on base-10 logarithm and square root of RO deviations from the global RO mean, is proposed to nullify the effects of spatial systematic variation on the response bits of a unique reconfigurable ROPUF design (r-ROPUF) and improve the reliability of the structure. The proposed technique is implemented on the data obtained from 30 Spartan 3E FPGA chips. IBM-SPSS statistical software is used to demonstrate the transformation of RO frequencies to statistically normal frequencies with high reliability through the implementation of the proposed technique. Additionally, it is shown via MATLAB simulation that the technique nullifies the effects of spatial systematic variation on the average RO frequencies extracted from four different r-ROPUF structures. Finally, the response bits generated from each r-ROPUF structure successfully passed the entire National Institute of Standards and Technology (NIST) statistical tests for randomness and exhibited true randomness and higher reliability comped to earlier techniques.","PeriodicalId":194799,"journal":{"name":"2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127515137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-03DOI: 10.1109/HST.2016.7495584
J. Breier, Dirmanto Jap, S. Bhasin
The versatility and cost of embedded systems have made it ubiquitous. Such wide-application exposes an embedded system to a variety of physical threats like side-channel attacks (SCA) and fault attacks (FA). Recently, a couple of software encoding schemes were proposed as a protection against SCA. These protection schemes are based on dual-rail precharge logic (DPL), previously shown resistant to both SCA and FA. In this paper, we analyze the previously proposed software encoding schemes against FA. Our results show that software encoding offers only limited resistance to FA. Finally, improvement to software-encoding schemes is improved. With this improvement, software encoding can serve as a common SCA and FA counter-measure with an exploitable fault probability as low as 0.0048.
{"title":"The other side of the coin: Analyzing software encoding schemes against fault injection attacks","authors":"J. Breier, Dirmanto Jap, S. Bhasin","doi":"10.1109/HST.2016.7495584","DOIUrl":"https://doi.org/10.1109/HST.2016.7495584","url":null,"abstract":"The versatility and cost of embedded systems have made it ubiquitous. Such wide-application exposes an embedded system to a variety of physical threats like side-channel attacks (SCA) and fault attacks (FA). Recently, a couple of software encoding schemes were proposed as a protection against SCA. These protection schemes are based on dual-rail precharge logic (DPL), previously shown resistant to both SCA and FA. In this paper, we analyze the previously proposed software encoding schemes against FA. Our results show that software encoding offers only limited resistance to FA. Finally, improvement to software-encoding schemes is improved. With this improvement, software encoding can serve as a common SCA and FA counter-measure with an exploitable fault probability as low as 0.0048.","PeriodicalId":194799,"journal":{"name":"2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121988904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-03DOI: 10.1109/HST.2016.7495574
Azalia Mirhoseini, A. Sadeghi, F. Koushanfar
We present CryptoML, the first practical framework for provably secure and efficient delegation of a wide range of contemporary matrix-based machine learning (ML) applications on massive datasets. In CryptoML a delegating client with memory and computational resource constraints wishes to assign the storage and ML-related computations to the cloud servers, while preserving the privacy of its data. We first suggest the dominant components of delegation performance cost, and create a matrix sketching technique that aims at minimizing the cost by data pre-processing. We then propose a novel interactive delegation protocol based on the provably secure Shamir's secret sharing. The protocol is customized for our new sketching technique to maximize the client's resource efficiency. CryptoML shows a new trade-off between the efficiency of secure delegation and the accuracy of the ML task. Proof of concept evaluations corroborate applicability of CryptoML to datasets with billions of non-zero records.
{"title":"CryptoML: Secure outsourcing of big data machine learning applications","authors":"Azalia Mirhoseini, A. Sadeghi, F. Koushanfar","doi":"10.1109/HST.2016.7495574","DOIUrl":"https://doi.org/10.1109/HST.2016.7495574","url":null,"abstract":"We present CryptoML, the first practical framework for provably secure and efficient delegation of a wide range of contemporary matrix-based machine learning (ML) applications on massive datasets. In CryptoML a delegating client with memory and computational resource constraints wishes to assign the storage and ML-related computations to the cloud servers, while preserving the privacy of its data. We first suggest the dominant components of delegation performance cost, and create a matrix sketching technique that aims at minimizing the cost by data pre-processing. We then propose a novel interactive delegation protocol based on the provably secure Shamir's secret sharing. The protocol is customized for our new sketching technique to maximize the client's resource efficiency. CryptoML shows a new trade-off between the efficiency of secure delegation and the accuracy of the ML task. Proof of concept evaluations corroborate applicability of CryptoML to datasets with billions of non-zero records.","PeriodicalId":194799,"journal":{"name":"2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124601737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-03DOI: 10.1109/HST.2016.7495575
Qihang Shi, N. Asadizanjani, Domenic Forte, M. Tehranipoor
Microprobing attacks against integrated circuits (IC) for security critical applications have become a serious concern. With the help of modern circuit editing techniques, an attacker could remove layers of materials and expose wires carrying security critical information for probing. Existing protection methods use active shielding to detect such attacks. However, this technique has been proven to be ineffective, while layers of trigger wire mesh introduce prohibitive cost overhead. In this paper, we investigate the problem of protection against microprobing attacks and present a method to scan layout for microprobing vulnerabilities so that more secure and less costly protections can be developed. Exemplary applications on OpenSPARC T1 core layout is used to evaluate the proposed flow and substantiate findings.
{"title":"A layout-driven framework to assess vulnerability of ICs to microprobing attacks","authors":"Qihang Shi, N. Asadizanjani, Domenic Forte, M. Tehranipoor","doi":"10.1109/HST.2016.7495575","DOIUrl":"https://doi.org/10.1109/HST.2016.7495575","url":null,"abstract":"Microprobing attacks against integrated circuits (IC) for security critical applications have become a serious concern. With the help of modern circuit editing techniques, an attacker could remove layers of materials and expose wires carrying security critical information for probing. Existing protection methods use active shielding to detect such attacks. However, this technique has been proven to be ineffective, while layers of trigger wire mesh introduce prohibitive cost overhead. In this paper, we investigate the problem of protection against microprobing attacks and present a method to scan layout for microprobing vulnerabilities so that more secure and less costly protections can be developed. Exemplary applications on OpenSPARC T1 core layout is used to evaluate the proposed flow and substantiate findings.","PeriodicalId":194799,"journal":{"name":"2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129576136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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